Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,414 @@
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-------------------------------------------------------------------------------
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--
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-- Copyright 2018 Ettus Research, a National Instruments Company
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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--
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-- Purpose:
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--
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-- Uses the RP and SP edges to cross a trigger from the RefClk domain to
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-- the SampleClk domain. The RP FE captures the input trigger and sends it to
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-- the SampleClk domain. There, it is double-synchronized but only allowed to pass
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-- when the SP RE occurs. The trigger (now in the SampleClk domain) is then passed
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-- through an elastic buffer before being sent on it's merry way.
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--
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-- Below is the latency through this module. If you assert rTriggerIn before or after
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-- the rRP RE, then you need to add/subtract the distance to the rRP RE.
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--
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-- Deterministic latency through this module is (starting at the rRP RE):
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-- Measured difference between rRP and sSP rising edges (using a TDC, positive value
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-- if rRP rises before sSP).
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-- + One period of sSP
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-- + Two periods of SampleClk (Double Sync)
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-- + (sElasticBufferPtr value + 1) * SampleClk Period
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-- + One period of SampleClk
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--
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-- How much skew between RP and SP can we allow and still safely pass triggers?
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-- Our "launch" edge is essentially the RP FE, and our "latch" edge is the SP RE.
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-- Consider the no skew (RP and SP edges align) case first. Our setup and hold budget
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-- is balanced at T/2. Based on this, it seems we can tolerate almost T/2 skew in either
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-- direction (ignoring a few Reference and Sample Clock cycles here and there).
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-- My recommendation is to keep the skew to a minimum, like less than T/4.
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-- In the context of the FTDC project for N310, this should be a no-brainer since
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-- the SP pulses are started only a few RefClk cycles after RP. The skew is
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-- easily verified by taking a FTDC measurement. If the skew is less than T/4, you can
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-- sleep easy. If not, then I recommend doing a comprehensive analysis of how much
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-- settling time you have between the trigger being launched from the RefClk domain
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-- and latched in the SampleClk domain.
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--
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-- vreview_group Tdc
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library unisim;
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use unisim.vcomponents.all;
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entity CrossTrigger is
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port (
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aReset : in boolean;
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RefClk : in std_logic;
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-- For convenience while writing this, I have only considered the N3x0 case where
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-- rRP is slightly ahead of sSP in phase.
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rRP : in boolean;
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-- De-asserts the clock cycle after rTriggerIn asserts. Re-asserts after the
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-- second falling edge of rRP, indicating new triggers can be accepted.
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rReadyForInput : out boolean;
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-- Only one pulse will be output for each rising edge of rTriggerIn. rTriggerIn is
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-- ignored when rReadyForInput is de-asserted. All levels are ignored when Enable
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-- is de-asserted.
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rEnableTrigger : in boolean;
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rTriggerIn : in boolean;
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SampleClk : in std_logic;
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sSP : in boolean;
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-- An elastic buffer just before the output is used to compensate for skew
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-- in sSP pulses across boards. Default should be in the middle of the 4 bit
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-- range at 7.
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sElasticBufferPtr : in unsigned(3 downto 0);
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-- Single-cycle pulse output.
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sTriggerOut : out boolean
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);
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end CrossTrigger;
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architecture rtl of CrossTrigger is
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--vhook_sigstart
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--vhook_sigend
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signal rRpFE,
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rRpDly,
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rTriggerToSClk,
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rTriggerCaptured,
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sSpRE,
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sSpDly : boolean;
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signal sTriggerBuffer : unsigned(2**sElasticBufferPtr'length-1 downto 0);
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signal sTriggerInSClk, sTriggerInSClk_ms : boolean;
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function to_StdLogic(b : boolean) return std_ulogic is
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begin
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if b then
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return '1';
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else
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return '0';
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end if;
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end to_StdLogic;
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function to_Boolean (s : std_ulogic) return boolean is
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begin
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return (To_X01(s)='1');
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end to_Boolean;
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attribute async_reg : string;
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attribute async_reg of sTriggerInSClk : signal is "TRUE";
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attribute async_reg of sTriggerInSClk_ms : signal is "TRUE";
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begin
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-- Reference Clock Domain Trigger Capture : -------------------------------------------
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-- The trigger input is captured whenever it is high. The captured value is reset
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-- by the falling edge of rRP.
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-- ------------------------------------------------------------------------------------
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rRpFE <= rRpDly and not rRP;
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CaptureTrigger : process(aReset, RefClk)
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begin
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if aReset then
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rTriggerCaptured <= false;
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rRpDly <= false;
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elsif rising_edge(RefClk) then
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rRpDly <= rRP;
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if not rEnableTrigger then
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rTriggerCaptured <= false;
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elsif rTriggerIn then
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-- Capture trigger whenever the input is asserted (so this will work with single
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-- cycle and multi-cycle pulses).
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rTriggerCaptured <= true;
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elsif rRpFE then
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-- Reset the captured trigger one cycle after the rRP FE.
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rTriggerCaptured <= false;
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end if;
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end if;
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end process;
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-- Send Trigger To Sample Clock Domain : ----------------------------------------------
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-- Send the captured trigger on the falling edge of rRP.
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-- ------------------------------------------------------------------------------------
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SendTrigger : process(aReset, RefClk)
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begin
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if aReset then
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rTriggerToSClk <= false;
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elsif rising_edge(RefClk) then
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if not rEnableTrigger then
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rTriggerToSClk <= false;
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elsif rRpFE then
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rTriggerToSClk <= rTriggerCaptured;
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end if;
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end if;
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end process;
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rReadyForInput <= not (rTriggerToSClk or rTriggerCaptured);
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-- Capture Trigger in Sample Clock Domain : -------------------------------------------
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-- On the rising edge of sSP, capture the trigger. To keep things free of
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-- metastability, we double-sync the trigger into the SampleClk domain first.
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-- ------------------------------------------------------------------------------------
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ReceiveAndProcessTrigger : process(aReset, SampleClk)
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begin
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if aReset then
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sSpDly <= false;
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sTriggerBuffer <= (others => '0');
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sTriggerOut <= false;
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sTriggerInSClk_ms <= false;
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sTriggerInSClk <= false;
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elsif rising_edge(SampleClk) then
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-- Edge detector delays.
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sSpDly <= sSP;
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-- Double-synchronizer for trigger.
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sTriggerInSClk_ms <= rTriggerToSClk;
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sTriggerInSClk <= sTriggerInSClk_ms;
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-- Delay chain for the elastic buffer. Move to the left people! Note that this
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-- operation incurs at least one cycle of delay. Also note the trigger input is
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-- gated with the SP RE.
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sTriggerBuffer <= sTriggerBuffer(sTriggerBuffer'high-1 downto 0) &
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to_stdlogic(sTriggerInSClk and sSpRE);
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-- Based on the buffer pointer value select and flop the output one more time.
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sTriggerOut <= to_boolean(sTriggerBuffer(to_integer(sElasticBufferPtr)));
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end if;
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end process;
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-- Rising edge detectors.
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sSpRE <= sSP and not sSpDly;
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end rtl;
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--------------------------------------------------------------------------------
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-- Testbench for CrossTrigger
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--
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-- Meh coverage on the triggers so far... but this tests general operation
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-- and latency.
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--------------------------------------------------------------------------------
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--synopsys translate_off
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity tb_CrossTrigger is end tb_CrossTrigger;
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architecture test of tb_CrossTrigger is
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-- Sets up a 1.25 MHz period.
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constant kClksPerPulseMaxBits: integer := 10;
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constant kRpPeriodInRClks : integer := 8;
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constant kRpHighTimeInRClks : integer := 4;
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constant kSpPeriodInRClks : integer := 100;
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constant kSpHighTimeInRClks : integer := 50;
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--vhook_sigstart
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signal aReset: boolean;
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signal RefClk: std_logic := '0';
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signal rEnablePulser: boolean;
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signal rEnableTrigger: boolean;
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signal rReadyForInput: boolean;
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signal rRP: boolean;
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signal rTriggerIn: boolean;
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signal SampleClk: std_logic := '0';
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signal sElasticBufferPtr: unsigned(3 downto 0);
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signal sEnablePulser: boolean;
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signal sSP: boolean;
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signal sTriggerOut: boolean;
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--vhook_sigend
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signal StopSim : boolean;
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-- shared variable Rand : Random_t;
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constant kSPer : time := 8.000 ns; -- 125.00 MHz
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constant kRPer : time := 100.000 ns; -- 10.00 MHz
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signal rRfiExpected: boolean:= true;
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signal sTriggerOutExpected: boolean:= false;
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procedure ClkWait(
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signal Clk : in std_logic;
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X : positive := 1) is
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begin
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for i in 1 to X loop
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wait until rising_edge(Clk);
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end loop;
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end procedure ClkWait;
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begin
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SampleClk <= not SampleClk after kSPer/2 when not StopSim else '0';
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RefClk <= not RefClk after kRPer/2 when not StopSim else '0';
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--vhook_e Pulser RpPulser
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--vhook_a Clk RefClk
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--vhook_a cLoadLimits true
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--vhook_a cPeriod to_unsigned(kRpPeriodInRClks,kClksPerPulseMaxBits)
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--vhook_a cHighTime to_unsigned(kRpHighTimeInRClks,kClksPerPulseMaxBits)
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--vhook_a cEnablePulse rEnablePulser
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--vhook_a cPulse rRP
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RpPulser: entity work.Pulser (rtl)
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generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16
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port map (
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aReset => aReset, --in boolean
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Clk => RefClk, --in std_logic
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cLoadLimits => true, --in boolean
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cPeriod => to_unsigned(kRpPeriodInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0)
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cHighTime => to_unsigned(kRpHighTimeInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0)
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cEnablePulse => rEnablePulser, --in boolean
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cPulse => rRP); --out boolean
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--vhook_e Pulser SpPulser
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--vhook_a Clk SampleClk
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--vhook_a cLoadLimits true
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--vhook_a cPeriod to_unsigned(kSpPeriodInRClks,kClksPerPulseMaxBits)
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--vhook_a cHighTime to_unsigned(kSpHighTimeInRClks,kClksPerPulseMaxBits)
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--vhook_a cEnablePulse sEnablePulser
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--vhook_a cPulse sSP
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SpPulser: entity work.Pulser (rtl)
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generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16
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port map (
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aReset => aReset, --in boolean
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Clk => SampleClk, --in std_logic
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cLoadLimits => true, --in boolean
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cPeriod => to_unsigned(kSpPeriodInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0)
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cHighTime => to_unsigned(kSpHighTimeInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0)
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cEnablePulse => sEnablePulser, --in boolean
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cPulse => sSP); --out boolean
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main: process
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procedure SendTrigger is
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begin
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assert rReadyForInput
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report "RFI isn't high, so we can't issue a trigger" severity error;
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-- Give it some action. We need to ideally test this for every phase offset of
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-- rTriggerIn with respect to the rising edge of rRP, but let's get to that later.
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-- For now, wait until a rising edge on rRP and then wait for most of the period
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-- to issue the trigger.
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wait until rRP and not rRP'delayed;
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wait for (kRpPeriodInRClks-3)*kRPer;
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rTriggerIn <= true;
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ClkWait(RefClk);
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rTriggerIn <= false;
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rRfiExpected <= false;
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-- At this point, we wait until a sSP RE, plus two SampleClks, plus sElasticBufferPtr
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-- plus 1 worth of SampleClks, plus one more SampleClk, and then the trigger
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-- should appear.
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wait until not rRP and rRP'delayed;
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wait until sSP and not sSP'delayed;
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ClkWait(SampleClk,1);
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ClkWait(SampleClk, to_integer(sElasticBufferPtr)+1);
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sTriggerOutExpected <= true;
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ClkWait(SampleClk,1);
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sTriggerOutExpected <= false;
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wait until not rRP and rRP'delayed;
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ClkWait(RefClk,1);
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rRfiExpected <= true;
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end procedure SendTrigger;
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begin
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rEnablePulser <= false;
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sEnablePulser <= false;
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rEnableTrigger <= true;
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sElasticBufferPtr <= to_unsigned(7, sElasticBufferPtr'length);
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aReset <= true, false after 10 ns;
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ClkWait(RefClk,5);
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-- Start up the pulsers and ensure nothing comes out of the trigger for a while.
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rEnablePulser <= true;
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ClkWait(RefClk, 3);
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ClkWait(SampleClk, 2);
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sEnablePulser <= true;
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ClkWait(RefClk, kRpPeriodInRClks*5);
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assert (not sTriggerOut) and sTriggerOut'stable(kRpPeriodInRClks*5*kRPer)
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report "Rogue activity on sTriggerOut before rTriggerIn asserted!" severity error;
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assert (rReadyForInput) and rReadyForInput'stable(kRpPeriodInRClks*5*kRPer)
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report "Ready for Input was not high before trigger!" severity error;
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SendTrigger;
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ClkWait(RefClk, kRpPeriodInRClks*5);
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SendTrigger;
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ClkWait(RefClk, kRpPeriodInRClks*5);
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-- Turn off the trigger enable and send a trigger.
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rEnableTrigger <= false;
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ClkWait(RefClk);
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rTriggerIn <= true;
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ClkWait(RefClk);
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rTriggerIn <= false;
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-- And nothing should happen.
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ClkWait(RefClk, kRpPeriodInRClks*5);
|
||||
assert (not sTriggerOut) and sTriggerOut'stable(kRpPeriodInRClks*5*kRPer)
|
||||
report "Rogue activity on sTriggerOut before rTriggerIn asserted!" severity error;
|
||||
|
||||
|
||||
ClkWait(RefClk, kRpPeriodInRClks*5);
|
||||
StopSim <= true;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
|
||||
CheckRfi : process(RefClk)
|
||||
begin
|
||||
if falling_edge(RefClk) then
|
||||
assert rReadyForInput = rRfiExpected
|
||||
report "RFI didn't match expected" severity error;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
CheckTrigOut : process(SampleClk)
|
||||
begin
|
||||
if falling_edge(SampleClk) then
|
||||
assert sTriggerOut = sTriggerOutExpected
|
||||
report "Trigger Out didn't match expected" severity error;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
--vhook_e CrossTrigger dutx
|
||||
dutx: entity work.CrossTrigger (rtl)
|
||||
port map (
|
||||
aReset => aReset, --in boolean
|
||||
RefClk => RefClk, --in std_logic
|
||||
rRP => rRP, --in boolean
|
||||
rReadyForInput => rReadyForInput, --out boolean
|
||||
rEnableTrigger => rEnableTrigger, --in boolean
|
||||
rTriggerIn => rTriggerIn, --in boolean
|
||||
SampleClk => SampleClk, --in std_logic
|
||||
sSP => sSP, --in boolean
|
||||
sElasticBufferPtr => sElasticBufferPtr, --in unsigned(3:0)
|
||||
sTriggerOut => sTriggerOut); --out boolean
|
||||
|
||||
|
||||
end test;
|
||||
--synopsys translate_on
|
||||
@@ -0,0 +1,362 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Copyright 2018 Ettus Research, a National Instruments Company
|
||||
--
|
||||
-- SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
--
|
||||
--
|
||||
-- Purpose:
|
||||
--
|
||||
-- The purpose of this module is to create a psuedo-clock "pulse" on the output
|
||||
-- cPulse whenever cEnablePulse is asserted.
|
||||
--
|
||||
-- The output period and high time are determined by the inputs cPeriod and
|
||||
-- cHighTime, where cPeriod must be greater than cHighTime+2. When these values
|
||||
-- are valid at the inputs, pulse cLoadLimits to load them into the pulser routine.
|
||||
-- It is not recommended to leave cEnablePulse asserted when loading new limits.
|
||||
--
|
||||
-- Dynamic period and duty cycle setup:
|
||||
-- 1) Disable the pulser by de-asserting cEnablePulse.
|
||||
-- 2) Load new period and duty cycle by modifying cPeriod and cHighTime. Pulse
|
||||
-- cLoadLimits for at least one Clk cycle.
|
||||
-- 3) Enable the pulser by asserting cEnablePulse.
|
||||
-- 4) Repeat 1-3 as necessary.
|
||||
--
|
||||
-- Static period and duty cycle setup:
|
||||
-- 1) Tie cLoadLimits to asserted.
|
||||
-- 2) Tie cPeriod and cHighTime to static values.
|
||||
-- 3) Enable and disable the pulser by asserting and de-asserting cEnablePulser at will.
|
||||
-- This input can also be tied asserted in this case.
|
||||
--
|
||||
-- vreview_group Tdc
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
entity Pulser is
|
||||
generic (
|
||||
-- The pulse counter is kClksPerPulseMaxBits wide.
|
||||
-- Why 16? Then both cPeriod and cHighTime fit nicely into one 32 bit register!
|
||||
-- Minimum of 3 to make our default values for cHighTime work out.
|
||||
kClksPerPulseMaxBits : integer range 3 to 32 := 16
|
||||
);
|
||||
port (
|
||||
aReset : in boolean;
|
||||
Clk : in std_logic;
|
||||
|
||||
-- Pulse cLoadLimits when cPeriod and cHighTime are valid. Is it not recommended to
|
||||
-- load new limits when the output is enabled.
|
||||
-- Alternatively, cLoadLimits can be tied high if cPeriod and cHighTime are also
|
||||
-- tied to static values.
|
||||
cLoadLimits : in boolean;
|
||||
cPeriod : in unsigned(kClksPerPulseMaxBits - 1 downto 0);
|
||||
cHighTime : in unsigned(kClksPerPulseMaxBits - 1 downto 0);
|
||||
|
||||
-- When cEnablePulse is de-asserted, cPulse idles low on the following cycle.
|
||||
-- When asserted, cPulse will then assert within a few cycles.
|
||||
-- This input can be tied high, if desired, and the pulses will start several
|
||||
-- clock cycles after aReset de-assertion.
|
||||
cEnablePulse : in boolean;
|
||||
|
||||
-- When cEnablePulse is asserted, cPulse will produce a rising edge every
|
||||
-- cPeriod of the Clk input and a falling edge cHighTime cycles after
|
||||
-- the rising edge.
|
||||
cPulse : out boolean
|
||||
);
|
||||
end Pulser;
|
||||
|
||||
|
||||
architecture rtl of Pulser is
|
||||
|
||||
signal cCounter,
|
||||
cPeriodStored,
|
||||
cHighTimeStored : unsigned(cPeriod'range);
|
||||
|
||||
signal cSafeToStart_ms, cSafeToStart, cSafeToStartDly : boolean;
|
||||
|
||||
attribute ASYNC_REG : string;
|
||||
attribute ASYNC_REG of cSafeToStart_ms : signal is "true";
|
||||
attribute ASYNC_REG of cSafeToStart : signal is "true";
|
||||
|
||||
begin
|
||||
|
||||
--synthesis translate_off
|
||||
CheckInputRanges : process(Clk)
|
||||
begin
|
||||
if falling_edge(Clk) then
|
||||
-- +2 since we have the output high offset from the zero of the counter
|
||||
assert (cPeriodStored > cHighTimeStored + 2)
|
||||
report "cPeriod is not greater than cHighTime + 2" severity error;
|
||||
-- Ensure the high time is greater than 1...
|
||||
assert (cHighTimeStored > 1)
|
||||
report "cHighTime is not greater than 1" severity error;
|
||||
end if;
|
||||
end process;
|
||||
--synthesis translate_on
|
||||
|
||||
|
||||
-- ------------------------------------------------------------------------------------
|
||||
-- !!! SAFE COUNTER STARTUP !!!
|
||||
-- This counter starts safely, meaning it cannot start counting immediately after
|
||||
-- aReset de-assertion, because the counter cannot start until cSafeToStart asserts,
|
||||
-- which cannot happen until 1-2 clock cycles after aReset de-assertion.
|
||||
-- ------------------------------------------------------------------------------------
|
||||
CountFreqRefPeriod: process(aReset, Clk)
|
||||
begin
|
||||
if aReset then
|
||||
cCounter <= (others => '0');
|
||||
cSafeToStart_ms <= false;
|
||||
cSafeToStart <= false;
|
||||
cSafeToStartDly <= false;
|
||||
cPulse <= false;
|
||||
cPeriodStored <= (others => '1');
|
||||
-- This is a rather arbitrary start value, but we are guaranteed that it is
|
||||
-- less than the reset value of cPeriodStored as well as greater than 2,
|
||||
-- so it works well enough in case the module isn't set up correctly.
|
||||
cHighTimeStored <= to_unsigned(kClksPerPulseMaxBits+2,cHighTimeStored'length);
|
||||
elsif rising_edge(Clk) then
|
||||
-- Create a safe counter startup signal that asserts shortly after
|
||||
-- aReset de-assertion.
|
||||
cSafeToStart_ms <= true;
|
||||
cSafeToStart <= cSafeToStart_ms;
|
||||
-- In the case where cLoadLimits and cEnablePulse are tied high, we need to give
|
||||
-- them one cycle to load before starting the counter, so we delay cSafeToStart
|
||||
-- by one for the counter.
|
||||
cSafeToStartDly <= cSafeToStart;
|
||||
|
||||
if cEnablePulse and cSafeToStartDly then
|
||||
-- Simple counter increment until ceiling reached, then roll over.
|
||||
if cCounter >= cPeriodStored - 1 then
|
||||
cCounter <= (others => '0');
|
||||
else
|
||||
cCounter <= cCounter + 1;
|
||||
end if;
|
||||
|
||||
-- Pulse the output when counter is between 1 and cHighTimeStored.
|
||||
if cCounter = 1 then
|
||||
cPulse <= true;
|
||||
elsif cCounter >= cHighTimeStored+1 then
|
||||
cPulse <= false;
|
||||
end if;
|
||||
|
||||
else
|
||||
cPulse <= false;
|
||||
cCounter <= (others => '0');
|
||||
end if;
|
||||
|
||||
if cLoadLimits and cSafeToStart then
|
||||
cPeriodStored <= cPeriod;
|
||||
cHighTimeStored <= cHighTime;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end rtl;
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Testbench for Pulser
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--synopsys translate_off
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
entity tb_Pulser is end tb_Pulser;
|
||||
|
||||
architecture test of tb_Pulser is
|
||||
|
||||
constant kClksPerPulseMaxBits : integer := 16;
|
||||
|
||||
--vhook_sigstart
|
||||
signal aReset: boolean;
|
||||
signal cEnablePulse: boolean;
|
||||
signal cHighTime: unsigned(kClksPerPulseMaxBits-1 downto 0);
|
||||
signal Clk: std_logic := '0';
|
||||
signal cLoadLimits: boolean;
|
||||
signal cPeriod: unsigned(kClksPerPulseMaxBits-1 downto 0);
|
||||
signal cPulse: boolean;
|
||||
signal cPulseDut2: boolean;
|
||||
--vhook_sigend
|
||||
|
||||
signal StopSim : boolean;
|
||||
constant kPer : time := 10 ns;
|
||||
|
||||
signal CheckPulse : boolean := false;
|
||||
signal cPulseSl : std_logic := '0';
|
||||
signal cPulseDut2Sl : std_logic := '0';
|
||||
|
||||
procedure ClkWait(X : positive := 1) is
|
||||
begin
|
||||
for i in 1 to X loop
|
||||
wait until rising_edge(Clk);
|
||||
end loop;
|
||||
end procedure ClkWait;
|
||||
|
||||
begin
|
||||
|
||||
Clk <= not Clk after kPer/2 when not StopSim else '0';
|
||||
|
||||
main: process
|
||||
begin
|
||||
cEnablePulse <= false;
|
||||
aReset <= true, false after 10 ns;
|
||||
ClkWait(5);
|
||||
|
||||
-- Ensure the pulse is quiet for a while.
|
||||
ClkWait(100);
|
||||
assert cPulse'stable(kPer*100) and not cPulse
|
||||
report "pulse not stable at false at startup"
|
||||
severity error;
|
||||
|
||||
|
||||
-- Set up, then enable the pulse; expect it to go high after a few cycles.
|
||||
cPeriod <= to_unsigned(250,cPeriod'length);
|
||||
cHighTime <= to_unsigned(100,cPeriod'length);
|
||||
cLoadLimits <= true;
|
||||
ClkWait;
|
||||
cLoadLimits <= false;
|
||||
cEnablePulse <= true;
|
||||
ClkWait(2); -- pulse rises here
|
||||
wait until falling_edge(Clk);
|
||||
assert cPulse report "cPulse not high two cycles after enabling" severity error;
|
||||
-- After another clock cycle the checker below should be primed, so we can enable it.
|
||||
ClkWait;
|
||||
CheckPulse <= true;
|
||||
ClkWait(to_integer(cHighTime)-1);
|
||||
wait until falling_edge(Clk);
|
||||
assert not cPulse report "Pulse not low after high requirement" severity error;
|
||||
|
||||
-- Check the pulse high and low for a few cycles (duplicated below, but this also
|
||||
-- checks that it actually is toggling).
|
||||
for i in 0 to 100 loop
|
||||
ClkWait(to_integer(cPeriod) - to_integer(cHighTime));
|
||||
wait until falling_edge(Clk);
|
||||
assert cPulse report "Pulse not high when expected" severity error;
|
||||
ClkWait(to_integer(cHighTime));
|
||||
wait until falling_edge(Clk);
|
||||
assert not cPulse report "Pulse not low after high requirement" severity error;
|
||||
end loop;
|
||||
|
||||
-- Disable pulse, and check that it goes away for a long time
|
||||
cEnablePulse <= false;
|
||||
CheckPulse <= false;
|
||||
-- 2 is about the max time for it to go away.
|
||||
ClkWait(2);
|
||||
ClkWait(2**kClksPerPulseMaxBits);
|
||||
assert (not cPulse) and cPulse'stable(2**kClksPerPulseMaxBits*kPer)
|
||||
report "disable didn't work" severity error;
|
||||
|
||||
|
||||
-- Re-do all the initial tests with different periods and such.
|
||||
|
||||
-- Enable the pulse, expect it to go high after a few cycles
|
||||
cPeriod <= to_unsigned(10,cPeriod'length);
|
||||
cHighTime <= to_unsigned(5,cPeriod'length);
|
||||
cLoadLimits <= true;
|
||||
ClkWait;
|
||||
cLoadLimits <= false;
|
||||
cEnablePulse <= true;
|
||||
ClkWait(2); -- pulse rises here
|
||||
wait until falling_edge(Clk);
|
||||
assert cPulse report "cPulse not high two cycles after enabling" severity error;
|
||||
-- After another clock cycle the checker below should be primed, so we can enable it.
|
||||
ClkWait;
|
||||
CheckPulse <= true;
|
||||
ClkWait(to_integer(cHighTime)-1);
|
||||
wait until falling_edge(Clk);
|
||||
assert not cPulse report "Pulse not low after high requirement" severity error;
|
||||
|
||||
-- Check the pulse high and low for a few cycles (duplicated below, but this also
|
||||
-- checks that it actually is toggling).
|
||||
for i in 0 to 100 loop
|
||||
ClkWait(to_integer(cPeriod) - to_integer(cHighTime));
|
||||
wait until falling_edge(Clk);
|
||||
assert cPulse report "Pulse not high when expected" severity error;
|
||||
ClkWait(to_integer(cHighTime));
|
||||
wait until falling_edge(Clk);
|
||||
assert not cPulse report "Pulse not low after high requirement" severity error;
|
||||
end loop;
|
||||
|
||||
ClkWait(100);
|
||||
|
||||
|
||||
StopSim <= true;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
cPulseSl <= '1' when cPulse else '0';
|
||||
|
||||
-- Test the period and duty cycle of the pulse.
|
||||
CheckPulseSpecs : process(cPulseSl)
|
||||
variable LastRise : time := 0 ns;
|
||||
begin
|
||||
if falling_edge(cPulseSl) then
|
||||
assert (not CheckPulse) or (now - LastRise = kPer*to_integer(cHighTime))
|
||||
report "High cycles requirement not met" severity error;
|
||||
elsif rising_edge(cPulseSl) then
|
||||
assert (not CheckPulse) or (now - LastRise = kPer*to_integer(cPeriod))
|
||||
report "Period requirement not met" & LF &
|
||||
"Act: " & time'image(now-LastRise) & LF &
|
||||
"Req: " & time'image(kPer*to_integer(cPeriod))
|
||||
severity error;
|
||||
LastRise := now;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--vhook_e Pulser dutx
|
||||
dutx: entity work.Pulser (rtl)
|
||||
generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16
|
||||
port map (
|
||||
aReset => aReset, --in boolean
|
||||
Clk => Clk, --in std_logic
|
||||
cLoadLimits => cLoadLimits, --in boolean
|
||||
cPeriod => cPeriod, --in unsigned(kClksPerPulseMaxBits-1:0)
|
||||
cHighTime => cHighTime, --in unsigned(kClksPerPulseMaxBits-1:0)
|
||||
cEnablePulse => cEnablePulse, --in boolean
|
||||
cPulse => cPulse); --out boolean
|
||||
|
||||
|
||||
--vhook_e Pulser dut2
|
||||
--vhook_a cLoadLimits true
|
||||
--vhook_a cPeriod to_unsigned(5,kClksPerPulseMaxBits)
|
||||
--vhook_a cHighTime to_unsigned(2,kClksPerPulseMaxBits)
|
||||
--vhook_a cEnablePulse true
|
||||
--vhook_a cPulse cPulseDut2
|
||||
dut2: entity work.Pulser (rtl)
|
||||
generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16
|
||||
port map (
|
||||
aReset => aReset, --in boolean
|
||||
Clk => Clk, --in std_logic
|
||||
cLoadLimits => true, --in boolean
|
||||
cPeriod => to_unsigned(5,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0)
|
||||
cHighTime => to_unsigned(2,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0)
|
||||
cEnablePulse => true, --in boolean
|
||||
cPulse => cPulseDut2); --out boolean
|
||||
|
||||
cPulseDut2Sl <= '1' when cPulseDut2 else '0';
|
||||
|
||||
CheckDut2 : process (cPulseDut2Sl)
|
||||
variable LastRise : time := 0 ns;
|
||||
begin
|
||||
if falling_edge(cPulseDut2Sl) then
|
||||
assert (not CheckPulse) or (now - LastRise = kPer*2)
|
||||
report "DUT 2 High cycles requirement not met" severity error;
|
||||
elsif rising_edge(cPulseDut2Sl) then
|
||||
assert (not CheckPulse) or (now - LastRise = kPer*5)
|
||||
report "DUT 2 Period requirement not met" & LF &
|
||||
"Act: " & time'image(now-LastRise) & LF &
|
||||
"Req: " & time'image(kPer*5)
|
||||
severity error;
|
||||
LastRise := now;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end test;
|
||||
--synopsys translate_on
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,397 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Copyright 2018 Ettus Research, a National Instruments Company
|
||||
--
|
||||
-- SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
--
|
||||
--
|
||||
-- Purpose:
|
||||
--
|
||||
-- Wrapper for the TDC and register control modules.
|
||||
--
|
||||
-- vreview_group Tdc
|
||||
-- vreview_reviewers dabaker sgupta jmarsar
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.PkgRegs.all;
|
||||
|
||||
entity TdcWrapper is
|
||||
port (
|
||||
-- Clocks and Resets : --------------------------------------------------------------
|
||||
-- Bus Clock and synchronous bus reset.
|
||||
BusClk : in std_logic;
|
||||
bBusReset : in std_logic;
|
||||
-- Reference Clock
|
||||
RefClk : in std_logic;
|
||||
-- Sample Clock
|
||||
SampleClk : in std_logic;
|
||||
-- Measurement Clock must run at a very specific frequency, determined by the
|
||||
-- SampleClk, RefClk, and Sync Pulse rates... oh and a lot of math.
|
||||
MeasClk : in std_logic;
|
||||
|
||||
|
||||
-- Register Port: -------------------------------------------------------------------
|
||||
bSyncRegPortOut : out RegPortOut_t;
|
||||
bSyncRegPortIn : in RegPortIn_t;
|
||||
|
||||
|
||||
-- PPS In and Out : -----------------------------------------------------------------
|
||||
-- Only required to pulse 1 RefClk cycle.
|
||||
rPpsPulse : in std_logic;
|
||||
-- PPS pulse output on the SampleClk domain.
|
||||
sPpsPulse : out std_logic;
|
||||
|
||||
|
||||
-- Sync Pulse Outputs : -------------------------------------------------------------
|
||||
-- The repeating pulses can be useful for many things, including passing triggers.
|
||||
rRpTransfer : out std_logic;
|
||||
sSpTransfer : out std_logic;
|
||||
|
||||
-- Pin bouncers out and in. Must go to unused and unconnected pins on the FPGA!
|
||||
rGatedPulseToPin : inout std_logic;
|
||||
sGatedPulseToPin : inout std_logic
|
||||
);
|
||||
end TdcWrapper;
|
||||
|
||||
|
||||
architecture struct of TdcWrapper is
|
||||
|
||||
component SyncRegsIfc
|
||||
port (
|
||||
aBusReset : in std_logic;
|
||||
bBusReset : in std_logic;
|
||||
BusClk : in std_logic;
|
||||
aTdcReset : out std_logic;
|
||||
bRegPortInFlat : in std_logic_vector(49 downto 0);
|
||||
bRegPortOutFlat : out std_logic_vector(33 downto 0);
|
||||
RefClk : in std_logic;
|
||||
rResetTdc : out std_logic;
|
||||
rResetTdcDone : in std_logic;
|
||||
rEnableTdc : out std_logic;
|
||||
rReRunEnable : out std_logic;
|
||||
rEnablePpsCrossing : out std_logic;
|
||||
rPpsPulseCaptured : in std_logic;
|
||||
rPulserEnableDelayVal : out std_logic_vector(3 downto 0);
|
||||
SampleClk : in std_logic;
|
||||
sPpsClkCrossDelayVal : out std_logic_vector(3 downto 0);
|
||||
MeasClk : in std_logic;
|
||||
mRpOffset : in std_logic_vector(39 downto 0);
|
||||
mSpOffset : in std_logic_vector(39 downto 0);
|
||||
mOffsetsDone : in std_logic;
|
||||
mOffsetsValid : in std_logic;
|
||||
rLoadRePulseCounts : out std_logic;
|
||||
rRePulsePeriodInRClks : out std_logic_vector(23 downto 0);
|
||||
rRePulseHighTimeInRClks : out std_logic_vector(23 downto 0);
|
||||
rLoadRpCounts : out std_logic;
|
||||
rRpPeriodInRClks : out std_logic_vector(15 downto 0);
|
||||
rRpHighTimeInRClks : out std_logic_vector(15 downto 0);
|
||||
rLoadRptCounts : out std_logic;
|
||||
rRptPeriodInRClks : out std_logic_vector(15 downto 0);
|
||||
rRptHighTimeInRClks : out std_logic_vector(15 downto 0);
|
||||
sLoadSpCounts : out std_logic;
|
||||
sSpPeriodInSClks : out std_logic_vector(15 downto 0);
|
||||
sSpHighTimeInSClks : out std_logic_vector(15 downto 0);
|
||||
sLoadSptCounts : out std_logic;
|
||||
sSptPeriodInSClks : out std_logic_vector(15 downto 0);
|
||||
sSptHighTimeInSClks : out std_logic_vector(15 downto 0));
|
||||
end component;
|
||||
|
||||
-- Generic values for the TdcTop instantiation below. These generics are the maximum
|
||||
-- of possible values for all combinations of Sample and Reference clocks for the N3xx
|
||||
-- family of devices.
|
||||
constant kRClksPerRePulsePeriodBitsMax : integer := 24;
|
||||
constant kRClksPerRpPeriodBitsMax : integer := 16;
|
||||
constant kSClksPerSpPeriodBitsMax : integer := 16;
|
||||
constant kPulsePeriodCntSize : integer := 13;
|
||||
-- The following are ideal values for balancing measurement time and accuracy, based
|
||||
-- on calcs given in the spec doc.
|
||||
constant kFreqRefPeriodsToCheckSize : integer := 17;
|
||||
constant kSyncPeriodsToStampSize : integer := 10;
|
||||
|
||||
--vhook_sigstart
|
||||
signal aTdcReset: std_logic;
|
||||
signal bSyncRegPortInFlat: std_logic_vector(49 downto 0);
|
||||
signal bSyncRegPortOutFlat: std_logic_vector(33 downto 0);
|
||||
signal mOffsetsDone: boolean;
|
||||
signal mOffsetsValid: boolean;
|
||||
signal mRpOffset: unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0);
|
||||
signal mSpOffset: unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0);
|
||||
signal rEnablePpsCrossing: std_logic;
|
||||
signal rEnableTdc: std_logic;
|
||||
signal rLoadRePulseCounts: std_logic;
|
||||
signal rLoadRpCounts: std_logic;
|
||||
signal rLoadRptCounts: std_logic;
|
||||
signal rPpsPulseCaptured: boolean;
|
||||
signal rPulserEnableDelayVal: std_logic_vector(3 downto 0);
|
||||
signal rRePulseHighTimeInRClks: std_logic_vector(kRClksPerRePulsePeriodBitsMax-1 downto 0);
|
||||
signal rRePulsePeriodInRClks: std_logic_vector(kRClksPerRePulsePeriodBitsMax-1 downto 0);
|
||||
signal rReRunEnable: std_logic;
|
||||
signal rResetTdc: std_logic;
|
||||
signal rResetTdcDone: boolean;
|
||||
signal rRpHighTimeInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0);
|
||||
signal rRpPeriodInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0);
|
||||
signal rRptHighTimeInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0);
|
||||
signal rRptPeriodInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0);
|
||||
signal rRpTransferBool: boolean;
|
||||
signal sLoadSpCounts: std_logic;
|
||||
signal sLoadSptCounts: std_logic;
|
||||
signal sPpsClkCrossDelayVal: std_logic_vector(3 downto 0);
|
||||
signal sPpsPulseAsyncReset: boolean;
|
||||
signal sSpHighTimeInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0);
|
||||
signal sSpPeriodInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0);
|
||||
signal sSptHighTimeInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0);
|
||||
signal sSptPeriodInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0);
|
||||
signal sSpTransferBool: boolean;
|
||||
--vhook_sigend
|
||||
|
||||
signal rPpsPulseAsyncReset_ms, rPpsPulseAsyncReset,
|
||||
sPpsPulseOut_ms, sPpsPulseOut : std_logic := '0';
|
||||
|
||||
function to_StdLogic(b : boolean) return std_ulogic is
|
||||
begin
|
||||
if b then
|
||||
return '1';
|
||||
else
|
||||
return '0';
|
||||
end if;
|
||||
end to_StdLogic;
|
||||
|
||||
function to_Boolean (s : std_ulogic) return boolean is
|
||||
begin
|
||||
return (To_X01(s)='1');
|
||||
end to_Boolean;
|
||||
|
||||
attribute ASYNC_REG : string;
|
||||
attribute ASYNC_REG of rPpsPulseAsyncReset_ms : signal is "true";
|
||||
attribute ASYNC_REG of rPpsPulseAsyncReset : signal is "true";
|
||||
attribute ASYNC_REG of sPpsPulseOut_ms : signal is "true";
|
||||
attribute ASYNC_REG of sPpsPulseOut : signal is "true";
|
||||
|
||||
begin
|
||||
|
||||
-- Cross the PPS from the no-reset domain into the aTdcReset domain since there is a
|
||||
-- reset crossing going into the TdcWrapper (reset by aTdcReset)! No clock domain
|
||||
-- crossing here, so crossing a single-cycle pulse is safe.
|
||||
DoubleSyncToAsyncReset : process (aTdcReset, RefClk)
|
||||
begin
|
||||
if to_boolean(aTdcReset) then
|
||||
rPpsPulseAsyncReset_ms <= '0';
|
||||
rPpsPulseAsyncReset <= '0';
|
||||
elsif rising_edge(RefClk) then
|
||||
rPpsPulseAsyncReset_ms <= rPpsPulse;
|
||||
rPpsPulseAsyncReset <= rPpsPulseAsyncReset_ms;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- In a similar fashion, cross the output PPS trigger from the async aTdcReset domain
|
||||
-- to the no-reset of the rest of the design. The odds of this signal triggering a
|
||||
-- failure are astronomically low (since it only pulses one clock cycle per second),
|
||||
-- but two flops is worth the assurance it won't mess something else up downstream.
|
||||
-- Note this double-sync mainly protects against the reset assertion case, since in the
|
||||
-- de-assertion case sPpsPulseAsyncReset should be zero and not transition for a long
|
||||
-- time afterwards. Again no clock crossing here, so crossing a single-cycle pulse
|
||||
-- is safe.
|
||||
DoubleSyncToNoReset : process (SampleClk)
|
||||
begin
|
||||
if rising_edge(SampleClk) then
|
||||
sPpsPulseOut_ms <= to_stdlogic(sPpsPulseAsyncReset);
|
||||
sPpsPulseOut <= sPpsPulseOut_ms;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
sPpsPulse <= sPpsPulseOut;
|
||||
|
||||
|
||||
rRpTransfer <= to_stdlogic(rRpTransferBool);
|
||||
sSpTransfer <= to_stdlogic(sSpTransferBool);
|
||||
|
||||
--vhook_e TdcTop
|
||||
--vhook_a aReset to_boolean(aTdcReset)
|
||||
--vhook_a rResetTdc to_boolean(rResetTdc)
|
||||
--vhook_a rEnableTdc to_boolean(rEnableTdc)
|
||||
--vhook_a rReRunEnable to_boolean(rReRunEnable)
|
||||
--vhook_a rPpsPulse to_boolean(rPpsPulseAsyncReset)
|
||||
--vhook_a rLoadRePulseCounts to_boolean(rLoadRePulseCounts)
|
||||
--vhook_a rLoadRpCounts to_boolean(rLoadRpCounts)
|
||||
--vhook_a rLoadRptCounts to_boolean(rLoadRptCounts)
|
||||
--vhook_a sLoadSpCounts to_boolean(sLoadSpCounts)
|
||||
--vhook_a sLoadSptCounts to_boolean(sLoadSptCounts)
|
||||
--vhook_a rEnablePpsCrossing to_boolean(rEnablePpsCrossing)
|
||||
--vhook_a rPulserEnableDelayVal unsigned(rPulserEnableDelayVal)
|
||||
--vhook_a sPpsClkCrossDelayVal unsigned(sPpsClkCrossDelayVal)
|
||||
--vhook_a rRpTransfer rRpTransferBool
|
||||
--vhook_a sSpTransfer sSpTransferBool
|
||||
--vhook_a sPpsPulse sPpsPulseAsyncReset
|
||||
--vhook_p {^rR(.*)In(.*)Clks} unsigned(rR$1In$2Clks)
|
||||
--vhook_p {^sS(.*)In(.*)Clks} unsigned(sS$1In$2Clks)
|
||||
TdcTopx: entity work.TdcTop (struct)
|
||||
generic map (
|
||||
kRClksPerRePulsePeriodBitsMax => kRClksPerRePulsePeriodBitsMax, --integer range 3:32 :=24
|
||||
kRClksPerRpPeriodBitsMax => kRClksPerRpPeriodBitsMax, --integer range 3:16 :=16
|
||||
kSClksPerSpPeriodBitsMax => kSClksPerSpPeriodBitsMax, --integer range 3:16 :=16
|
||||
kPulsePeriodCntSize => kPulsePeriodCntSize, --integer:=13
|
||||
kFreqRefPeriodsToCheckSize => kFreqRefPeriodsToCheckSize, --integer:=17
|
||||
kSyncPeriodsToStampSize => kSyncPeriodsToStampSize) --integer:=10
|
||||
port map (
|
||||
aReset => to_boolean(aTdcReset), --in boolean
|
||||
RefClk => RefClk, --in std_logic
|
||||
SampleClk => SampleClk, --in std_logic
|
||||
MeasClk => MeasClk, --in std_logic
|
||||
rResetTdc => to_boolean(rResetTdc), --in boolean
|
||||
rResetTdcDone => rResetTdcDone, --out boolean
|
||||
rEnableTdc => to_boolean(rEnableTdc), --in boolean
|
||||
rReRunEnable => to_boolean(rReRunEnable), --in boolean
|
||||
rPpsPulse => to_boolean(rPpsPulseAsyncReset), --in boolean
|
||||
rPpsPulseCaptured => rPpsPulseCaptured, --out boolean
|
||||
rPulserEnableDelayVal => unsigned(rPulserEnableDelayVal), --in unsigned(3:0)
|
||||
rEnablePpsCrossing => to_boolean(rEnablePpsCrossing), --in boolean
|
||||
sPpsClkCrossDelayVal => unsigned(sPpsClkCrossDelayVal), --in unsigned(3:0)
|
||||
sPpsPulse => sPpsPulseAsyncReset, --out boolean
|
||||
mRpOffset => mRpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0)
|
||||
mSpOffset => mSpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0)
|
||||
mOffsetsDone => mOffsetsDone, --out boolean
|
||||
mOffsetsValid => mOffsetsValid, --out boolean
|
||||
rLoadRePulseCounts => to_boolean(rLoadRePulseCounts), --in boolean
|
||||
rRePulsePeriodInRClks => unsigned(rRePulsePeriodInRClks), --in unsigned(kRClksPerRePulsePeriodBitsMax-1:0)
|
||||
rRePulseHighTimeInRClks => unsigned(rRePulseHighTimeInRClks), --in unsigned(kRClksPerRePulsePeriodBitsMax-1:0)
|
||||
rLoadRpCounts => to_boolean(rLoadRpCounts), --in boolean
|
||||
rRpPeriodInRClks => unsigned(rRpPeriodInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0)
|
||||
rRpHighTimeInRClks => unsigned(rRpHighTimeInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0)
|
||||
rLoadRptCounts => to_boolean(rLoadRptCounts), --in boolean
|
||||
rRptPeriodInRClks => unsigned(rRptPeriodInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0)
|
||||
rRptHighTimeInRClks => unsigned(rRptHighTimeInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0)
|
||||
sLoadSpCounts => to_boolean(sLoadSpCounts), --in boolean
|
||||
sSpPeriodInSClks => unsigned(sSpPeriodInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0)
|
||||
sSpHighTimeInSClks => unsigned(sSpHighTimeInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0)
|
||||
sLoadSptCounts => to_boolean(sLoadSptCounts), --in boolean
|
||||
sSptPeriodInSClks => unsigned(sSptPeriodInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0)
|
||||
sSptHighTimeInSClks => unsigned(sSptHighTimeInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0)
|
||||
rRpTransfer => rRpTransferBool, --out boolean
|
||||
sSpTransfer => sSpTransferBool, --out boolean
|
||||
rGatedPulseToPin => rGatedPulseToPin, --inout std_logic
|
||||
sGatedPulseToPin => sGatedPulseToPin); --inout std_logic
|
||||
|
||||
-- Expand/compress the RegPort for moving through the netlist boundary.
|
||||
bSyncRegPortOut <= Unflatten(bSyncRegPortOutFlat);
|
||||
bSyncRegPortInFlat <= Flatten(bSyncRegPortIn);
|
||||
|
||||
--vhook SyncRegsIfc
|
||||
--vhook_# Tying this low is safe because the sync reset is used inside SyncRegsIfc.
|
||||
--vhook_a aBusReset '0'
|
||||
--vhook_a bRegPortInFlat bSyncRegPortInFlat
|
||||
--vhook_a bRegPortOutFlat bSyncRegPortOutFlat
|
||||
--vhook_a rResetTdcDone to_stdlogic(rResetTdcDone)
|
||||
--vhook_a rPpsPulseCaptured to_stdlogic(rPpsPulseCaptured)
|
||||
--vhook_a mOffsetsDone to_stdlogic(mOffsetsDone)
|
||||
--vhook_a mOffsetsValid to_stdlogic(mOffsetsValid)
|
||||
--vhook_a mRpOffset std_logic_vector(mRpOffset)
|
||||
--vhook_a mSpOffset std_logic_vector(mSpOffset)
|
||||
SyncRegsIfcx: SyncRegsIfc
|
||||
port map (
|
||||
aBusReset => '0', --in std_logic
|
||||
bBusReset => bBusReset, --in std_logic
|
||||
BusClk => BusClk, --in std_logic
|
||||
aTdcReset => aTdcReset, --out std_logic
|
||||
bRegPortInFlat => bSyncRegPortInFlat, --in std_logic_vector(49:0)
|
||||
bRegPortOutFlat => bSyncRegPortOutFlat, --out std_logic_vector(33:0)
|
||||
RefClk => RefClk, --in std_logic
|
||||
rResetTdc => rResetTdc, --out std_logic
|
||||
rResetTdcDone => to_stdlogic(rResetTdcDone), --in std_logic
|
||||
rEnableTdc => rEnableTdc, --out std_logic
|
||||
rReRunEnable => rReRunEnable, --out std_logic
|
||||
rEnablePpsCrossing => rEnablePpsCrossing, --out std_logic
|
||||
rPpsPulseCaptured => to_stdlogic(rPpsPulseCaptured), --in std_logic
|
||||
rPulserEnableDelayVal => rPulserEnableDelayVal, --out std_logic_vector(3:0)
|
||||
SampleClk => SampleClk, --in std_logic
|
||||
sPpsClkCrossDelayVal => sPpsClkCrossDelayVal, --out std_logic_vector(3:0)
|
||||
MeasClk => MeasClk, --in std_logic
|
||||
mRpOffset => std_logic_vector(mRpOffset), --in std_logic_vector(39:0)
|
||||
mSpOffset => std_logic_vector(mSpOffset), --in std_logic_vector(39:0)
|
||||
mOffsetsDone => to_stdlogic(mOffsetsDone), --in std_logic
|
||||
mOffsetsValid => to_stdlogic(mOffsetsValid), --in std_logic
|
||||
rLoadRePulseCounts => rLoadRePulseCounts, --out std_logic
|
||||
rRePulsePeriodInRClks => rRePulsePeriodInRClks, --out std_logic_vector(23:0)
|
||||
rRePulseHighTimeInRClks => rRePulseHighTimeInRClks, --out std_logic_vector(23:0)
|
||||
rLoadRpCounts => rLoadRpCounts, --out std_logic
|
||||
rRpPeriodInRClks => rRpPeriodInRClks, --out std_logic_vector(15:0)
|
||||
rRpHighTimeInRClks => rRpHighTimeInRClks, --out std_logic_vector(15:0)
|
||||
rLoadRptCounts => rLoadRptCounts, --out std_logic
|
||||
rRptPeriodInRClks => rRptPeriodInRClks, --out std_logic_vector(15:0)
|
||||
rRptHighTimeInRClks => rRptHighTimeInRClks, --out std_logic_vector(15:0)
|
||||
sLoadSpCounts => sLoadSpCounts, --out std_logic
|
||||
sSpPeriodInSClks => sSpPeriodInSClks, --out std_logic_vector(15:0)
|
||||
sSpHighTimeInSClks => sSpHighTimeInSClks, --out std_logic_vector(15:0)
|
||||
sLoadSptCounts => sLoadSptCounts, --out std_logic
|
||||
sSptPeriodInSClks => sSptPeriodInSClks, --out std_logic_vector(15:0)
|
||||
sSptHighTimeInSClks => sSptHighTimeInSClks); --out std_logic_vector(15:0)
|
||||
|
||||
|
||||
end struct;
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Testbench for TdcWrapper
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--synopsys translate_off
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.PkgRegs.all;
|
||||
|
||||
entity tb_TdcWrapper is end tb_TdcWrapper;
|
||||
|
||||
architecture test of tb_TdcWrapper is
|
||||
|
||||
--vhook_sigstart
|
||||
signal bBusReset: std_logic;
|
||||
signal bSyncRegPortIn: RegPortIn_t;
|
||||
signal bSyncRegPortOut: RegPortOut_t;
|
||||
signal BusClk: std_logic := '0';
|
||||
signal MeasClk: std_logic := '0';
|
||||
signal RefClk: std_logic := '0';
|
||||
signal rGatedPulseToPin: std_logic;
|
||||
signal rPpsPulse: std_logic;
|
||||
signal rRpTransfer: std_logic;
|
||||
signal SampleClk: std_logic := '0';
|
||||
signal sGatedPulseToPin: std_logic;
|
||||
signal sPpsPulse: std_logic;
|
||||
signal sSpTransfer: std_logic;
|
||||
--vhook_sigend
|
||||
|
||||
begin
|
||||
|
||||
--vhook_e TdcWrapper dutx
|
||||
dutx: entity work.TdcWrapper (struct)
|
||||
port map (
|
||||
BusClk => BusClk, --in std_logic
|
||||
bBusReset => bBusReset, --in std_logic
|
||||
RefClk => RefClk, --in std_logic
|
||||
SampleClk => SampleClk, --in std_logic
|
||||
MeasClk => MeasClk, --in std_logic
|
||||
bSyncRegPortOut => bSyncRegPortOut, --out RegPortOut_t
|
||||
bSyncRegPortIn => bSyncRegPortIn, --in RegPortIn_t
|
||||
rPpsPulse => rPpsPulse, --in std_logic
|
||||
sPpsPulse => sPpsPulse, --out std_logic
|
||||
rRpTransfer => rRpTransfer, --out std_logic
|
||||
sSpTransfer => sSpTransfer, --out std_logic
|
||||
rGatedPulseToPin => rGatedPulseToPin, --inout std_logic
|
||||
sGatedPulseToPin => sGatedPulseToPin); --inout std_logic
|
||||
|
||||
main: process
|
||||
|
||||
begin
|
||||
report "TdcWrapper Test is EMPTY! (but that's ok in this case)" severity note;
|
||||
--vhook_nowarn tb_TdcWrapper.test.*
|
||||
wait;
|
||||
end process;
|
||||
|
||||
end test;
|
||||
--synopsys translate_on
|
||||
Reference in New Issue
Block a user