Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,42 @@
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#
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# Copyright 2008-2013 Ettus Research LLC
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#
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include $(TOOLS_DIR)/make/viv_ip_builder.mak
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TEN_GIGE_PHY_SRCS = \
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$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v \
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$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy.v \
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$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS)
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IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma_ex/, \
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imports/ten_gig_eth_pcs_pma_example_design.v \
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imports/ten_gig_eth_pcs_pma_ff_synchronizer_rst2.v \
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imports/ten_gig_eth_pcs_pma_shared_clock_and_reset.v \
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imports/ten_gig_eth_pcs_pma_support.v \
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imports/ten_gig_eth_pcs_pma_gt_common.v \
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)
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IP_TEN_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
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IP_TEN_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/, \
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ten_gig_eth_pcs_pma.xci.out \
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synth/ten_gig_eth_pcs_pma_block.v \
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synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_multi_gt.v \
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synth/ten_gig_eth_pcs_pma_cable_pull_logic.v \
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synth/ten_gig_eth_pcs_pma_local_clock_and_reset.v \
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synth/ten_gig_eth_pcs_pma_clocks.xdc \
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synth/ten_gig_eth_pcs_pma_ooc.xdc \
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synth/ten_gig_eth_pcs_pma_ff_synchronizer_rst.v \
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synth/ten_gig_eth_pcs_pma_sim_speedup_controller.v \
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synth/ten_gig_eth_pcs_pma_ff_synchronizer.v \
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synth/ten_gig_eth_pcs_pma.v \
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synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \
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synth/ten_gig_eth_pcs_pma.xdc \
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)
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$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_TEN_GIG_ETH_PCS_PMA_OUTS)
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$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
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$(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1)
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@@ -0,0 +1,200 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>xci</spirit:library>
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<spirit:name>unknown</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:instanceName>ten_gig_eth_pcs_pma</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ten_gig_eth_pcs_pma" spirit:version="6.0"/>
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESET.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESET_CORECLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESET_CORECLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESET_DATAPATHCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESET_RXUSRCLK2.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK_OUT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK_OUT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK_OUT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORECLK_OUT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DCLK_RESET.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTRXRESET.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTRXRESET_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTTXRESET.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTTXRESET_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_LATCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LFRESET.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MDIO_INTERFACE.CAN_DEBUG">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PCS_RESETOUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PMA_RESETOUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK_OUT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK_OUT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK_OUT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTCLK_OUT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK_OUT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK_OUT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK_OUT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0OUTREFCLK_OUT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK_OUT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK_OUT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK_OUT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTCLK_OUT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK_OUT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK_OUT.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK_OUT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLOUTREFCLK_OUT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REFCLK_DIFF_PORT.CAN_DEBUG">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET_TX_BUFG_GT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLK_OUT.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLK_OUT.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLK_OUT.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRESET_RXUSRCLK2.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_IN.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_IN.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_IN.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_IN.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXOUTCLK_IN.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXRESET_TXUSRCLK2.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2.PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2_OUT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2_OUT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK2_OUT.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK_OUT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK_OUT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK_OUT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TXUSRCLK_OUT.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_1588">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">ten_gig_eth_pcs_pma</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_dclkrate">78.125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_family">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc">X0Y0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gtif_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gttype">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_an">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_fec">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_has_mdio">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_is_32bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_is_kr">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_no_ebuff">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclk">clk0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclkrate">156</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_speed10_25">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_sub_core_name">ten_gig_eth_pcs_pma_gt</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ten_gig_eth_pcs_pma</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DClkRate">78.125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IEEE_1588">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Locations">X0Y0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MDIO_Management">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RefClk">clk0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RefClkRate">156.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SupportLevel">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Timer_Format">Time_of_day</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverControl">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverInExample">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.autonegotiation">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.base_kr">BASE-R</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.baser32">64bit</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.fec">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.no_ebuff">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.speed10_25">10Gig</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vu_gt_type">GTH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DClkRate" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TransceiverControl" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
@@ -0,0 +1,249 @@
|
||||
//
|
||||
// Copyright 2008-2013 Ettus Research LLC
|
||||
//
|
||||
|
||||
module ten_gige_phy
|
||||
(
|
||||
input refclk,
|
||||
input clk156,
|
||||
input dclk,
|
||||
input areset,
|
||||
input sim_speedup_control,
|
||||
input [63:0] xgmii_txd,
|
||||
input [7:0] xgmii_txc,
|
||||
output reg [63:0] xgmii_rxd,
|
||||
output reg [7:0] xgmii_rxc,
|
||||
output txp,
|
||||
output txn,
|
||||
input rxp,
|
||||
input rxn,
|
||||
input mdc,
|
||||
input mdio_in,
|
||||
output reg mdio_out,
|
||||
output reg mdio_tri,
|
||||
input [4:0] prtad,
|
||||
output [7:0] core_status,
|
||||
output resetdone,
|
||||
input signal_detect,
|
||||
input tx_fault,
|
||||
output tx_disable
|
||||
);
|
||||
|
||||
reg [63:0] xgmii_txd_reg;
|
||||
reg [7:0] xgmii_txc_reg;
|
||||
wire [63:0] xgmii_rxd_int;
|
||||
wire [7:0] xgmii_rxc_int;
|
||||
|
||||
// Add a pipeline to the xmgii_tx inputs, to aid timing closure
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
xgmii_txd_reg <= xgmii_txd;
|
||||
xgmii_txc_reg <= xgmii_txc;
|
||||
end
|
||||
|
||||
// Add a pipeline to the xmgii_rx outputs, to aid timing closure
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
xgmii_rxd <= xgmii_rxd_int;
|
||||
xgmii_rxc <= xgmii_rxc_int;
|
||||
end
|
||||
|
||||
wire mdio_out_int;
|
||||
wire mdio_tri_int;
|
||||
reg mdc_reg;
|
||||
reg mdio_in_reg;
|
||||
|
||||
// Add a pipeline to the mdio in/outputs, to aid timing closure
|
||||
// This is safe because the mdio clock is running so slowly
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
mdio_out <= mdio_out_int;
|
||||
mdio_tri <= mdio_tri_int;
|
||||
mdc_reg <= mdc;
|
||||
mdio_in_reg <= mdio_in;
|
||||
end
|
||||
|
||||
// Signal declarations
|
||||
wire txclk322;
|
||||
wire qplloutclk;
|
||||
wire qplloutrefclk;
|
||||
wire qplllock;
|
||||
|
||||
wire drp_gnt;
|
||||
wire drp_req;
|
||||
wire drp_den_o;
|
||||
wire drp_dwe_o;
|
||||
wire [15:0] drp_daddr_o;
|
||||
wire [15:0] drp_di_o;
|
||||
wire drp_drdy_o;
|
||||
wire [15:0] drp_drpdo_o;
|
||||
wire drp_den_i;
|
||||
wire drp_dwe_i;
|
||||
wire [15:0] drp_daddr_i;
|
||||
wire [15:0] drp_di_i;
|
||||
wire drp_drdy_i;
|
||||
wire [15:0] drp_drpdo_i;
|
||||
|
||||
wire tx_resetdone_int;
|
||||
wire rx_resetdone_int;
|
||||
|
||||
wire areset_clk156;
|
||||
wire gttxreset;
|
||||
wire gtrxreset;
|
||||
wire qpllreset;
|
||||
wire qplllock_txusrclk2;
|
||||
wire gttxreset_txusrclk2;
|
||||
wire reset_counter_done;
|
||||
wire txusrclk;
|
||||
wire txusrclk2;
|
||||
reg txuserrdy;
|
||||
|
||||
assign resetdone = tx_resetdone_int && rx_resetdone_int;
|
||||
|
||||
// If no arbitration is required on the GT DRP ports then connect REQ to GNT
|
||||
// and connect other signals i <= o;
|
||||
assign drp_gnt = drp_req;
|
||||
assign drp_den_i = drp_den_o;
|
||||
assign drp_dwe_i = drp_dwe_o;
|
||||
assign drp_daddr_i = drp_daddr_o;
|
||||
assign drp_di_i = drp_di_o;
|
||||
assign drp_drdy_i = drp_drdy_o;
|
||||
assign drp_drpdo_i = drp_drpdo_o;
|
||||
|
||||
// Instantiate the 10GBASER/KR GT Common block
|
||||
ten_gig_eth_pcs_pma_gt_common # (
|
||||
.WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware
|
||||
) ten_gig_eth_pcs_pma_gt_common_block (
|
||||
.refclk(refclk),
|
||||
.qpllreset(qpllreset),
|
||||
.qplllock(qplllock),
|
||||
.qplloutclk(qplloutclk),
|
||||
.qplloutrefclk(qplloutrefclk)
|
||||
);
|
||||
|
||||
// Asynch reset synchronizers...
|
||||
ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #(
|
||||
.C_NUM_SYNC_REGS(4),
|
||||
.C_RVAL(1'b1)
|
||||
) areset_clk156_sync_i (
|
||||
.clk(clk156),
|
||||
.rst(areset),
|
||||
.data_in(1'b0),
|
||||
.data_out(areset_clk156)
|
||||
);
|
||||
|
||||
ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #(
|
||||
.C_NUM_SYNC_REGS(4),
|
||||
.C_RVAL(1'b0)
|
||||
) qplllock_txusrclk2_sync_i (
|
||||
.clk(txusrclk2),
|
||||
.rst(!qplllock),
|
||||
.data_in(1'b1),
|
||||
.data_out(qplllock_txusrclk2)
|
||||
);
|
||||
|
||||
reg [7:0] reset_counter = 8'h00;
|
||||
reg [3:0] reset_pulse = 4'b1110;
|
||||
assign reset_counter_done = reset_counter[7];
|
||||
|
||||
// Hold off the GT resets until 500ns after configuration.
|
||||
// 128 ticks at 6.4ns period will be >> 500 ns.
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
if (!reset_counter[7])
|
||||
reset_counter <= reset_counter + 1'b1;
|
||||
else
|
||||
reset_counter <= reset_counter;
|
||||
end
|
||||
|
||||
always @(posedge clk156)
|
||||
begin
|
||||
if (areset_clk156 == 1'b1)
|
||||
reset_pulse <= 4'b1110;
|
||||
else if(reset_counter[7])
|
||||
reset_pulse <= {1'b0, reset_pulse[3:1]};
|
||||
end
|
||||
|
||||
assign qpllreset = reset_pulse[0];
|
||||
assign gttxreset = reset_pulse[0];
|
||||
assign gtrxreset = reset_pulse[0];
|
||||
|
||||
ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #(
|
||||
.C_NUM_SYNC_REGS(4),
|
||||
.C_RVAL(1'b1)
|
||||
) gttxreset_txusrclk2_sync_i (
|
||||
.clk(txusrclk2),
|
||||
.rst(gttxreset),
|
||||
.data_in(1'b0),
|
||||
.data_out(gttxreset_txusrclk2)
|
||||
);
|
||||
|
||||
always @(posedge txusrclk2 or posedge gttxreset_txusrclk2)
|
||||
begin
|
||||
if(gttxreset_txusrclk2)
|
||||
txuserrdy <= 1'b0;
|
||||
else
|
||||
txuserrdy <= qplllock_txusrclk2;
|
||||
end
|
||||
|
||||
BUFG tx322clk_bufg_i (
|
||||
.I (txclk322),
|
||||
.O (txusrclk)
|
||||
);
|
||||
|
||||
assign txusrclk2 = txusrclk;
|
||||
|
||||
// Instantiate the 10GBASER/KR Block Level
|
||||
ten_gig_eth_pcs_pma ten_gig_eth_pcs_pma_i (
|
||||
.coreclk(clk156),
|
||||
.dclk(dclk),
|
||||
.txusrclk(txusrclk),
|
||||
.txusrclk2(txusrclk2),
|
||||
.txoutclk(txclk322),
|
||||
.areset_coreclk(areset_clk156),
|
||||
.txuserrdy(txuserrdy),
|
||||
.areset(areset),
|
||||
.gttxreset(gttxreset),
|
||||
.gtrxreset(gtrxreset),
|
||||
.sim_speedup_control(sim_speedup_control),
|
||||
.qplllock(qplllock),
|
||||
.qplloutclk(qplloutclk),
|
||||
.qplloutrefclk(qplloutrefclk),
|
||||
.reset_counter_done(reset_counter_done),
|
||||
.xgmii_txd(xgmii_txd_reg),
|
||||
.xgmii_txc(xgmii_txc_reg),
|
||||
.xgmii_rxd(xgmii_rxd_int),
|
||||
.xgmii_rxc(xgmii_rxc_int),
|
||||
.txp(txp),
|
||||
.txn(txn),
|
||||
.rxp(rxp),
|
||||
.rxn(rxn),
|
||||
.mdc(mdc_reg),
|
||||
.mdio_in(mdio_in_reg),
|
||||
.mdio_out(mdio_out_int),
|
||||
.mdio_tri(mdio_tri_int),
|
||||
.prtad(prtad),
|
||||
.core_status(core_status),
|
||||
.tx_resetdone(tx_resetdone_int),
|
||||
.rx_resetdone(rx_resetdone_int),
|
||||
.signal_detect(signal_detect),
|
||||
.tx_fault(tx_fault),
|
||||
.drp_req(drp_req),
|
||||
.drp_gnt(drp_gnt),
|
||||
.drp_den_o(drp_den_o),
|
||||
.drp_dwe_o(drp_dwe_o),
|
||||
.drp_daddr_o(drp_daddr_o),
|
||||
.drp_di_o(drp_di_o),
|
||||
.drp_drdy_o(drp_drdy_o),
|
||||
.drp_drpdo_o(drp_drpdo_o),
|
||||
.drp_den_i(drp_den_i),
|
||||
.drp_dwe_i(drp_dwe_i),
|
||||
.drp_daddr_i(drp_daddr_i),
|
||||
.drp_di_i(drp_di_i),
|
||||
.drp_drdy_i(drp_drdy_i),
|
||||
.drp_drpdo_i(drp_drpdo_i),
|
||||
.pma_pmd_type(3'b101),
|
||||
.tx_disable(tx_disable)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,37 @@
|
||||
//
|
||||
// Copyright 2008-2013 Ettus Research LLC
|
||||
//
|
||||
|
||||
module ten_gige_phy_clk_gen
|
||||
(
|
||||
input refclk_ibuf,
|
||||
output clk156,
|
||||
output dclk
|
||||
);
|
||||
|
||||
wire dclk_buf;
|
||||
|
||||
BUFG clk156_bufg_inst (
|
||||
.I (refclk_ibuf),
|
||||
.O (clk156)
|
||||
);
|
||||
|
||||
// Dividing independent clock by 2 as source for DRP clock
|
||||
BUFR # (
|
||||
.BUFR_DIVIDE ("2")
|
||||
) dclk_divide_by_2_buf (
|
||||
.I (clk156),
|
||||
.O (dclk_buf),
|
||||
.CE (1'b1),
|
||||
.CLR (1'b0)
|
||||
);
|
||||
|
||||
BUFG dclk_bufg_i (
|
||||
.I (dclk_buf),
|
||||
.O (dclk)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user