Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,100 @@
|
||||
#
|
||||
# Copyright 2018-2019 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
|
||||
# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
|
||||
##-------------------
|
||||
##USRP E3XX FPGA Help
|
||||
##-------------------
|
||||
##Usage:
|
||||
## make <Targets> <Options>
|
||||
##
|
||||
##Output:
|
||||
## build/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
|
||||
## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file
|
||||
## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
|
||||
|
||||
1G_DEFS=SFP_1GBE=1 BUILD_1G=1 $(OPTIONS)
|
||||
XG_DEFS=SFP_10GBE=1 BUILD_10G=1 $(OPTIONS)
|
||||
AA_DEFS=SFP_AURORA=1 BUILD_AURORA=1 $(OPTIONS)
|
||||
|
||||
# Set build option (check RTL, run synthesis, or do a full build)
|
||||
ifndef TARGET
|
||||
ifdef CHECK
|
||||
TARGET = rtl
|
||||
else ifdef SYNTH
|
||||
TARGET = synth
|
||||
else
|
||||
TARGET = bin
|
||||
endif
|
||||
endif
|
||||
TOP ?= e320
|
||||
|
||||
DEFAULT_IMAGE_CORE_FILE_E320=e320_rfnoc_image_core.v
|
||||
DEFAULT_EDGE_FILE_E320=$(abspath e320_static_router.hex)
|
||||
|
||||
# vivado_build($1=Device, $2=Definitions)
|
||||
vivado_build = make -f Makefile.e320.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1)
|
||||
|
||||
# post_build($1=Device, $2=Option)
|
||||
ifeq ($(TARGET),bin)
|
||||
post_build = @\
|
||||
mkdir -p build; \
|
||||
echo "Exporting bitstream file..."; \
|
||||
cp build-$(1)_$(2)/e320.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
|
||||
echo "Exporting build report..."; \
|
||||
cp build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
|
||||
echo "Build DONE ... $(1)_$(2)";
|
||||
else
|
||||
post_build = @echo "Skipping bitfile export."
|
||||
endif
|
||||
|
||||
##
|
||||
##Supported Targets
|
||||
##-----------------
|
||||
|
||||
all: E320_1G E320_XG ##(Default target)
|
||||
|
||||
##E320_1G: 1GigE on SFP+ Port.
|
||||
E320_1G: build/usrp_e320_fpga_1G.dts
|
||||
$(call vivado_build,E320,$(1G_DEFS) E320=1)
|
||||
$(call post_build,E320,1G)
|
||||
|
||||
##E320_XG: 10GigE on SFP+ Port.
|
||||
E320_XG: build/usrp_e320_fpga_XG.dts
|
||||
$(call vivado_build,E320,$(XG_DEFS) E320=1)
|
||||
$(call post_build,E320,XG)
|
||||
|
||||
##E320_AA: Aurora on SFP+ Port.
|
||||
E320_AA: build/usrp_e320_fpga_AA.dts
|
||||
$(call vivado_build,E320,$(AA_DEFS) E320=1)
|
||||
$(call post_build,E320,AA)
|
||||
|
||||
|
||||
build/%.dts: dts/%.dts dts/*.dtsi
|
||||
-mkdir -p build
|
||||
${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
|
||||
|
||||
clean: ##Clean up all target build outputs.
|
||||
@echo "Cleaning targets..."
|
||||
@rm -rf build-E3*_*
|
||||
@rm -rf build
|
||||
|
||||
cleanall: ##Clean up all target and ip build outputs.
|
||||
@echo "Cleaning targets and IP..."
|
||||
@rm -rf build-ip
|
||||
@rm -rf build-E3*_*
|
||||
@rm -rf build
|
||||
|
||||
help: ##Show this help message.
|
||||
@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
|
||||
|
||||
##
|
||||
##Supported Options
|
||||
##-----------------
|
||||
##GUI=1 Launch the build in the Vivado GUI.
|
||||
##CHECK=1 Launch the syntax checker instead of building a bitfile.
|
||||
##SYNTH=1 Launch the build but stop after synthesis.
|
||||
##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
|
||||
|
||||
.PHONY: all clean cleanall help
|
||||
Reference in New Issue
Block a user