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Merge FPGA repository back into UHD repository

Browse Source 
The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>


Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
2020-01-28 09:35:36 -08:00
co-authored by Alex Williams Andrej Rode Ashish Chaudhari Ben Hilburn Ciro Nishiguchi Daniel Jepson Derek Kozel EJ Kreinar Humberto Jimenez Ian Buckley Jörg Hofrichter Jon Kiser Josh Blum Jonathon Pendlum Matt Ettus Michael West Moritz Fischer Nick Foster Nicolas Cuervo Paul Butler Paul David Ryan Marlow Sugandha Gupta Sylvain Munaut Trung Tran Vidush Vishwanath Wade Fife
parent 74893643ca
commit 6b67702ad7
2157 changed files with 1282567 additions and 0 deletions
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top/e31x/Makefile
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#
# Copyright 2018 Ettus Research LLC
#
# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
##-------------------
##USRP E3XX FPGA Help
##-------------------
##Usage:
## make <Targets> <Options>
##
##Output:
## build/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file
## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
# Set build option (check RTL, run synthesis, or do a full build)
ifndef TARGET
ifdef CHECK
TARGET = rtl
else ifdef SYNTH
TARGET = synth
else
TARGET = bin
endif
endif
TOP ?= e31x
DEFAULT_IMAGE_CORE_FILE_E31X=e31x_rfnoc_image_core.v
DEFAULT_EDGE_FILE_E31X=$(abspath e310_static_router.hex)
# vivado_build($1=Device, $2=Definitions)
vivado_build = make -f Makefile.e31x.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_E31X)
# post_build($1=Device, $2=Option)
ifeq ($(TARGET),bin)
post_build = @\
mkdir -p build; \
echo "Exporting bitstream file..."; \
cp build-$(1)/e31x.bit build/usrp_`echo $(2) | tr A-Z a-z`_fpga.bit; \
echo "Exporting build report..."; \
cp build-$(1)/build.rpt build/usrp_`echo $(2) | tr A-Z a-z`_fpga.rpt; \
echo "Build DONE ... $(1)";
else
post_build = @echo "Skipping bitfile export."
endif
##
##Supported Targets
##-----------------
all: E310_SG1_IDLE E310_SG3_IDLE E310_SG1 E310_SG3 E310_SG1_RFNOC E310_SG3_RFNOC ##(Default target)
##E310_SG1_IDLE: Build USRP E3XX idle design (Speed Grade 1).
E310_SG1_IDLE E3XX_idle: build/usrp_e310_sg1_idle_fpga.dts
$(call vivado_build,E310_SG1, E310_IDLE_IMAGE=1 E310_SG1=1)
$(call post_build,$@,E310_SG1_IDLE)
##E310_SG3_IDLE: Build USRP E3XX idle design (Speed Grade 3).
E310_SG3_IDLE E3XX_idle_sg3: build/usrp_e310_sg3_idle_fpga.dts
$(call vivado_build,E310_SG3, E310_IDLE_IMAGE=1 E310_SG3=1)
$(call post_build,$@,E310_SG3_IDLE)
##E310_SG1: Build USRP E3XX (Speed Grade 1).
E310_SG1 E310: build/usrp_e310_sg1_fpga.dts
$(call vivado_build,E310_SG1, E310_SG1=1)
$(call post_build,$@,E310_SG1)
##E310_SG3: Build USRP E3XX (Speed Grade 3).
E310_SG3 E310_sg3: build/usrp_e310_sg3_fpga.dts
$(call vivado_build,E310_SG3, E310_SG3=1)
$(call post_build,$@,E310_SG3)
build/%.dts: dts/%.dts dts/*.dtsi
-mkdir -p build
${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
clean: ##Clean up all target build outputs.
@echo "Cleaning targets..."
@rm -rf build-E3*
@rm -rf build
cleanall: ##Clean up all target and ip build outputs.
@echo "Cleaning targets and IP..."
@rm -rf build-ip
@rm -rf build-E3*
@rm -rf build
help: ##Show this help message.
@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
##
##Supported Options
##-----------------
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
.PHONY: all clean cleanall help
top/e31x/Makefile.e31x.inc
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#
# Copyright 2008-2012 Ettus Research LLC
#
##################################################
# Project Setup
##################################################
TOP_MODULE = <Input arg>
# NAME = <Input arg>
# PART_ID = <Input arg>
# ARCH = <Input arg>
##################################################
# Include other makefiles
##################################################
BASE_DIR = $(abspath ..)
IP_DIR = $(abspath ./ip)
include $(BASE_DIR)/../tools/make/viv_design_builder.mak
include $(IP_DIR)/Makefile.inc
include ../n3xx/coregen_dsp/Makefile.srcs
include $(LIB_DIR)/ip/Makefile.inc
include $(LIB_DIR)/hls/Makefile.inc
include $(LIB_DIR)/control/Makefile.srcs
include $(LIB_DIR)/fifo/Makefile.srcs
include $(LIB_DIR)/axi/Makefile.srcs
include $(LIB_DIR)/timing/Makefile.srcs
include $(LIB_DIR)/packet_proc/Makefile.srcs
include $(LIB_DIR)/dsp/Makefile.srcs
include $(LIB_DIR)/io_cap_gen/Makefile.srcs
include $(LIB_DIR)/rfnoc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
EDGE_FILE ?= $(DEFAULT_EDGE_FILE)
##################################################
# Sources
##################################################
TOP_SRCS = \
ppsloop.v \
axi_pmu.v \
spi_slave.v
ifneq (IDLE,$(findstring IDLE, $(EXTRA_DEFS)))
TOP_SRCS += e31x.v
TOP_SRCS += e31x_core.v
TOP_SRCS += e310_io.v
TOP_SRCS += $(EDGE_FILE) $(IMAGE_CORE)
MB_XDC = \
e31x_pins.xdc \
e31x_timing.xdc
else
TOP_SRCS += e31x_idle.v
MB_XDC = \
e31x_idle_pins.xdc
endif
# The XDC files must be read in a specific order, motherboard first and then daughterboard.
# Outside of that, all the other sources can be read in any order desired.
DESIGN_SRCS = \
$(abspath $(TOP_SRCS)) \
$(CONTROL_LIB_SRCS) \
$(IP_XCI_SRCS) \
$(PACKET_PROC_SRCS) \
$(AXI_SRCS) \
$(FIFO_SRCS) \
$(AURORA_PHY_SRCS) \
$(BD_SRCS) \
$(RADIO_SRCS) \
$(RFNOC_SRCS) \
$(TIMING_SRCS) \
$(VITA_SRCS) \
$(CAT_CAP_GEN_SRCS) \
$(DRAM_SRCS) \
$(COREGEN_DSP_SRCS) \
$(DSP_SRCS) \
$(LIB_IP_XCI_SRCS) \
$(LIB_HLS_IP_SRCS) \
$(EXTRAM_SRCS) \
$(CAP_GEN_GENERIC_SRCS) \
$(RFNOC_OOT_SRCS)\
$(RFNOC_FRAMEWORK_SRCS) $(RFNOC_BLOCK_NULL_SRC_SINK_SRCS) \
$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) $(RFNOC_BLOCK_RADIO_SRCS) \
$(RFNOC_BLOCK_EXAMPLE_SRCS) \
$(abspath $(MB_XDC))
EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(EDGE_FILE)"
##################################################
# Dependency Targets
##################################################
.SECONDEXPANSION:
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF)
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs $$(DESIGN_SRCS) ip
$(call BUILD_VIVADO_DESIGN,$(abspath ./build_e31x.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
synth: .prereqs $$(DESIGN_SRCS) ip
$(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
rtl: .prereqs $$(DESIGN_SRCS) ip
$(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
.PHONY: bin rtl
top/e31x/axi_pmu.v
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//
// Copyright 2015 Ettus Research, A National Instruments Company
// SPDX-License-Identifier: LGPL-3.0
//
// Description: AXI PMU
//
module axi_pmu
#(
parameter DEPTH = 64
)
(
// sys connect
input s_axi_aclk,
input s_axi_areset,
// spi slave port
input ss,
input mosi,
input sck,
output miso,
// axi4 lite slave port
input [31:0] s_axi_awaddr,
input s_axi_awvalid,
output s_axi_awready,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
input s_axi_wvalid,
output s_axi_wready,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
input [31:0] s_axi_araddr,
input s_axi_arvalid,
output s_axi_arready,
output [31:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rvalid,
input s_axi_rready,
output s_axi_irq
);
wire spi_stb;
wire [DEPTH-1:0] spi_rx;
wire [DEPTH-1:0] spi_tx;
spi_slave inst_spi_slave0
(
.clk(s_axi_aclk),
.rst(s_axi_areset),
.ss(ss),
.mosi(mosi),
.miso(miso),
.sck(sck),
.parallel_stb(spi_stb),
.parallel_din(spi_tx),
.parallel_dout(spi_rx)
);
wire [7:0] rx_type = spi_rx[7:0];
reg [DEPTH-1:0] spi_rx_r0, spi_rx_r1, spi_rx_r2;
always @ (posedge s_axi_aclk)
if (s_axi_areset) begin
spi_rx_r0 <= 64'h0000_0000_0000_0000;
spi_rx_r1 <= 64'h0000_0000_0000_0000;
spi_rx_r2 <= 64'h0000_0000_0000_0000;
end else begin
spi_rx_r0 <= spi_stb && (rx_type == 0) ? spi_rx : spi_rx_r0;
spi_rx_r1 <= spi_stb && (rx_type == 1) ? spi_rx : spi_rx_r1;
spi_rx_r2 <= spi_stb && (rx_type == 2) ? spi_rx : spi_rx_r2;
end
localparam IDLE = 3'b001;
localparam READ_IN_PROGRESS = 3'b010;
localparam WRITE_IN_PROGRESS = 3'b100;
reg [2:0] state;
reg [7:0] addr;
always @ (posedge s_axi_aclk) begin
if (s_axi_areset) begin
state <= IDLE;
end
else case (state)
IDLE: begin
if (s_axi_arvalid) begin
state <= READ_IN_PROGRESS;
addr <= s_axi_araddr[7:0];
end
else if (s_axi_awvalid) begin
state <= WRITE_IN_PROGRESS;
addr <= s_axi_awaddr[7:0];
end
end
READ_IN_PROGRESS: begin
if (s_axi_rready)
state <= IDLE;
end
WRITE_IN_PROGRESS: begin
if (s_axi_bready)
state <= IDLE;
end
default: begin
state <= IDLE;
end
endcase
end
// write mux
reg write_shutdown;
reg write_irq_mask;
always @(*) begin
write_shutdown = 1'b0;
write_irq_mask = 1'b0;
if (state == WRITE_IN_PROGRESS)
case (addr)
8'h00: write_shutdown = 1'b1;
8'h04: write_irq_mask = 1'b1;
endcase
end
reg [31:0] shutdown = 32'h0000_0000;
always @ (posedge s_axi_aclk) begin
if (s_axi_areset)
shutdown <= 32'h0000_0000;
else if (write_shutdown)
shutdown <= s_axi_wdata;
end
wire [31:0] spi_tx_tdata;
wire spi_tx_tvalid;
wire [5:0] spi_tx_occupied;
wire [5:0] spi_tx_space;
wire [31:0] tmux = write_shutdown ? {s_axi_wdata[23:0], 8'h00}
: {s_axi_wdata[7:0], s_axi_wdata[15:8], addr[7:0], 8'h01};
wire is_spi_cmd = (addr[7:0] == 8'h00) || (addr[7:0] > 8'h04);
axi_fifo_bram #(.WIDTH(32), .SIZE(5)) axi_fifo_short_inst
(
.clk(s_axi_aclk),
.reset(s_axi_areset),
.clear(1'b0),
.i_tdata(tmux),
.i_tvalid(state == WRITE_IN_PROGRESS && is_spi_cmd),
.i_tready(),
.o_tdata(spi_tx_tdata),
.o_tvalid(spi_tx_tvalid),
.o_tready(spi_stb),
.occupied(spi_tx_occupied),
.space(spi_tx_space)
);
reg [63:0] spi_tx_reg;
always @ (posedge s_axi_aclk)
if(s_axi_areset)
spi_tx_reg <= 64'h0000_0000_0000_0000;
else if (spi_stb)
spi_tx_reg <= {spi_tx_tvalid, 31'h00, spi_tx_tdata};
assign spi_tx = spi_tx_reg;
/* battery stuff */
wire [15:0] battery_voltage = {spi_rx_r0[55:48], spi_rx_r0[63:56]};
wire [1:0] battery_temp_alert = spi_rx_r0[47:46];
wire battery_online = spi_rx_r0[45];
wire [2:0] battery_health = spi_rx_r0[44:42];
wire [1:0] battery_status = spi_rx_r0[41:40];
/* charger stuff */
/* unused [39:38] */
wire [1:0] charger_health = spi_rx_r0[37:36];
wire charger_online = spi_rx_r0[35];
/* unused bit 34 */
wire [1:0] charger_charge_type = spi_rx_r0[33:32];
/* gauge stuff */
wire [7:0] gauge_status = spi_rx_r1[63:56];
wire [15:0] voltage = {spi_rx_r1[47:40], spi_rx_r1[55:48]};
wire [15:0] temp = {spi_rx_r1[31:24], spi_rx_r1[39:32]};
wire [15:0] charge_acc = {spi_rx_r1[15:8] , spi_rx_r1[23:16]};
/* charge last full */
wire [15:0] charge_last_full = {spi_rx_r2[15:8], spi_rx_r2[23:16]};
/* settings flags */
wire [7:0] settings = spi_rx_r2[31:24];
reg [7:0] irq_enable;
always @ (posedge s_axi_aclk) begin
if (s_axi_areset)
irq_enable <= 8'h00;
else if (write_irq_mask)
irq_enable <= s_axi_wdata[15:8];
end
wire [7:0] irq_status = gauge_status;
assign s_axi_irq = |(irq_status & irq_enable);
wire [3:0] version_maj = spi_rx_r0[15:12];
wire [3:0] version_min = spi_rx_r0[11:8];
reg [31:0] rdata;
// read mux
always @(*) begin
rdata = 32'hdead_beef;
if (state == READ_IN_PROGRESS)
case (addr)
8'h00: rdata = shutdown;
8'h04: rdata = {16'h0000, irq_enable, version_maj, version_min};
8'h08: rdata = {8'h0, battery_voltage, battery_temp_alert, battery_online, battery_health, battery_status};
8'h0c: rdata = {27'd0, charger_charge_type, charger_online, charger_health};
8'h10: rdata = {temp, charge_acc};
8'h14: rdata = {8'h00, gauge_status, voltage};
8'h18: rdata = {16'h0000, charge_last_full};
8'h1c: rdata = {24'd0, settings};
endcase
end
assign s_axi_arready = (state == IDLE);
assign s_axi_rvalid = (state == READ_IN_PROGRESS);
assign s_axi_rresp = 2'b00;
assign s_axi_rdata = rdata;
assign s_axi_awready = (state == IDLE);
assign s_axi_wready = (state == WRITE_IN_PROGRESS);
assign s_axi_bresp = 2'b00;
assign s_axi_bvalid = (state == WRITE_IN_PROGRESS);
endmodule
top/e31x/build_e31x.tcl
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#
# Copyright 2016 Ettus Research
#
source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl
source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl
# STEP#1: Create project, add sources, refresh IP
vivado_utils::initialize_project
# STEP#2: Run synthesis
vivado_utils::synthesize_design
vivado_utils::generate_post_synth_reports
# STEP#3: Run implementation strategy
set e31x_strategy [dict create]
dict set e31x_strategy "opt_design.is_enabled" 1
dict set e31x_strategy "opt_design.directive" "Default"
dict set e31x_strategy "post_opt_power_opt_design.is_enabled" 0
dict set e31x_strategy "place_design.directive" "Default"
dict set e31x_strategy "post_place_power_opt_design.is_enabled" 0
dict set e31x_strategy "post_place_phys_opt_design.is_enabled" 1
dict set e31x_strategy "post_place_phys_opt_design.directive" "Default"
dict set e31x_strategy "route_design.directive" "Default"
dict set e31x_strategy "route_design.more_options" "-tns_cleanup"
dict set e31x_strategy "post_route_phys_opt_design.is_enabled" 1
dict set e31x_strategy "post_route_phys_opt_design.directive" "Default"
vivado_strategies::implement_design $e31x_strategy
# STEP#4: Generate reports
vivado_utils::generate_post_route_reports
# STEP#5: Generate a bitstream, netlist and debug probes
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [get_designs *]
set byte_swap_bin 1
vivado_utils::write_implementation_outputs $byte_swap_bin
# Cleanup
vivado_utils::close_batch_project
top/e31x/dts/dma-common.dtsi
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/*
* Copyright (c) 2018 National Instruments Corp
*
* SPDX-License-Identifier: GPL-2.0 OR X11
*/
&fpga_full {
tx_dma0: dma@43CA0000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43CA0000 0x10000>;
interrupts = <0 53 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <0>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <1>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
tx_dma1: dma@43CB0000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43CB0000 0x10000>;
interrupts = <0 53 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <0>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <1>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
tx_dma2: dma@43CC0000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43CC0000 0x10000>;
interrupts = <0 53 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <0>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <1>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
tx_dma3: dma@43CD0000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43CD0000 0x10000>;
interrupts = <0 53 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <0>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <1>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
tx_dma4: dma@43CE0000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43CE0000 0x10000>;
interrupts = <0 53 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <0>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <1>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
rx_dma0: dma@43C00000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43C00000 0x10000>;
interrupts = <0 52 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <1>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <0>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
rx_dma1: dma@43C10000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43C10000 0x10000>;
interrupts = <0 52 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <1>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <0>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
rx_dma2: dma@43C20000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43C20000 0x10000>;
interrupts = <0 52 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <1>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <0>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
rx_dma3: dma@43C30000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43C30000 0x10000>;
interrupts = <0 52 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <1>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <0>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
rx_dma4: dma@43C40000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x43C40000 0x10000>;
interrupts = <0 52 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 15>;
#dma-cells = <1>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-type = <1>;
adi,source-bus-width = <0x20>;
adi,destination-bus-type = <0>;
adi,destination-bus-width = <0x20>;
adi,length-width = <24>;
};
};
};
usrp_rx_dma0: usrp-rx-dma@43c00000 {
compatible = "ettus,usrp-rx-dma";
dmas = <&rx_dma0 0>;
dma-names = "dma";
port-id = <0>;
status = "okay";
regmap = <&dma_conf0>;
offset = <0x0>;
};
usrp_rx_dma1: usrp-rx-dma@43c10000 {
compatible = "ettus,usrp-rx-dma";
dmas = <&rx_dma1 0>;
dma-names = "dma";
port-id = <1>;
regmap = <&dma_conf0>;
offset = <0x4>;
};
usrp_rx_dma2: usrp-rx-dma@43c20000 {
compatible = "ettus,usrp-rx-dma";
dmas = <&rx_dma2 0>;
dma-names = "dma";
port-id = <2>;
regmap = <&dma_conf0>;
offset = <0x8>;
};
usrp_rx_dma3: usrp-rx-dma@43c30000 {
compatible = "ettus,usrp-rx-dma";
dmas = <&rx_dma3 0>;
dma-names = "dma";
port-id = <3>;
regmap = <&dma_conf0>;
offset = <0xc>;
};
usrp_rx_dma4: usrp-rx-dma@43c40000 {
compatible = "ettus,usrp-rx-dma";
dmas = <&rx_dma4 0>;
dma-names = "dma";
port-id = <4>;
regmap = <&dma_conf0>;
offset = <0x10>;
};
usrp_tx_dma0: usrp-tx-dma@43ca0000 {
compatible = "ettus,usrp-tx-dma";
dmas = <&tx_dma0 0>;
dma-names = "dma";
port-id = <0>;
};
usrp_tx_dma1: usrp-tx-dma@43cb0000 {
compatible = "ettus,usrp-tx-dma";
dmas = <&tx_dma1 0>;
dma-names = "dma";
port-id = <1>;
};
usrp_tx_dma2: usrp-tx-dma@43cc0000 {
compatible = "ettus,usrp-tx-dma";
dmas = <&tx_dma2 0>;
dma-names = "dma";
port-id = <2>;
status = "okay";
};
usrp_tx_dma3: usrp-tx-dma@43cd0000 {
compatible = "ettus,usrp-tx-dma";
dmas = <&tx_dma3 0>;
dma-names = "dma";
port-id = <3>;
};
usrp_tx_dma4: usrp-tx-dma@43ce0000 {
compatible = "ettus,usrp-tx-dma";
dmas = <&tx_dma4 0>;
dma-names = "dma";
port-id = <4>;
status = "okay";
};
dma_conf0: dma_conf0@42080000 {
compatible = "syscon";
reg = <0x42080000 0x1000>;
status = "okay";
};
};
top/e31x/dts/e31x-common.dtsi
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/*
* Copyright (c) 2018 National Instruments Corp
*
* SPDX-License-Identifier: GPL-2.0 OR X11
*/
&fpga_full {
uio@40010000 {
compatible = "usrp-uio";
reg = <0x40010000 0x2000>;
reg-names = "mboard-regs";
status = "okay";
};
};
&spi0 {
status = "okay";
cs-gpios = <0>;
spidev0: spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
status = "okay";
spi-max-frequency = <1000000>;
};
};
top/e31x/dts/e31x-pmu.dtsi
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/*
* Copyright (c) 2018 National Instruments Corp
*
* SPDX-License-Identifier: GPL-2.0 OR X11
*/
&fpga_full {
devctrl: devctrl@40000000 {
compatible = "syscon";
reg = <0x40000000 0x24>;
};
poweroff {
compatible = "syscon-poweroff";
regmap = <&devctrl>;
offset = <0x0>;
mask = <0x7a>;
};
pmu {
compatible = "ni,e31x-pmu";
regmap = <&devctrl>;
status = "okay";
charger: charger@0{
compatible = "ni,e31x-charger";
};
battery: battery@1{
compatible = "ni,e31x-battery";
};
};
};
top/e31x/dts/e31x-sg1-fpga.dtsi
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/*
* Copyright (c) 2018 National Instruments Corp
*
* SPDX-License-Identifier: GPL-2.0 OR X11
*/
&fpga_full {
firmware-name = "e310_sg1.bin";
};
top/e31x/dts/e31x-sg1-idle-fpga.dtsi
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/*
* Copyright (c) 2018 National Instruments Corp
*
* SPDX-License-Identifier: GPL-2.0 OR X11
*/
&fpga_full {
firmware-name = "e310_sg1_idle.bin";
};
top/e31x/dts/e31x-sg3-fpga.dtsi
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/*
* Copyright (c) 2018 National Instruments Corp
*
* SPDX-License-Identifier: GPL-2.0 OR X11
*/
&fpga_full {
firmware-name = "e310_sg3.bin";
};
top/e31x/dts/e31x-sg3-idle-fpga.dtsi
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/*
* Copyright (c) 2018 National Instruments Corp
*
* SPDX-License-Identifier: GPL-2.0 OR X11
*/
&fpga_full {
firmware-name = "e310_sg3_idle.bin";
};
top/e31x/dts/usrp_e310_sg1_fpga.dts
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/*
* Copyright (c) 2018 National Instruments Corp
*
* SPDX-License-Identifier: GPL-2.0 OR X11
*/
/dts-v1/;
/plugin/;
#include "e31x-sg1-fpga.dtsi"
#include "e31x-common.dtsi"
#include "e31x-pmu.dtsi"
#include "dma-common.dtsi"
top/e31x/dts/usrp_e310_sg1_idle_fpga.dts
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/*
* Copyright (c) 2018 National Instruments Corp
*
* SPDX-License-Identifier: GPL-2.0 OR X11
*/
/dts-v1/;
/plugin/;
#include "e31x-sg1-idle-fpga.dtsi"
#include "e31x-pmu.dtsi"
top/e31x/dts/usrp_e310_sg3_fpga.dts
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/*
* Copyright (c) 2018 National Instruments Corp
*
* SPDX-License-Identifier: GPL-2.0 OR X11
*/
/dts-v1/;
/plugin/;
#include "e31x-sg3-fpga.dtsi"
#include "e31x-common.dtsi"
#include "e31x-pmu.dtsi"
#include "dma-common.dtsi"
top/e31x/dts/usrp_e310_sg3_idle_fpga.dts
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/*
* Copyright (c) 2018 National Instruments Corp
*
* SPDX-License-Identifier: GPL-2.0 OR X11
*/
/dts-v1/;
/plugin/;
#include "e31x-sg3-idle-fpga.dtsi"
#include "e31x-pmu.dtsi"
top/e31x/e310_io.v
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//
// Copyright 2015 Ettus Research, A National Instruments Company
// SPDX-License-Identifier: LGPL-3.0
//
// Description: E31X IO for CMOS interface
//
module e310_io (
input areset,
input mimo,
// Baseband sample interface
output radio_clk,
output radio_rst,
output reg [11:0] rx_i0,
output reg [11:0] rx_q0,
output reg [11:0] rx_i1,
output reg [11:0] rx_q1,
output reg rx_stb,
input [11:0] tx_i0,
input [11:0] tx_q0,
input [11:0] tx_i1,
input [11:0] tx_q1,
output reg tx_stb,
// AD9361 interface
input rx_clk,
input rx_frame,
input [11:0] rx_data,
output tx_clk,
output tx_frame,
output [11:0] tx_data
);
// Synchronize asynchronous reset and MIMO
synchronizer #(.STAGES(3), .INITIAL_VAL(1'b1)) sychronizer_radio_rst (
.clk(radio_clk), .rst(areset), .in(1'b0), .out(radio_rst));
wire mimo_sync;
synchronizer synchronizer_mimo (.clk(radio_clk), .rst(radio_rst), .in(mimo), .out(mimo_sync));
/****************************************************************************
** RX Capture Interface
****************************************************************************/
wire rx_clk_bufr; // Capture clock
BUFR bufr_rx_clk (.I(rx_clk), .O(rx_clk_bufr));
BUFG bufg_radio_clk (.I(rx_clk_bufr), .O(radio_clk));
wire [11:0] rx_i, rx_q;
genvar n;
generate
for (n = 0; n < 12; n = n + 1) begin
IDDR #(.DDR_CLK_EDGE("SAME_EDGE")) iddr (
.C(rx_clk_bufr), .CE(1'b1), .R(1'b0), .S(1'b0),
.D(rx_data[n]), .Q1(rx_q[n]), .Q2(rx_i[n]));
end
endgenerate
wire rx_frame_rising, rx_frame_falling;
IDDR #(.DDR_CLK_EDGE("SAME_EDGE")) iddr_frame (
.C(rx_clk_bufr), .CE(1'b1), .R(1'b0), .S(1'b0),
.D(rx_frame), .Q1(rx_frame_rising), .Q2(rx_frame_falling));
always @(posedge radio_clk or posedge radio_rst) begin
if (radio_rst) begin
rx_stb <= 1'b0;
end else begin
if (mimo_sync) begin
if (rx_frame_rising) begin
rx_i0 <= rx_i;
rx_q0 <= rx_q;
end else begin
rx_i1 <= rx_i;
rx_q1 <= rx_q;
end
rx_stb <= ~rx_frame_rising;
end else begin
rx_i0 <= rx_i;
rx_q0 <= rx_q;
rx_i1 <= rx_i;
rx_q1 <= rx_q;
rx_stb <= 1'b1;
end
end
end
/****************************************************************************
** TX Output Interface
****************************************************************************/
reg [11:0] tx_i, tx_q;
reg tx_frame_int = 1'b1;
generate
for (n = 0; n < 12; n = n + 1) begin
ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr (
.C(radio_clk), .CE(1'b1), .R(1'b0), .S(1'b0),
.D1(tx_i[n]), .D2(tx_q[n]), .Q(tx_data[n]));
end
endgenerate
ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_frame (
.C(radio_clk), .CE(1'b1), .R(1'b0), .S(1'b0),
// In SISO mode, TX frame is asserted only on the falling edge
.D1(tx_frame_int), .D2(tx_frame_int & mimo_sync), .Q(tx_frame));
ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_clk (
.C(radio_clk), .CE(1'b1), .R(1'b0), .S(1'b0),
.D1(1'b1), .D2(1'b0), .Q(tx_clk));
reg [11:0] tx_i1_hold, tx_q1_hold;
always @(posedge radio_clk or posedge radio_rst) begin
if (radio_rst) begin
tx_stb <= 1'b0;
tx_frame_int <= 1'b1;
end else begin
if (mimo_sync) begin
tx_stb <= ~tx_stb;
tx_frame_int <= tx_stb;
if (tx_stb) begin
tx_i <= tx_i0;
tx_q <= tx_q0;
tx_i1_hold <= tx_i1;
tx_q1_hold <= tx_q1;
end else begin
tx_i <= tx_i1_hold;
tx_q <= tx_q1_hold;
end
end else begin
tx_stb <= 1'b1;
tx_frame_int <= 1'b1;
if ({tx_i0,tx_q0} != 24'd0) begin
tx_i <= tx_i0;
tx_q <= tx_q0;
end else begin
tx_i <= tx_i1;
tx_q <= tx_q1;
end
end
end
end
endmodule
top/e31x/e310_static_router.hex
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00000004
004000c0
008000c1
00c00040
00c10080
top/e31x/e31x.v
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/////////////////////////////////////////////////////////////////////
//
// Copyright 2018 Ettus Research, A National Instruments Company
// Copyright 2019 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: e31x
// Description:
// E31x Top Level
//
/////////////////////////////////////////////////////////////////////
module e31x (
// PS Connections
inout [53:0] MIO,
input PS_SRSTB,
input PS_CLK,
input PS_PORB,
inout DDR_CLK,
inout DDR_CLK_N,
inout DDR_CKE,
inout DDR_CS_N,
inout DDR_RAS_N,
inout DDR_CAS_N,
inout DDR_WEB,
inout [2:0] DDR_BANKADDR,
inout [14:0] DDR_ADDR,
inout DDR_ODT,
inout DDR_DRSTB,
inout [31:0] DDR_DQ,
inout [3:0] DDR_DM,
inout [3:0] DDR_DQS,
inout [3:0] DDR_DQS_N,
inout DDR_VRP,
inout DDR_VRN,
// PL DDR
//input PL_DDR3_SYSCLK,
//output PL_DDR3_RESET_N,
//inout [15:0] PL_DDR3_DQ,
//inout [1:0] PL_DDR3_DQS_N,
//inout [1:0] PL_DDR3_DQS_P,
//output [14:0] PL_DDR3_ADDR,
//output [2:0] PL_DDR3_BA,
//output PL_DDR3_RAS_N,
//output PL_DDR3_CAS_N,
//output PL_DDR3_WE_N,
//output [0:0] PL_DDR3_CK_P,
//output [0:0] PL_DDR3_CK_N,
//output [0:0] PL_DDR3_CKE,
//output [1:0] PL_DDR3_DM,
//output [0:0] PL_DDR3_ODT,
//AVR SPI IO
input AVR_CS_R,
output AVR_IRQ,
output AVR_MISO_R,
input AVR_MOSI_R,
input AVR_SCK_R,
input ONSWITCH_DB,
// RF Board connections
// Change to inout/output as
// they are implemented/tested
input [34:0] DB_EXP_1_8V,
// Front-end Band Selects
output [2:0] TX_BANDSEL,
output [2:0] RX1_BANDSEL,
output [2:0] RX2_BANDSEL,
output [1:0] RX2C_BANDSEL,
output [1:0] RX1B_BANDSEL,
output [1:0] RX1C_BANDSEL,
output [1:0] RX2B_BANDSEL,
// Enables
output TX_ENABLE1A,
output TX_ENABLE2A,
output TX_ENABLE1B,
output TX_ENABLE2B,
// Antenna Selects
output VCTXRX1_V1,
output VCTXRX1_V2,
output VCTXRX2_V1,
output VCTXRX2_V2,
output VCRX1_V1,
output VCRX1_V2,
output VCRX2_V1,
output VCRX2_V2,
// Leds
output LED_TXRX1_TX,
output LED_TXRX1_RX,
output LED_RX1_RX,
output LED_TXRX2_TX,
output LED_TXRX2_RX,
output LED_RX2_RX,
// AD9361 connections
input [7:0] CAT_CTRL_OUT,
output [3:0] CAT_CTRL_IN,
output CAT_RESET, // FIXME Fix in Pinout
output CAT_CS,
output CAT_SCLK,
output CAT_MOSI,
input CAT_MISO,
input CAT_BBCLK_OUT, //unused
output CAT_SYNC,
output CAT_TXNRX,
output CAT_ENABLE,
output CAT_ENAGC,
input CAT_RX_FRAME,
input CAT_DATA_CLK,
output CAT_TX_FRAME,
output CAT_FB_CLK,
input [11:0] CAT_P0_D,
output [11:0] CAT_P1_D,
// pps connections
input GPS_PPS,
input PPS_EXT_IN,
// VTCXO and the DAC that feeds it
output TCXO_DAC_SYNC_N,
output TCXO_DAC_SCLK,
output TCXO_DAC_SDIN,
input TCXO_CLK,
// gpios, change to inout somehow
inout [5:0] PL_GPIO
);
// Constants
localparam REG_AWIDTH = 14; // log2(0x4000)
localparam REG_DWIDTH = 32;
localparam DB_GPIO_WIDTH = 32;
localparam FP_GPIO_OFFSET = 32; // Offset within ps_gpio_*
localparam FP_GPIO_WIDTH = 6;
//If bus_clk freq ever changes, update this parameter accordingly.
localparam BUS_CLK_RATE = 32'd100000000; //100 MHz bus_clk rate.
localparam NUM_SFP_PORTS = 0;
localparam NUM_RADIOS = 1;
localparam NUM_CHANNELS_PER_RADIO = 2;
localparam NUM_DBOARDS = 1;
localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO;
// Clocks
wire bus_clk;
wire radio_clk;
wire reg_clk;
wire clk40;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
// Resets
wire global_rst;
wire bus_rst;
wire radio_rst;
wire reg_rstn;
wire clk40_rst;
wire clk40_rstn;
wire FCLK_RESET0_N;
// Crossbar
wire m_axi_xbar_arvalid;
wire m_axi_xbar_awvalid;
wire m_axi_xbar_bready;
wire m_axi_xbar_rready;
wire m_axi_xbar_wvalid;
wire [11:0] m_axi_xbar_arid;
wire [11:0] m_axi_xbar_awid;
wire [11:0] m_axi_xbar_wid;
wire [31:0] m_axi_xbar_araddr;
wire [31:0] m_axi_xbar_awaddr;
wire [31:0] m_axi_xbar_wdata;
wire [3:0] m_axi_xbar_wstrb;
wire m_axi_xbar_arready;
wire m_axi_xbar_awready;
wire m_axi_xbar_bvalid;
wire m_axi_xbar_rlast;
wire m_axi_xbar_rvalid;
wire m_axi_xbar_wready;
wire [1:0] m_axi_xbar_bresp;
wire [1:0] m_axi_xbar_rresp;
wire [31:0] m_axi_xbar_rdata;
// PMU
wire [31:0] m_axi_pmu_araddr;
wire [2:0] m_axi_pmu_arprot;
wire m_axi_pmu_arready;
wire m_axi_pmu_arvalid;
wire [31:0] m_axi_pmu_awaddr;
wire [2:0] m_axi_pmu_awprot;
wire m_axi_pmu_awready;
wire m_axi_pmu_awvalid;
wire m_axi_pmu_bready;
wire [1:0] m_axi_pmu_bresp;
wire m_axi_pmu_bvalid;
wire [31:0] m_axi_pmu_rdata;
wire m_axi_pmu_rready;
wire [1:0] m_axi_pmu_rresp;
wire m_axi_pmu_rvalid;
wire [31:0] m_axi_pmu_wdata;
wire m_axi_pmu_wready;
wire [3:0] m_axi_pmu_wstrb;
wire m_axi_pmu_wvalid;
// DMA xport adapter to PS
wire [63:0] m_axis_dma_tdata;
wire [3:0] m_axis_dma_tuser;
wire m_axis_dma_tlast;
wire m_axis_dma_tready;
wire m_axis_dma_tvalid;
wire [63:0] s_axis_dma_tdata;
wire [3:0] s_axis_dma_tdest;
wire s_axis_dma_tlast;
wire s_axis_dma_tready;
wire s_axis_dma_tvalid;
/////////////////////////////////////////////////////////////////////
//
// Resets:
// - PL - Global Reset --> Bus Reset
// --> Radio Reset
// - PS - FCLK_RESET0_N --> clk40_rst(n)
//
//////////////////////////////////////////////////////////////////////
// Global synchronous reset, on the bus_clk domain. De-asserts after 85
// bus_clk cycles. Asserted by default.
por_gen por_gen (
.clk(bus_clk),
.reset_out(global_rst)
);
// Synchronous reset for the bus_clk domain
reset_sync bus_reset_gen (
.clk(bus_clk),
.reset_in(~FCLK_RESET0_N),
//.reset_in(~clocks_locked),
.reset_out(bus_rst)
);
// PS-based Resets //
//
// Synchronous reset for the clk40 domain. This is derived from the PS reset 0.
reset_sync clk40_reset_gen (
.clk(clk40),
.reset_in(~FCLK_RESET0_N),
.reset_out(clk40_rst)
);
// Invert for various modules.
assign clk40_rstn = ~clk40_rst;
assign reg_rstn = clk40_rstn;
/////////////////////////////////////////////////////////////////////
//
// Clocks and PPS
//
/////////////////////////////////////////////////////////////////////
wire [1:0] pps_select;
assign clk40 = FCLK_CLK1; // 40 MHz
assign bus_clk = FCLK_CLK0; // 100 MHz
//assign bus_clk = FCLK_CLK3; // 200 MHz
assign reg_clk = clk40;
wire pps;
wire clk_tcxo = TCXO_CLK; // 40 MHz
wire is_10meg, is_pps, reflck, plllck; // reference status bits
reg [3:0] tcxo_status, st_rsync;
reg [2:0] pps_reg;
wire pps_ext = PPS_EXT_IN;
wire gps_pps = GPS_PPS;
// A local pps signal is derived from the tcxo clock. If a reference
// at an appropriate rate (1 pps or 10 MHz) is present and selected
// a digital control loop will be invoked to tune the vcxo and lock
// the reference.
ppsloop ppslp (
.reset(1'b0),
.xoclk(clk_tcxo), .ppsgps(gps_pps), .ppsext(pps_ext),
.refsel(pps_select),
.lpps(pps),
.is10meg(is_10meg), .ispps(is_pps), .reflck(reflck), .plllck(plllck),
.sclk(TCXO_DAC_SCLK), .mosi(TCXO_DAC_SDIN), .sync_n(TCXO_DAC_SYNC_N),
.dac_dflt(16'h7fff)
);
always @(posedge bus_clk) begin
// status signals originate from other than the bus_clk domain so re-sync
// before passing to e300_core
st_rsync <= {plllck, is_10meg, is_pps, reflck};
tcxo_status <= st_rsync;
end
// TODO: Check this logic
// connect PPS input to GPIO so ntpd can use it
always @ (posedge bus_clk)
pps_reg <= bus_rst ? 3'b000 : {pps_reg[1:0], GPS_PPS};
assign ps_gpio_in[8] = pps_reg[2]; // 62
/////////////////////////////////////////////////////////////////////
//
// Power Button
//
//////////////////////////////////////////////////////////////////////
// register the debounced onswitch signal to detect edges,
// Note: ONSWITCH_DB is low active
reg [1:0] onswitch_edge;
always @ (posedge bus_clk)
onswitch_edge <= bus_rst ? 2'b00 : {onswitch_edge[0], ONSWITCH_DB};
wire button_press = ~ONSWITCH_DB & onswitch_edge[0] & onswitch_edge[1];
wire button_release = ONSWITCH_DB & ~onswitch_edge[0] & ~onswitch_edge[1];
// stretch the pulse so IRQs don't get lost
reg [7:0] button_press_reg, button_release_reg;
always @ (posedge bus_clk)
if (bus_rst) begin
button_press_reg <= 8'h00;
button_release_reg <= 8'h00;
end else begin
button_press_reg <= {button_press_reg[6:0], button_press};
button_release_reg <= {button_release_reg[6:0], button_release};
end
wire button_press_irq = |button_press_reg;
wire button_release_irq = |button_release_reg;
/////////////////////////////////////////////////////////////////////
//
// Interrupts Fabric to PS
//
//////////////////////////////////////////////////////////////////////
wire [15:0] IRQ_F2P;
wire pmu_irq;
assign IRQ_F2P = {12'b0,
pmu_irq, // Interrupt 32
button_release_irq, // Interrupt 31
button_press_irq, // Interrupt 30
1'b0};
/////////////////////////////////////////////////////////////////////
//
// PS Connections
//
//////////////////////////////////////////////////////////////////////
wire [63:0] ps_gpio_in;
wire [63:0] ps_gpio_out;
wire [63:0] ps_gpio_tri;
e31x_ps_bd e31x_ps_bd_inst (
// DDR Interface
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_addr(DDR_ADDR),
.DDR_ba(DDR_BANKADDR),
.DDR_cas_n(DDR_CAS_N),
.DDR_ck_n(DDR_CLK_N),
.DDR_ck_p(DDR_CLK),
.DDR_cke(DDR_CKE),
.DDR_cs_n(DDR_CS_N),
.DDR_dm(DDR_DM),
.DDR_dq(DDR_DQ),
.DDR_dqs_n(DDR_DQS_N),
.DDR_dqs_p(DDR_DQS),
.DDR_odt(DDR_ODT),
.DDR_ras_n(DDR_RAS_N),
.DDR_reset_n(DDR_RESET_N),
.DDR_we_n(DDR_WE_N),
// Clocks
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(FCLK_CLK1),
.FCLK_CLK2(FCLK_CLK2),
.FCLK_CLK3(FCLK_CLK3),
// Resets
.FCLK_RESET0_N(FCLK_RESET0_N),
// GPIO
.GPIO_0_tri_i(ps_gpio_in),
.GPIO_0_tri_o(ps_gpio_out),
.GPIO_0_tri_t(ps_gpio_tri),
// Interrupts
.IRQ_F2P(IRQ_F2P),
// MIO
.MIO(MIO),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
// SPI
.SPI0_MISO_I(CAT_MISO),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(CAT_MOSI),
.SPI0_MOSI_T(),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(CAT_SCLK),
.SPI0_SCLK_T(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_I(1'b1),
.SPI0_SS_O(CAT_CS),
.SPI0_SS_T(),
.SPI1_MISO_I(),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_MOSI_I(),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_SCLK_I(),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_I(),
.SPI1_SS_O(),
.SPI1_SS_T(),
// USB
.USBIND_0_port_indctl(),
.USBIND_0_vbus_pwrfault(),
.USBIND_0_vbus_pwrselect(),
.bus_clk(bus_clk),
.bus_rstn(~bus_rst),
.clk40(clk40),
.clk40_rstn(clk40_rstn),
.S_AXI_GP0_ACLK(clk40),
.S_AXI_GP0_ARESETN(clk40_rstn),
// XBAR Regport
.m_axi_xbar_araddr(m_axi_xbar_araddr),
.m_axi_xbar_arprot(m_axi_xbar_arprot),
.m_axi_xbar_arready(m_axi_xbar_arready),
.m_axi_xbar_arvalid(m_axi_xbar_arvalid),
.m_axi_xbar_awaddr(m_axi_xbar_awaddr),
.m_axi_xbar_awprot(m_axi_xbar_awprot),
.m_axi_xbar_awready(m_axi_xbar_awready),
.m_axi_xbar_awvalid(m_axi_xbar_awvalid),
.m_axi_xbar_bready(m_axi_xbar_bready),
.m_axi_xbar_bresp(m_axi_xbar_bresp),
.m_axi_xbar_bvalid(m_axi_xbar_bvalid),
.m_axi_xbar_rdata(m_axi_xbar_rdata),
.m_axi_xbar_rready(m_axi_xbar_rready),
.m_axi_xbar_rresp(m_axi_xbar_rresp),
.m_axi_xbar_rvalid(m_axi_xbar_rvalid),
.m_axi_xbar_wdata(m_axi_xbar_wdata),
.m_axi_xbar_wready(m_axi_xbar_wready),
.m_axi_xbar_wstrb(m_axi_xbar_wstrb),
.m_axi_xbar_wvalid(m_axi_xbar_wvalid),
// PMU
.m_axi_pmu_araddr(m_axi_pmu_araddr),
.m_axi_pmu_arprot(m_axi_pmu_arprot),
.m_axi_pmu_arready(m_axi_pmu_arready),
.m_axi_pmu_arvalid(m_axi_pmu_arvalid),
.m_axi_pmu_awaddr(m_axi_pmu_awaddr),
.m_axi_pmu_awprot(m_axi_pmu_awprot),
.m_axi_pmu_awready(m_axi_pmu_awready),
.m_axi_pmu_awvalid(m_axi_pmu_awvalid),
.m_axi_pmu_bready(m_axi_pmu_bready),
.m_axi_pmu_bresp(m_axi_pmu_bresp),
.m_axi_pmu_bvalid(m_axi_pmu_bvalid),
.m_axi_pmu_rdata(m_axi_pmu_rdata),
.m_axi_pmu_rready(m_axi_pmu_rready),
.m_axi_pmu_rresp(m_axi_pmu_rresp),
.m_axi_pmu_rvalid(m_axi_pmu_rvalid),
.m_axi_pmu_wdata(m_axi_pmu_wdata),
.m_axi_pmu_wready(m_axi_pmu_wready),
.m_axi_pmu_wstrb(m_axi_pmu_wstrb),
.m_axi_pmu_wvalid(m_axi_pmu_wvalid),
// DMA
.s_axis_dma_tdata(s_axis_dma_tdata),
.s_axis_dma_tdest(s_axis_dma_tdest),
.s_axis_dma_tlast(s_axis_dma_tlast),
.s_axis_dma_tready(s_axis_dma_tready),
.s_axis_dma_tvalid(s_axis_dma_tvalid),
.m_axis_dma_tdata(m_axis_dma_tdata),
.m_axis_dma_tuser(m_axis_dma_tuser),
.m_axis_dma_tlast(m_axis_dma_tlast),
.m_axis_dma_tready(m_axis_dma_tready),
.m_axis_dma_tvalid(m_axis_dma_tvalid)
);
/////////////////////////////////////////////////////////////////////
//
// AD9361 Interface
//
/////////////////////////////////////////////////////////////////////
wire [REG_DWIDTH-1:0] dboard_ctrl;
wire [REG_DWIDTH-1:0] dboard_status;
wire mimo_busclk;
wire tx_pll_lock_busclk, rx_pll_lock_busclk;
wire codec_arst;
wire [NUM_CHANNELS*32-1:0] rx_flat, tx_flat;
wire [11:0] rx_i0, rx_q0, tx_i0, tx_q0;
wire [11:0] rx_i1, rx_q1, tx_i1, tx_q1;
wire rx_stb, tx_stb;
wire [NUM_CHANNELS-1:0] rx_atr, tx_atr;
assign rx_flat = {rx_i1, 4'd0, rx_q1, 4'd0,
rx_i0, 4'd0, rx_q0, 4'd0};
assign tx_q0 = tx_flat[15:4];
assign tx_i0 = tx_flat[31:20];
assign tx_q1 = tx_flat[47:36];
assign tx_i1 = tx_flat[63:52];
assign mimo_busclk = dboard_ctrl[0];
assign codec_arst = dboard_ctrl[1];
synchronizer synchronizer_tx_pll_lock (
.clk(bus_clk), .rst(1'b0), .in(CAT_CTRL_OUT[7]), .out(tx_pll_lock_busclk)
);
synchronizer synchronizer_rx_pll_lock (
.clk(bus_clk), .rst(1'b0), .in(CAT_CTRL_OUT[6]), .out(rx_pll_lock_busclk)
);
assign dboard_status = {
20'b0,
tcxo_status, // TCXO satus {plllck, is_10meg, is_pps, refclk}
tx_pll_lock_busclk, // TX PLL Lock
rx_pll_lock_busclk, // RX PLL Lock
6'b0
};
e310_io e310_io (
//.areset(codec_arst), TODO
.areset(bus_rst),
.mimo(mimo_busclk),
// Baseband sample interface
.radio_clk(radio_clk),
.radio_rst(radio_rst),
.rx_i0(rx_i1),
.rx_q0(rx_q1),
.rx_i1(rx_i0),
.rx_q1(rx_q0),
.rx_stb(rx_stb),
.tx_i0(tx_i1),
.tx_q0(tx_q1),
.tx_i1(tx_i0),
.tx_q1(tx_q0),
.tx_stb(tx_stb),
// AD9361 interface
.rx_clk(CAT_DATA_CLK),
.rx_frame(CAT_RX_FRAME),
.rx_data(CAT_P0_D),
.tx_clk(CAT_FB_CLK),
.tx_frame(CAT_TX_FRAME),
.tx_data(CAT_P1_D)
);
assign CAT_CTRL_IN = 4'b1;
assign CAT_ENAGC = 1'b1;
assign CAT_TXNRX = 1'b1;
assign CAT_ENABLE = 1'b1;
assign CAT_RESET = ~bus_rst; // Operates active-low, really CAT_RESET_B
assign CAT_SYNC = 1'b0;
/////////////////////////////////////////////////////////////////////
//
// DB GPIO Interface
// - Control Filter Banks
// - LEDs
//
/////////////////////////////////////////////////////////////////////
// Flattened Radio GPIO control
wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_out_flat;
wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_ddr_flat;
wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_in_flat;
wire [32*NUM_CHANNELS-1:0] leds_flat;
// Radio GPIO control
wire [DB_GPIO_WIDTH-1:0] db_gpio_in[0:NUM_CHANNELS-1];
wire [DB_GPIO_WIDTH-1:0] db_gpio_out[0:NUM_CHANNELS-1];
wire [DB_GPIO_WIDTH-1:0] db_gpio_ddr[0:NUM_CHANNELS-1];
wire [DB_GPIO_WIDTH-1:0] db_gpio_pins[0:NUM_CHANNELS-1];
wire [31:0] leds[0:NUM_CHANNELS-1];
genvar i;
generate
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin
assign db_gpio_in_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH] = db_gpio_in[i];
assign db_gpio_out[i] = db_gpio_out_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH];
assign db_gpio_ddr[i] = db_gpio_ddr_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH];
assign leds[i] = leds_flat[32*i +: 32];
gpio_atr_io #(
.WIDTH(DB_GPIO_WIDTH)
) gpio_atr_db_inst (
.clk(radio_clk),
.gpio_pins(db_gpio_pins[i]),
.gpio_ddr(db_gpio_ddr[i]),
.gpio_out(db_gpio_out[i]),
.gpio_in(db_gpio_in[i])
);
end
endgenerate
// DB_GPIO and LED pin assignments with software mapping
wire [2:0] TX1_BANDSEL;
wire [2:0] TX2_BANDSEL;
// Channel 0
assign {VCRX1_V1, // [15:15]
VCRX1_V2, // [14:14]
VCTXRX1_V1, // [13:13]
VCTXRX1_V2, // [12:12]
TX_ENABLE1B, // [11:11]
TX_ENABLE1A, // [10:10]
RX1C_BANDSEL, // [9:8]
RX1B_BANDSEL, // [7:6]
RX1_BANDSEL, // [5:3]
TX1_BANDSEL // [2:0]
} = db_gpio_pins[1];
assign {LED_RX1_RX,
LED_TXRX1_TX,
LED_TXRX1_RX
} = leds[1];
// Channel 1
assign {VCRX2_V1,
VCRX2_V2,
VCTXRX2_V1,
VCTXRX2_V2,
TX_ENABLE2B,
TX_ENABLE2A,
RX2C_BANDSEL,
RX2B_BANDSEL,
RX2_BANDSEL,
TX2_BANDSEL
} = db_gpio_pins[0];
assign {LED_RX2_RX,
LED_TXRX2_TX,
LED_TXRX2_RX
} = leds[0];
// It is okay to OR here as the both channels must be set to the same freq.
// This is needed so software does not have to set properties of radio core 0
// when only using radio core 1.
assign TX_BANDSEL = TX1_BANDSEL | TX2_BANDSEL;
/////////////////////////////////////////////////////////////////////
//
// Front-Panel GPIO
//
/////////////////////////////////////////////////////////////////////
wire [FP_GPIO_WIDTH-1:0] fp_gpio_in;
wire [FP_GPIO_WIDTH-1:0] fp_gpio_out;
wire [FP_GPIO_WIDTH-1:0] fp_gpio_tri;
gpio_atr_io #(.WIDTH(FP_GPIO_WIDTH)) fp_gpio_atr_inst (
.clk(radio_clk), .gpio_pins(PL_GPIO),
.gpio_ddr(fp_gpio_tri), .gpio_out(fp_gpio_out), .gpio_in(fp_gpio_in)
);
/////////////////////////////////////////////////////////////////////
//
// E320 Core:
// - xbar
// - Radio
// - DMA
// - DRAM
// - CEs
//
//////////////////////////////////////////////////////////////////////
wire [31:0] build_datestamp;
USR_ACCESSE2 usr_access_i (
.DATA(build_datestamp), .CFGCLK(), .DATAVALID()
);
e31x_core #(
.REG_AWIDTH(REG_AWIDTH),
.BUS_CLK_RATE(BUS_CLK_RATE),
.NUM_SFP_PORTS(NUM_SFP_PORTS),
.NUM_RADIOS(NUM_RADIOS),
.NUM_CHANNELS_PER_RADIO(NUM_CHANNELS_PER_RADIO),
.NUM_CHANNELS(NUM_CHANNELS),
.NUM_DBOARDS(NUM_DBOARDS),
.NUM_CHANNELS_PER_DBOARD(NUM_CHANNELS_PER_RADIO),
.FP_GPIO_WIDTH(FP_GPIO_WIDTH),
.DB_GPIO_WIDTH(DB_GPIO_WIDTH)
) e31x_core_inst (
//Clocks and resets
.radio_clk(radio_clk),
.radio_rst(radio_rst),
.bus_clk(bus_clk),
.bus_rst(bus_rst),
// Clocking and PPS Controls/Indicators
.pps_refclk(pps),
.refclk_locked(reflck),
.pps_select(pps_select),
.s_axi_aclk(clk40),
.s_axi_aresetn(clk40_rstn),
// AXI4-Lite: Write address port (domain: s_axi_aclk)
.s_axi_awaddr(m_axi_xbar_awaddr),
.s_axi_awvalid(m_axi_xbar_awvalid),
.s_axi_awready(m_axi_xbar_awready),
// AXI4-Lite: Write data port (domain: s_axi_aclk)
.s_axi_wdata(m_axi_xbar_wdata),
.s_axi_wstrb(m_axi_xbar_wstrb),
.s_axi_wvalid(m_axi_xbar_wvalid),
.s_axi_wready(m_axi_xbar_wready),
// AXI4-Lite: Write response port (domain: s_axi_aclk)
.s_axi_bresp(m_axi_xbar_bresp),
.s_axi_bvalid(m_axi_xbar_bvalid),
.s_axi_bready(m_axi_xbar_bready),
// AXI4-Lite: Read address port (domain: s_axi_aclk)
.s_axi_araddr(m_axi_xbar_araddr),
.s_axi_arvalid(m_axi_xbar_arvalid),
.s_axi_arready(m_axi_xbar_arready),
// AXI4-Lite: Read data port (domain: s_axi_aclk)
.s_axi_rdata(m_axi_xbar_rdata),
.s_axi_rresp(m_axi_xbar_rresp),
.s_axi_rvalid(m_axi_xbar_rvalid),
.s_axi_rready(m_axi_xbar_rready),
// Radio ATR
.rx_atr(rx_atr),
.tx_atr(tx_atr),
// Front-Panel GPIO
.fp_gpio_in(fp_gpio_in),
.fp_gpio_tri(fp_gpio_tri),
.fp_gpio_out(fp_gpio_out),
// PS GPIO Connection
.ps_gpio_tri(ps_gpio_tri[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1: FP_GPIO_OFFSET]),
.ps_gpio_out(ps_gpio_out[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1: FP_GPIO_OFFSET]),
.ps_gpio_in(ps_gpio_in[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1: FP_GPIO_OFFSET]),
// DB GPIO
.db_gpio_out_flat(db_gpio_out_flat),
.db_gpio_ddr_flat(db_gpio_ddr_flat),
.db_gpio_in_flat(db_gpio_in_flat),
.db_gpio_fab_flat(32'b0),
// TX/RX LEDs
.leds_flat(leds_flat),
// Radio Strobes
.rx_stb({NUM_CHANNELS{rx_stb}}),
.tx_stb({NUM_CHANNELS{tx_stb}}),
// Radio Data
.rx(rx_flat),
.tx(tx_flat),
// DMA to PS
.m_dma_tdata(s_axis_dma_tdata),
.m_dma_tdest(s_axis_dma_tdest),
.m_dma_tlast(s_axis_dma_tlast),
.m_dma_tready(s_axis_dma_tready),
.m_dma_tvalid(s_axis_dma_tvalid),
.s_dma_tdata(m_axis_dma_tdata),
.s_dma_tuser(m_axis_dma_tuser),
.s_dma_tlast(m_axis_dma_tlast),
.s_dma_tready(m_axis_dma_tready),
.s_dma_tvalid(m_axis_dma_tvalid),
.build_datestamp(build_datestamp),
.sfp_ports_info(),
.dboard_status(dboard_status),
.xadc_readback(32'h0), //Unused
.fp_gpio_ctrl(), //Unused
.dboard_ctrl(dboard_ctrl)
);
/////////////////////////////////////////////////////////////////////
//
// PL DDR3 Memory Interface
//
/////////////////////////////////////////////////////////////////////
//wire pl_dram_clk = FCLK_CLK3;
//wire pl_dram_rst = ~FCLK_RESET0_N;
//example_top inst_example_top
//(
// .ddr3_dq (PL_DDR3_DQ),
// .ddr3_dqs_n (PL_DDR3_DQS_N),
// .ddr3_dqs_p (PL_DDR3_DQS_P),
// .ddr3_addr (PL_DDR3_ADDR),
// .ddr3_ba (PL_DDR3_BA),
// .ddr3_ras_n (PL_DDR3_RAS_N),
// .ddr3_cas_n (PL_DDR3_CAS_N),
// .ddr3_we_n (PL_DDR3_WE_N),
// .ddr3_reset_n (PL_DDR3_RESET_N),
// .ddr3_ck_p (PL_DDR3_CK_P),
// .ddr3_ck_n (PL_DDR3_CK_N),
// .ddr3_cke (PL_DDR3_CKE),
// .ddr3_dm (PL_DDR3_DM),
// .ddr3_odt (PL_DDR3_ODT),
// .sys_clk_i (PL_DDR3_SYSCLK),
// .clk_ref_i (pl_dram_clk),
// .tg_compare_error (),
// .init_calib_complete (),
// .sys_rst (pl_dram_rst)
//);
// PMU
axi_pmu inst_axi_pmu (
.s_axi_aclk(clk40), // TODO: Original design used bus_clk
.s_axi_areset(clk40_rst),
.ss(AVR_CS_R),
.mosi(AVR_MOSI_R),
.sck(AVR_SCK_R),
.miso(AVR_MISO_R),
// AXI4-Lite: Write address port (domain: s_axi_aclk)
.s_axi_awaddr(m_axi_pmu_awaddr),
.s_axi_awvalid(m_axi_pmu_awvalid),
.s_axi_awready(m_axi_pmu_awready),
// AXI4-Lite: Write data port (domain: s_axi_aclk)
.s_axi_wdata(m_axi_pmu_wdata),
.s_axi_wstrb(m_axi_pmu_wstrb),
.s_axi_wvalid(m_axi_pmu_wvalid),
.s_axi_wready(m_axi_pmu_wready),
// AXI4-Lite: Write response port (domain: s_axi_aclk)
.s_axi_bresp(m_axi_pmu_bresp),
.s_axi_bvalid(m_axi_pmu_bvalid),
.s_axi_bready(m_axi_pmu_bready),
// AXI4-Lite: Read address port (domain: s_axi_aclk)
.s_axi_araddr(m_axi_pmu_araddr),
.s_axi_arvalid(m_axi_pmu_arvalid),
.s_axi_arready(m_axi_pmu_arready),
// AXI4-Lite: Read data port (domain: s_axi_aclk)
.s_axi_rdata(m_axi_pmu_rdata),
.s_axi_rresp(m_axi_pmu_rresp),
.s_axi_rvalid(m_axi_pmu_rvalid),
.s_axi_rready(m_axi_pmu_rready),
.s_axi_irq(pmu_irq)
);
assign AVR_IRQ = 1'b0;
endmodule // e31x
top/e31x/e31x_core.v
+681
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/////////////////////////////////////////////////////////////////////
//
// Copyright 2018 Ettus Research, A National Instruments Company
// Copyright 2019 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0
//
// Module: e31x_core
// Description:
// - Motherboard Registers
// - Crossbar
// - Noc Block Radio
// - Noc Block Dram Fifo
// - Radio Front End control
//
/////////////////////////////////////////////////////////////////////
`default_nettype none
module e31x_core #(
parameter REG_DWIDTH = 32, // Width of the AXI4-Lite data bus (must be 32 or 64)
parameter REG_AWIDTH = 32, // Width of the address bus
parameter BUS_CLK_RATE = 200000000, // bus_clk rate
parameter NUM_SFP_PORTS = 0, // Number of SFP Ports
parameter NUM_RADIOS = 1,
parameter NUM_CHANNELS_PER_RADIO = 2,
parameter NUM_CHANNELS = 2,
parameter NUM_DBOARDS = 1,
parameter NUM_CHANNELS_PER_DBOARD = 2,
parameter FP_GPIO_WIDTH = 8, // Front panel GPIO width
parameter DB_GPIO_WIDTH = 16, // Daughterboard GPIO width
parameter CHDR_WIDTH = 16'd64 ,
parameter RFNOC_PROTOVER = {8'd1, 8'd0}
)(
// Clocks and resets
input wire radio_clk,
input wire radio_rst,
input wire bus_clk,
input wire bus_rst,
// Motherboard Registers: AXI lite interface
input wire s_axi_aclk,
input wire s_axi_aresetn,
input wire [REG_AWIDTH-1:0] s_axi_awaddr,
input wire s_axi_awvalid,
output wire s_axi_awready,
input wire [REG_DWIDTH-1:0] s_axi_wdata,
input wire [REG_DWIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wvalid,
output wire s_axi_wready,
output wire [1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
input wire [REG_AWIDTH-1:0] s_axi_araddr,
input wire s_axi_arvalid,
output wire s_axi_arready,
output wire [REG_DWIDTH-1:0] s_axi_rdata,
output wire [1:0] s_axi_rresp,
output wire s_axi_rvalid,
input wire s_axi_rready,
// PPS and Clock Control
input wire pps_refclk,
input wire refclk_locked,
output reg [1:0] pps_select,
// PS GPIO source
input wire [FP_GPIO_WIDTH-1:0] ps_gpio_out,
input wire [FP_GPIO_WIDTH-1:0] ps_gpio_tri,
output wire [FP_GPIO_WIDTH-1:0] ps_gpio_in,
// Front Panel GPIO
input wire [FP_GPIO_WIDTH-1:0] fp_gpio_in,
output wire [FP_GPIO_WIDTH-1:0] fp_gpio_tri,
output wire [FP_GPIO_WIDTH-1:0] fp_gpio_out,
// Radio GPIO control
output wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_out_flat,
output wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_ddr_flat,
input wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_in_flat,
input wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_fab_flat,
// TX/RX LEDs
output wire [32*NUM_CHANNELS-1:0] leds_flat,
// Radio ATR
output wire [NUM_CHANNELS-1:0] rx_atr,
output wire [NUM_CHANNELS-1:0] tx_atr,
// Radio Data
input wire [NUM_CHANNELS-1:0] rx_stb,
input wire [NUM_CHANNELS-1:0] tx_stb,
input wire [32*NUM_CHANNELS-1:0] rx,
output wire [32*NUM_CHANNELS-1:0] tx,
// DMA xport adapter to PS
input wire [63:0] s_dma_tdata,
input wire [3:0] s_dma_tuser,
input wire s_dma_tlast,
output wire s_dma_tready,
input wire s_dma_tvalid,
output wire [63:0] m_dma_tdata,
output wire [3:0] m_dma_tdest,
output wire m_dma_tlast,
input wire m_dma_tready,
output wire m_dma_tvalid,
// Misc
input wire [31:0] build_datestamp,
input wire [31:0] sfp_ports_info,
input wire [31:0] dboard_status,
input wire [31:0] xadc_readback,
output reg [31:0] fp_gpio_ctrl,
output reg [31:0] dboard_ctrl,
output reg [15:0] device_id
);
/////////////////////////////////////////////////////////////////////////////////
//
// FPGA Compatibility Number
// Rules for modifying compat number:
// - Major is updated when the FPGA is changed and requires a software
// change as a result.
// - Minor is updated when a new feature is added to the FPGA that does not
// break software compatibility.
//
/////////////////////////////////////////////////////////////////////////////////
localparam [15:0] COMPAT_MAJOR = 16'd5;
localparam [15:0] COMPAT_MINOR = 16'd0;
/////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
//
// Motherboard Registers
//
/////////////////////////////////////////////////////////////////////////////////
// Register base
localparam REG_BASE_MISC = 14'h0;
localparam REG_BASE_TIMEKEEPER = 14'h1000;
// Misc Registers
localparam REG_COMPAT_NUM = REG_BASE_MISC + 14'h00;
localparam REG_DATESTAMP = REG_BASE_MISC + 14'h04;
localparam REG_GIT_HASH = REG_BASE_MISC + 14'h08;
localparam REG_SCRATCH = REG_BASE_MISC + 14'h0C;
localparam REG_DEVICE_ID = REG_BASE_MISC + 14'h10;
localparam REG_RFNOC_INFO = REG_BASE_MISC + 14'h14;
localparam REG_CLOCK_CTRL = REG_BASE_MISC + 14'h18;
localparam REG_XADC_READBACK = REG_BASE_MISC + 14'h1C;
localparam REG_BUS_CLK_RATE = REG_BASE_MISC + 14'h20;
localparam REG_BUS_CLK_COUNT = REG_BASE_MISC + 14'h24;
localparam REG_SFP_PORT_INFO = REG_BASE_MISC + 14'h28;
localparam REG_FP_GPIO_CTRL = REG_BASE_MISC + 14'h2C;
localparam REG_FP_GPIO_MASTER = REG_BASE_MISC + 14'h30;
localparam REG_FP_GPIO_RADIO_SRC = REG_BASE_MISC + 14'h34;
localparam REG_DBOARD_CTRL = REG_BASE_MISC + 14'h40;
localparam REG_DBOARD_STATUS = REG_BASE_MISC + 14'h44;
localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48;
localparam NUM_TIMEKEEPERS = 16'd1;
wire m_ctrlport_req_wr;
wire m_ctrlport_req_rd;
wire [19:0] m_ctrlport_req_addr;
wire [31:0] m_ctrlport_req_data;
wire m_ctrlport_req_has_time;
wire [63:0] m_ctrlport_req_time;
wire m_ctrlport_resp_ack;
wire [31:0] m_ctrlport_resp_data;
reg [31:0] fp_gpio_master_reg = 32'h0;
reg [31:0] fp_gpio_src_reg = 32'h0;
wire reg_wr_req;
wire [REG_AWIDTH-1:0] reg_wr_addr;
wire [REG_DWIDTH-1:0] reg_wr_data;
wire reg_rd_req;
wire [REG_AWIDTH-1:0] reg_rd_addr;
wire reg_rd_resp;
wire [REG_DWIDTH-1:0] reg_rd_data;
reg reg_rd_resp_glob;
reg [REG_DWIDTH-1:0] reg_rd_data_glob;
wire reg_rd_resp_tk;
wire [REG_DWIDTH-1:0] reg_rd_data_tk;
reg [31:0] scratch_reg = 32'h0;
reg [31:0] bus_counter = 32'h0;
always @(posedge bus_clk) begin
if (bus_rst)
bus_counter <= 32'd0;
else
bus_counter <= bus_counter + 32'd1;
end
// Regport Master to convert AXI4-Lite to regport
axil_regport_master #(
.DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
.AWIDTH (REG_AWIDTH), // Width of the address bus
.WRBASE (0), // Write address base
.RDBASE (0), // Read address base
.TIMEOUT (10) // log2(timeout). Read will timeout after (2^TIMEOUT - 1) cycles
) core_regport_master_i (
// Clock and reset
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
// AXI4-Lite: Write address port (domain: s_axi_aclk)
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// AXI4-Lite: Write data port (domain: s_axi_aclk)
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// AXI4-Lite: Write response port (domain: s_axi_aclk)
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// AXI4-Lite: Read address port (domain: s_axi_aclk)
.s_axi_araddr (s_axi_araddr),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// AXI4-Lite: Read data port (domain: s_axi_aclk)
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// Register port: Write port (domain: reg_clk)
.reg_clk (bus_clk),
.reg_wr_req (reg_wr_req),
.reg_wr_addr (reg_wr_addr),
.reg_wr_data (reg_wr_data),
.reg_wr_keep (/*unused*/),
// Register port: Read port (domain: reg_clk)
.reg_rd_req (reg_rd_req),
.reg_rd_addr (reg_rd_addr),
.reg_rd_resp (reg_rd_resp),
.reg_rd_data (reg_rd_data)
);
//--------------------------------------------------------------------
// Global Registers
// -------------------------------------------------------------------
// Write Registers
always @ (posedge bus_clk) begin
if (bus_rst) begin
scratch_reg <= 32'h0;
pps_select <= 2'b01; // Default to internal
fp_gpio_ctrl <= 32'h9; // Default to OFF - 4'b1001
dboard_ctrl <= 32'h1; // Default to mimo
device_id <= 16'h0;
end else if (reg_wr_req) begin
case (reg_wr_addr)
REG_DEVICE_ID: begin
device_id <= reg_wr_data[15:0];
end
REG_FP_GPIO_MASTER: begin
fp_gpio_master_reg <= reg_wr_data;
end
REG_FP_GPIO_RADIO_SRC: begin
fp_gpio_src_reg <= reg_wr_data;
end
REG_SCRATCH: begin
scratch_reg <= reg_wr_data;
end
REG_CLOCK_CTRL: begin
pps_select <= reg_wr_data[1:0];
end
REG_FP_GPIO_CTRL: begin
fp_gpio_ctrl <= reg_wr_data;
end
REG_DBOARD_CTRL: begin
dboard_ctrl <= reg_wr_data;
end
endcase
end
end
// Read Registers
always @ (posedge bus_clk) begin
if (bus_rst) begin
reg_rd_resp_glob <= 1'b0;
end
else begin
if (reg_rd_req) begin
reg_rd_resp_glob <= 1'b1;
case (reg_rd_addr)
REG_DEVICE_ID:
reg_rd_data_glob <= device_id;
REG_RFNOC_INFO:
reg_rd_data_glob <= {CHDR_WIDTH[15:0], RFNOC_PROTOVER[15:0]};
REG_COMPAT_NUM:
reg_rd_data_glob <= {COMPAT_MAJOR[15:0], COMPAT_MINOR[15:0]};
REG_FP_GPIO_CTRL:
reg_rd_data_glob <= fp_gpio_ctrl;
REG_FP_GPIO_MASTER:
reg_rd_data_glob <= fp_gpio_master_reg;
REG_FP_GPIO_RADIO_SRC:
reg_rd_data_glob <= fp_gpio_src_reg;
REG_DATESTAMP:
reg_rd_data_glob <= build_datestamp;
REG_GIT_HASH:
reg_rd_data_glob <= `GIT_HASH;
REG_SCRATCH:
reg_rd_data_glob <= scratch_reg;
REG_CLOCK_CTRL: begin
reg_rd_data_glob <= 32'b0;
reg_rd_data_glob[1:0] <= pps_select;
reg_rd_data_glob[3] <= refclk_locked;
end
REG_XADC_READBACK:
reg_rd_data_glob <= xadc_readback;
REG_BUS_CLK_RATE:
reg_rd_data_glob <= BUS_CLK_RATE;
REG_BUS_CLK_COUNT:
reg_rd_data_glob <= bus_counter;
REG_SFP_PORT_INFO:
reg_rd_data_glob <= sfp_ports_info;
REG_DBOARD_CTRL:
reg_rd_data_glob <= dboard_ctrl;
REG_DBOARD_STATUS:
reg_rd_data_glob <= dboard_status;
REG_NUM_TIMEKEEPERS:
reg_rd_data_glob <= NUM_TIMEKEEPERS;
default:
reg_rd_resp_glob <= 1'b0;
endcase
end
else if (reg_rd_resp_glob) begin
reg_rd_resp_glob <= 1'b0;
end
end
end
wire pps_radioclk;
// Synchronize the PPS signal to the radio clock domain
synchronizer pps_radio_sync (
.clk(radio_clk), .rst(1'b0), .in(pps_refclk), .out(pps_radioclk)
);
/////////////////////////////////////////////////////////////////////////////
//
// DMA Transport Adapter
//
/////////////////////////////////////////////////////////////////////////////
wire [63:0] dmao_tdata;
wire dmao_tlast;
wire dmao_tvalid;
wire dmao_tready;
wire [63:0] dmai_tdata;
wire dmai_tlast;
wire dmai_tvalid;
wire dmai_tready;
liberio_chdr64_adapter #(
.DMA_ID_WIDTH (4)
) dma_xport_adapter (
.clk (bus_clk),
.rst (bus_rst),
.device_id (device_id),
// From DMA engine to core
.s_dma_tdata (s_dma_tdata),
.s_dma_tuser (s_dma_tuser),
.s_dma_tlast (s_dma_tlast),
.s_dma_tvalid (s_dma_tvalid),
.s_dma_tready (s_dma_tready),
// From core to DMA engine
.m_dma_tdata (m_dma_tdata),
.m_dma_tuser (m_dma_tdest),
.m_dma_tlast (m_dma_tlast),
.m_dma_tvalid (m_dma_tvalid),
.m_dma_tready (m_dma_tready),
// CHDR buses
.s_chdr_tdata (dmao_tdata),
.s_chdr_tlast (dmao_tlast),
.s_chdr_tvalid (dmao_tvalid),
.s_chdr_tready (dmao_tready),
.m_chdr_tdata (dmai_tdata),
.m_chdr_tlast (dmai_tlast),
.m_chdr_tvalid (dmai_tvalid),
.m_chdr_tready (dmai_tready)
);
/////////////////////////////////////////////////////////////////////////////
//
// Radio Daughter board and Front End Control
//
/////////////////////////////////////////////////////////////////////////////
// Radio Daughter board GPIO
wire [DB_GPIO_WIDTH-1:0] db_gpio_in[0:NUM_CHANNELS-1];
wire [DB_GPIO_WIDTH-1:0] db_gpio_out[0:NUM_CHANNELS-1];
wire [DB_GPIO_WIDTH-1:0] db_gpio_ddr[0:NUM_CHANNELS-1];
wire [DB_GPIO_WIDTH-1:0] db_gpio_fab[0:NUM_CHANNELS-1];
wire [31:0] radio_gpio_out[0:NUM_CHANNELS-1];
wire [31:0] radio_gpio_ddr[0:NUM_CHANNELS-1];
wire [31:0] radio_gpio_in[0:NUM_CHANNELS-1];
wire [31:0] leds[0:NUM_CHANNELS-1];
// Daughter board I/O
wire rx_running[0:NUM_CHANNELS-1], tx_running[0:NUM_CHANNELS-1];
wire [31:0] rx_int[0:NUM_CHANNELS-1], rx_data[0:NUM_CHANNELS-1], tx_int[0:NUM_CHANNELS-1], tx_data[0:NUM_CHANNELS-1];
//wire rx_stb[0:NUM_CHANNELS-1], tx_stb[0:NUM_CHANNELS-1];
wire db_fe_set_stb[0:NUM_CHANNELS-1];
wire [7:0] db_fe_set_addr[0:NUM_CHANNELS-1];
wire [31:0] db_fe_set_data[0:NUM_CHANNELS-1];
wire db_fe_rb_stb[0:NUM_CHANNELS-1];
wire [7:0] db_fe_rb_addr[0:NUM_CHANNELS-1];
wire [63:0] db_fe_rb_data[0:NUM_CHANNELS-1];
wire [NUM_RADIOS-1:0] sync_out;
genvar i;
generate
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin
assign rx_atr[i] = rx_running[i];
assign tx_atr[i] = tx_running[i];
end
endgenerate
//------------------------------------
// Daughterboard Control
// -----------------------------------
localparam [7:0] SR_DB_BASE = 8'd160;
localparam [7:0] RB_DB_BASE = 8'd16;
generate
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: gen_db_control
db_control #(
.USE_SPI_CLK(0),
.SR_BASE(SR_DB_BASE),
.RB_BASE(RB_DB_BASE)
) db_control_i (
.clk(radio_clk), .reset(radio_rst),
.set_stb(db_fe_set_stb[i]), .set_addr(db_fe_set_addr[i]), .set_data(db_fe_set_data[i]),
.rb_stb(db_fe_rb_stb[i]), .rb_addr(db_fe_rb_addr[i]), .rb_data(db_fe_rb_data[i]),
.run_rx(rx_running[i]), .run_tx(tx_running[i]),
.misc_ins(32'h0), .misc_outs(),
.fp_gpio_in(radio_gpio_in[i]), .fp_gpio_out(radio_gpio_out[i]), .fp_gpio_ddr(radio_gpio_ddr[i]), .fp_gpio_fab(32'h0),
.db_gpio_in(db_gpio_in[i]), .db_gpio_out(db_gpio_out[i]), .db_gpio_ddr(db_gpio_ddr[i]), .db_gpio_fab(),
.leds(leds[i]),
.spi_clk(1'b0), .spi_rst(1'b0), .sen(), .sclk(), .mosi(), .miso(1'b0)
);
end
endgenerate
generate
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: gen_gpio_control
// Radio Data
assign rx_data[i] = rx[32*i+31:32*i];
assign tx[32*i+31:32*i] = tx_data[i];
// GPIO
assign db_gpio_out_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH] = db_gpio_out[i];
assign db_gpio_ddr_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH] = db_gpio_ddr[i];
assign db_gpio_in[i] = db_gpio_in_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH];
assign db_gpio_fab[i] = db_gpio_fab_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH];
// LEDs
assign leds_flat[32*i+31:32*i] = leds[i];
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
//
// Front-panel GPIO
//
/////////////////////////////////////////////////////////////////////////////
wire [FP_GPIO_WIDTH-1:0] radio_gpio_in_sync;
wire [FP_GPIO_WIDTH-1:0] radio_gpio_src_out;
reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_out_reg;
wire [FP_GPIO_WIDTH-1:0] radio_gpio_src_ddr;
reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_ddr_reg = ~0;
// Double-synchronize the inputs to the PS
synchronizer #(
.INITIAL_VAL(1'b0), .WIDTH(FP_GPIO_WIDTH)
) ps_gpio_in_sync_i (
.clk(bus_clk), .rst(1'b0), .in(fp_gpio_in), .out(ps_gpio_in)
);
// Double-synchronize the inputs to the radio
synchronizer #(
.INITIAL_VAL(1'b0), .WIDTH(FP_GPIO_WIDTH)
) radio_gpio_in_sync_i (
.clk(radio_clk), .rst(1'b0), .in(fp_gpio_in), .out(radio_gpio_in_sync)
);
// Map the double-synchronized inputs to all radio channels
generate
for (i=0; i<NUM_CHANNELS; i=i+1) begin: gen_fp_gpio_in_sync
assign radio_gpio_in[i][FP_GPIO_WIDTH-1:0] = radio_gpio_in_sync;
end
endgenerate
// For each of the FP GPIO bits, implement four control muxes
generate
for (i=0; i<FP_GPIO_WIDTH; i=i+1) begin: gpio_muxing_gen
// 1) Select which radio drives the output
assign radio_gpio_src_out[i] = radio_gpio_out[fp_gpio_src_reg[2*i+1:2*i]][i];
always @ (posedge radio_clk) begin
if (radio_rst) begin
radio_gpio_src_out_reg <= 0;
end else begin
radio_gpio_src_out_reg <= radio_gpio_src_out;
end
end
// 2) Select which radio drives the direction
assign radio_gpio_src_ddr[i] = radio_gpio_ddr[fp_gpio_src_reg[2*i+1:2*i]][i];
always @ (posedge radio_clk) begin
if (radio_rst) begin
radio_gpio_src_ddr_reg <= ~0;
end else begin
radio_gpio_src_ddr_reg <= radio_gpio_src_ddr;
end
end
// 3) Select if the radio or the ps drives the output
//
// The following implements a 2:1 mux in a LUT explicitly to avoid
// glitches that can be introduced by unexpected Vivado synthesis.
//
(* dont_touch = "TRUE" *) LUT3 #(
.INIT(8'hCA) // Specify LUT Contents. O = ~I2&I0 | I2&I1
) mux_out_i (
.O(fp_gpio_out[i]), // LUT general output. Mux output
.I0(radio_gpio_src_out_reg[i]), // LUT input. Input 1
.I1(ps_gpio_out[i]), // LUT input. Input 2
.I2(fp_gpio_master_reg[i]) // LUT input. Select bit
);
// 4) Select if the radio or the PS drives the direction
//
(* dont_touch = "TRUE" *) LUT3 #(
.INIT(8'hC5) // Specify LUT Contents. O = ~I2&I0 | I2&~I1
) mux_ddr_i (
.O(fp_gpio_tri[i]), // LUT general output. Mux output
.I0(radio_gpio_src_ddr_reg[i]), // LUT input. Input 1
.I1(ps_gpio_tri[i]), // LUT input. Input 2
.I2(fp_gpio_master_reg[i]) // LUT input. Select bit
);
end
endgenerate
// Regport Mux for response
regport_resp_mux #(
.WIDTH (32),
.NUM_SLAVES (2)
) reg_resp_mux_i (
.clk(bus_clk), .reset(bus_rst),
.sla_rd_resp({reg_rd_resp_tk, reg_rd_resp_glob}),
.sla_rd_data({reg_rd_data_tk, reg_rd_data_glob}),
.mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data)
);
// Timekeeper
wire [63:0] radio_time;
timekeeper #(
.BASE_ADDR (REG_BASE_TIMEKEEPER),
.TIME_INCREMENT (1'b1)
) timekeeper_i (
.tb_clk (radio_clk),
.tb_rst (radio_rst),
.s_ctrlport_clk (bus_clk),
.s_ctrlport_req_wr (reg_wr_req),
.s_ctrlport_req_rd (reg_rd_req),
.s_ctrlport_req_addr (reg_wr_req ? reg_wr_addr: reg_rd_addr),
.s_ctrlport_req_data (reg_wr_data),
.s_ctrlport_resp_ack (reg_rd_resp_tk),
.s_ctrlport_resp_data (reg_rd_data_tk),
.sample_rx_stb (rx_stb[0]),
.pps (pps_radioclk),
.tb_timestamp (radio_time),
.tb_timestamp_last_pps (),
.tb_period_ns_q32 ()
);
rfnoc_image_core #(
.PROTOVER(RFNOC_PROTOVER)
) rfnoc_image_core_i (
.chdr_aclk (bus_clk ),
.ctrl_aclk (bus_clk ), //TODO: X310 uses bus_clk_div2. we can also reduce it here.
.core_arst (bus_rst ),
.device_id (device_id ),
.radio_clk (radio_clk ),
.m_ctrlport_req_wr (m_ctrlport_req_wr ),
.m_ctrlport_req_rd (m_ctrlport_req_rd ),
.m_ctrlport_req_addr (m_ctrlport_req_addr ),
.m_ctrlport_req_data (m_ctrlport_req_data ),
.m_ctrlport_req_byte_en (),
.m_ctrlport_req_has_time (m_ctrlport_req_has_time),
.m_ctrlport_req_time (m_ctrlport_req_time ),
.m_ctrlport_resp_ack (m_ctrlport_resp_ack ),
.m_ctrlport_resp_status (2'b0),
.m_ctrlport_resp_data (m_ctrlport_resp_data ),
.radio_time (radio_time ),
.radio_rx_stb ({rx_stb[1], rx_stb[0] }),
.radio_rx_data ({rx_data[1], rx_data[0] }),
.radio_rx_running ({rx_running[1], rx_running[0]}),
.radio_tx_stb ({tx_stb[1], tx_stb[0] }),
.radio_tx_data ({tx_data[1], tx_data[0] }),
.radio_tx_running ({tx_running[1], tx_running[0]}),
.s_dma_tdata (dmai_tdata),
.s_dma_tlast (dmai_tlast),
.s_dma_tvalid (dmai_tvalid),
.s_dma_tready (dmai_tready),
.m_dma_tdata (dmao_tdata),
.m_dma_tlast (dmao_tlast),
.m_dma_tvalid (dmao_tvalid),
.m_dma_tready (dmao_tready)
);
//---------------------------------------------------------------------------
// Convert Control Port to Settings Bus
//---------------------------------------------------------------------------
ctrlport_to_settings_bus # (
.NUM_PORTS (2),
.USE_TIME (1)
) ctrlport_to_settings_bus_i (
.ctrlport_clk (radio_clk),
.ctrlport_rst (radio_rst),
.s_ctrlport_req_wr (m_ctrlport_req_wr),
.s_ctrlport_req_rd (m_ctrlport_req_rd),
.s_ctrlport_req_addr (m_ctrlport_req_addr),
.s_ctrlport_req_data (m_ctrlport_req_data),
.s_ctrlport_req_has_time (m_ctrlport_req_has_time),
.s_ctrlport_req_time (m_ctrlport_req_time),
.s_ctrlport_resp_ack (m_ctrlport_resp_ack),
.s_ctrlport_resp_data (m_ctrlport_resp_data),
.set_data ({db_fe_set_data[1], db_fe_set_data[0]}),
.set_addr ({db_fe_set_addr[1], db_fe_set_addr[0]}),
.set_stb ({db_fe_set_stb[1], db_fe_set_stb[0] }),
.set_time (),
.set_has_time (),
.rb_stb ({db_fe_rb_stb[1], db_fe_rb_stb[0] }),
.rb_addr ({db_fe_rb_addr[1], db_fe_rb_addr[0] }),
.rb_data ({db_fe_rb_data[1], db_fe_rb_data[0] }),
.timestamp (radio_time)
);
endmodule //e31x_core
`default_nettype wire
top/e31x/e31x_idle.v
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/////////////////////////////////////////////////////////////////////
//
// Copyright 2018-2019 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: e31x
// Description:
// E31x Top Level Idle
//
/////////////////////////////////////////////////////////////////////
module e31x (
// PS Connections
inout [53:0] MIO,
input PS_SRSTB,
input PS_CLK,
input PS_PORB,
inout DDR_CLK,
inout DDR_CLK_N,
inout DDR_CKE,
inout DDR_CS_N,
inout DDR_RAS_N,
inout DDR_CAS_N,
inout DDR_WEB,
inout [2:0] DDR_BANKADDR,
inout [14:0] DDR_ADDR,
inout DDR_ODT,
inout DDR_DRSTB,
inout [31:0] DDR_DQ,
inout [3:0] DDR_DM,
inout [3:0] DDR_DQS,
inout [3:0] DDR_DQS_N,
inout DDR_VRP,
inout DDR_VRN,
//AVR SPI IO
input AVR_CS_R,
output AVR_IRQ,
output AVR_MISO_R,
input AVR_MOSI_R,
input AVR_SCK_R,
input ONSWITCH_DB,
// pps connections
input GPS_PPS,
input PPS_EXT_IN,
// gpios, change to inout somehow
inout [5:0] PL_GPIO,
// RF Board connections
inout [99:0] DB_IO
);
// Clocks
wire bus_clk;
wire radio_clk;
wire reg_clk;
wire clk40;
wire FCLK_CLK0;
wire FCLK_CLK1;
// Resets
wire global_rst;
wire bus_rst;
wire radio_rst;
wire reg_rstn;
wire clk40_rst;
wire clk40_rstn;
wire FCLK_RESET0_N;
// PMU
wire [31:0] m_axi_pmu_araddr;
wire [2:0] m_axi_pmu_arprot;
wire m_axi_pmu_arready;
wire m_axi_pmu_arvalid;
wire [31:0] m_axi_pmu_awaddr;
wire [2:0] m_axi_pmu_awprot;
wire m_axi_pmu_awready;
wire m_axi_pmu_awvalid;
wire m_axi_pmu_bready;
wire [1:0] m_axi_pmu_bresp;
wire m_axi_pmu_bvalid;
wire [31:0] m_axi_pmu_rdata;
wire m_axi_pmu_rready;
wire [1:0] m_axi_pmu_rresp;
wire m_axi_pmu_rvalid;
wire [31:0] m_axi_pmu_wdata;
wire m_axi_pmu_wready;
wire [3:0] m_axi_pmu_wstrb;
wire m_axi_pmu_wvalid;
/////////////////////////////////////////////////////////////////////
//
// Resets:
// - PL - Bus Reset
// Radio Reset
// - PS - FCLK_RESET0_N --> clk40_rst(n)
//
//////////////////////////////////////////////////////////////////////
// Synchronous reset for the bus_clk domain
reset_sync bus_reset_gen (
.clk(bus_clk),
.reset_in(~FCLK_RESET0_N),
//.reset_in(~clocks_locked),
.reset_out(bus_rst)
);
// PS-based Resets //
//
// Synchronous reset for the clk40 domain. This is derived from the PS reset 0.
reset_sync clk40_reset_gen (
.clk(clk40),
.reset_in(~FCLK_RESET0_N),
.reset_out(clk40_rst)
);
// Invert for various modules.
assign clk40_rstn = ~clk40_rst;
assign reg_rstn = clk40_rstn;
/////////////////////////////////////////////////////////////////////
//
// Clocks and PPS
//
/////////////////////////////////////////////////////////////////////
wire [1:0] pps_select;
assign clk40 = FCLK_CLK1; // 40 MHz
assign bus_clk = FCLK_CLK0; // 100 MHz
assign reg_clk = clk40;
reg [2:0] pps_reg;
wire pps_ext = PPS_EXT_IN;
wire gps_pps = GPS_PPS;
// connect PPS input to GPIO so ntpd can use it
always @ (posedge bus_clk)
pps_reg <= bus_rst ? 3'b000 : {pps_reg[1:0], GPS_PPS};
assign ps_gpio_in[8] = pps_reg[2]; // 62
/////////////////////////////////////////////////////////////////////
//
// Power Button
//
//////////////////////////////////////////////////////////////////////
// register the debounced onswitch signal to detect edges,
// Note: ONSWITCH_DB is low active
reg [1:0] onswitch_edge;
always @ (posedge bus_clk)
onswitch_edge <= bus_rst ? 2'b00 : {onswitch_edge[0], ONSWITCH_DB};
wire button_press = ~ONSWITCH_DB & onswitch_edge[0] & onswitch_edge[1];
wire button_release = ONSWITCH_DB & ~onswitch_edge[0] & ~onswitch_edge[1];
// stretch the pulse so IRQs don't get lost
reg [7:0] button_press_reg, button_release_reg;
always @ (posedge bus_clk)
if (bus_rst) begin
button_press_reg <= 8'h00;
button_release_reg <= 8'h00;
end else begin
button_press_reg <= {button_press_reg[6:0], button_press};
button_release_reg <= {button_release_reg[6:0], button_release};
end
wire button_press_irq = |button_press_reg;
wire button_release_irq = |button_release_reg;
/////////////////////////////////////////////////////////////////////
//
// Interrupts Fabric to PS
//
//////////////////////////////////////////////////////////////////////
wire [15:0] IRQ_F2P;
wire pmu_irq;
assign IRQ_F2P = {12'b0,
pmu_irq, // Interrupt 32
button_release_irq, // Interrupt 31
button_press_irq, // Interrupt 30
1'b0};
/////////////////////////////////////////////////////////////////////
//
// PS Connections
//
//////////////////////////////////////////////////////////////////////
wire [63:0] ps_gpio_in;
wire [63:0] ps_gpio_out;
wire [63:0] ps_gpio_tri;
e31x_ps_bd e31x_ps_bd_inst (
// DDR Interface
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_addr(DDR_ADDR),
.DDR_ba(DDR_BANKADDR),
.DDR_cas_n(DDR_CAS_N),
.DDR_ck_n(DDR_CLK_N),
.DDR_ck_p(DDR_CLK),
.DDR_cke(DDR_CKE),
.DDR_cs_n(DDR_CS_N),
.DDR_dm(DDR_DM),
.DDR_dq(DDR_DQ),
.DDR_dqs_n(DDR_DQS_N),
.DDR_dqs_p(DDR_DQS),
.DDR_odt(DDR_ODT),
.DDR_ras_n(DDR_RAS_N),
.DDR_reset_n(DDR_RESET_N),
.DDR_we_n(DDR_WE_N),
// Clocks
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(FCLK_CLK1),
.FCLK_CLK2(),
.FCLK_CLK3(),
// Resets
.FCLK_RESET0_N(FCLK_RESET0_N),
// GPIO
.GPIO_0_tri_i(ps_gpio_in),
.GPIO_0_tri_o(ps_gpio_out),
.GPIO_0_tri_t(ps_gpio_tri),
// Interrupts
.IRQ_F2P(IRQ_F2P),
// MIO
.MIO(MIO),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
// SPI
.SPI0_MISO_I(),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_MOSI_I(),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_SCLK_I(),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_I(),
.SPI0_SS_O(),
.SPI0_SS_T(),
.SPI1_MISO_I(),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_MOSI_I(),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_SCLK_I(),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_I(),
.SPI1_SS_O(),
.SPI1_SS_T(),
// USB
.USBIND_0_port_indctl(),
.USBIND_0_vbus_pwrfault(),
.USBIND_0_vbus_pwrselect(),
.bus_clk(bus_clk),
.bus_rstn(~bus_rst),
.clk40(clk40),
.clk40_rstn(clk40_rstn),
.S_AXI_GP0_ACLK(clk40),
.S_AXI_GP0_ARESETN(clk40_rstn),
// XBAR Regport
.m_axi_xbar_araddr(),
.m_axi_xbar_arprot(),
.m_axi_xbar_arready(),
.m_axi_xbar_arvalid(),
.m_axi_xbar_awaddr(),
.m_axi_xbar_awprot(),
.m_axi_xbar_awready(),
.m_axi_xbar_awvalid(),
.m_axi_xbar_bready(),
.m_axi_xbar_bresp(),
.m_axi_xbar_bvalid(),
.m_axi_xbar_rdata(),
.m_axi_xbar_rready(),
.m_axi_xbar_rresp(),
.m_axi_xbar_rvalid(),
.m_axi_xbar_wdata(),
.m_axi_xbar_wready(),
.m_axi_xbar_wstrb(),
.m_axi_xbar_wvalid(),
// PMU
.m_axi_pmu_araddr(m_axi_pmu_araddr),
.m_axi_pmu_arprot(m_axi_pmu_arprot),
.m_axi_pmu_arready(m_axi_pmu_arready),
.m_axi_pmu_arvalid(m_axi_pmu_arvalid),
.m_axi_pmu_awaddr(m_axi_pmu_awaddr),
.m_axi_pmu_awprot(m_axi_pmu_awprot),
.m_axi_pmu_awready(m_axi_pmu_awready),
.m_axi_pmu_awvalid(m_axi_pmu_awvalid),
.m_axi_pmu_bready(m_axi_pmu_bready),
.m_axi_pmu_bresp(m_axi_pmu_bresp),
.m_axi_pmu_bvalid(m_axi_pmu_bvalid),
.m_axi_pmu_rdata(m_axi_pmu_rdata),
.m_axi_pmu_rready(m_axi_pmu_rready),
.m_axi_pmu_rresp(m_axi_pmu_rresp),
.m_axi_pmu_rvalid(m_axi_pmu_rvalid),
.m_axi_pmu_wdata(m_axi_pmu_wdata),
.m_axi_pmu_wready(m_axi_pmu_wready),
.m_axi_pmu_wstrb(m_axi_pmu_wstrb),
.m_axi_pmu_wvalid(m_axi_pmu_wvalid),
// DMA
.s_axis_dma_tdata(),
.s_axis_dma_tdest(),
.s_axis_dma_tlast(),
.s_axis_dma_tready(),
.s_axis_dma_tvalid(1'b0),
.m_axis_dma_tdata(),
.m_axis_dma_tuser(),
.m_axis_dma_tlast(),
.m_axis_dma_tready(1'b1),
.m_axis_dma_tvalid()
);
/////////////////////////////////////////////////////////////////////
//
// PMU
//
//////////////////////////////////////////////////////////////////////
axi_pmu inst_axi_pmu (
.s_axi_aclk(clk40), // TODO: Original design used bus_clk
.s_axi_areset(clk40_rst),
.ss(AVR_CS_R),
.mosi(AVR_MOSI_R),
.sck(AVR_SCK_R),
.miso(AVR_MISO_R),
// AXI4-Lite: Write address port (domain: s_axi_aclk)
.s_axi_awaddr(m_axi_pmu_awaddr),
.s_axi_awvalid(m_axi_pmu_awvalid),
.s_axi_awready(m_axi_pmu_awready),
// AXI4-Lite: Write data port (domain: s_axi_aclk)
.s_axi_wdata(m_axi_pmu_wdata),
.s_axi_wstrb(m_axi_pmu_wstrb),
.s_axi_wvalid(m_axi_pmu_wvalid),
.s_axi_wready(m_axi_pmu_wready),
// AXI4-Lite: Write response port (domain: s_axi_aclk)
.s_axi_bresp(m_axi_pmu_bresp),
.s_axi_bvalid(m_axi_pmu_bvalid),
.s_axi_bready(m_axi_pmu_bready),
// AXI4-Lite: Read address port (domain: s_axi_aclk)
.s_axi_araddr(m_axi_pmu_araddr),
.s_axi_arvalid(m_axi_pmu_arvalid),
.s_axi_arready(m_axi_pmu_arready),
// AXI4-Lite: Read data port (domain: s_axi_aclk)
.s_axi_rdata(m_axi_pmu_rdata),
.s_axi_rresp(m_axi_pmu_rresp),
.s_axi_rvalid(m_axi_pmu_rvalid),
.s_axi_rready(m_axi_pmu_rready),
.s_axi_irq(pmu_irq)
);
assign AVR_IRQ = 1'b0;
localparam DB_E31X_IDLE_OUT = {
1'b0, /* DB_EXP_18_24 (99) */
13'b0000000000000, /* leds & rx bandsels */
1'b0, /* CAT_FB_CLK (85) */
1'b0, /* CAT_TX_FRAME (84) */
1'b0, /* CAT_RX_DATA_CLK (83) */
25'b0000_0000_0000_0000_0000_0000_0, /* CAT_RX_FRAME(81), CAT_P0 & CAT_P1 (58)*/
1'b0, /* CAT_SYNC(57) */
4'b0000, /* CAT_ENAGC(56), CAT_BBCLK_OUT (55), CAT_ENABLE(54), CAT_TXNRX(53) */
3'b000, /* DB_EXP_1_8_V_{33,34,32} */
2'b00, /* CAT_CTRL_IN[1:0] (49,48) */
1'b0, /* CAT_MISO (47) */
4'b0000, /* CAT_{MOSI,SCLK,CS,RESETn) (46,45, 44, 43) */
1'b0, /* DB_1_8V_31 (42) */
8'h00, /* CAT_CTRL_OUT (41:34) */
1'b0, /* DB_1_8V_11 (33) */
1'b0, /* CAT_CTRL_IN3 (32) */
1'b0, /* DB_1_8V_10 (31) */
1'b0, /* CAT_CTRL_IN2 (30) */
1'b0, /* DB_1_8V_9 (29) */
1'b0, /* VCRX2_V2 (28) */
1'b0, /* DB_1_8V_8 (25) */
1'b0, /* VCRX2_V1 (26) */
1'b0, /* DB_1_8V_7 (25) */
1'b0, /* VCRX1_V2 (24) */
1'b0, /* DB_1_8V_6 (23) */
1'b0, /* VCRX1_V1 (22) */
1'b0, /* DB_1_8V_5 (21) */
1'b0, /* VCTXRX1_V2 (20) */
1'b0, /* DB_1_8V_4 (19) */
1'b0, /* VCTXRX1_V1 (18) */
1'b0, /* DB_1_8V_3 (17) */
1'b0, /* VCTXRX2_V1 (16) */
1'b1, /* DB_1_8V_2 (15) */
15'd0};
localparam DB_E31X_IDLE_DDR = {
1'b0, /* DB_EXP_18_24 (99) */
13'b0101010101010, /* leds & rx bandsels */
1'b0, /* CAT_FB_CLK (85) */
1'b0, /* CAT_TX_FRAME (84) */
1'b0, /* CAT_RX_DATA_CLK (83) */
25'b0000_0000_0000_0000_0000_0000_0, /* CAT_RX_FRAME(81), CAT_P0 & CAT_P1 (58) */
1'b0, /* CAT_SYNC(57) */
4'b0001, /* CAT_ENAGC(56), CAT_BBCLK_OUT (55), CAT_ENABLE(54), CAT_TXNRX(53) */
3'b000, /* DB_EXP_1_8_V_{32,33,34,} (52, 51, 50) */
2'b00, /* CAT_CTRL_IN[1:0] (49,48) */
1'b0, /* CAT_MISO (47) */
4'b0111, /* CAT_{MOSI,SCLK,CS,RESETn) (46, 45, 44, 43) */
1'b0, /* DB_1_8V_31 (42) */
8'h00, /* CAT_CTRL_OUT (41:34) */
1'b0, /* DB_1_8V_11 (33) */
1'b0, /* CAT_CTRL_IN3 (32) */
1'b0, /* DB_1_8V_10 (31) */
1'b0, /* CAT_CTRL_IN2 (30) */
1'b0, /* DB_1_8V_9 (29) */
1'b0, /* VCRX2_V2 (28) */
1'b0, /* DB_1_8V_8 (25) */
1'b0, /* VCRX2_V1 (26) */
1'b0, /* DB_1_8V_7 (24) */
1'b0, /* VCRX1_V2 (24) */
1'b0, /* DB_1_8V_6 (23) */
1'b0, /* VCRX1_V1 (22) */
1'b0, /* DB_1_8V_5 (21) */
1'b0, /* VCTXRX1_V1 (20) */
1'b0, /* DB_1_8V_4 (19) */
1'b0, /* VCTXRX1_V2 (18) */
1'b1, /* DB_1_8V_3 (17) */
1'b0, /* VCTXRX2_V1 (16) */
1'b1, /* DB_1_8V_2 (15) */
15'd0};
localparam NUM_DB_IO_PINS = 100;
wire [NUM_DB_IO_PINS-1:0] db_ddr = DB_E31X_IDLE_DDR;
wire [NUM_DB_IO_PINS-1:0] db_out = DB_E31X_IDLE_OUT;
wire [NUM_DB_IO_PINS-1:0] db_in;
genvar k;
generate
for (k = 0; k < NUM_DB_IO_PINS; k = k+1) begin
IOBUF db_io_i(.O(db_in[k]), .IO(DB_IO[k]), .I(db_out[k]), .T(~db_ddr[k]));
end
endgenerate
endmodule // e31x
top/e31x/e31x_idle_pins.xdc
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###############################################################################
# Pin mapping
###############################################################################
## RF board connector pins
# Pin 1
set_property PACKAGE_PIN H19 [get_ports {DB_IO[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[0]}]
# Pin 2
# 3.3v DB
# Pin 3
set_property PACKAGE_PIN F19 [get_ports {DB_IO[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[1]}]
#Pin 4
# 3.3v DB
#Pin 5
set_property PACKAGE_PIN G19 [get_ports {DB_IO[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[2]}]
#Pin 6
set_property PACKAGE_PIN E19 [get_ports {DB_IO[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[3]}]
#Pin 7
set_property PACKAGE_PIN E20 [get_ports {DB_IO[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[4]}]
#Pin 8
set_property PACKAGE_PIN G21 [get_ports {DB_IO[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[5]}]
#Pin 9
set_property PACKAGE_PIN G22 [get_ports {DB_IO[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[6]}]
#Pin 10
set_property PACKAGE_PIN G20 [get_ports {DB_IO[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[7]}]
#Pin 11
set_property PACKAGE_PIN H22 [get_ports {DB_IO[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[8]}]
#Pin 12
set_property PACKAGE_PIN F22 [get_ports {DB_IO[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[9]}]
#Pin 13
set_property PACKAGE_PIN A17 [get_ports {DB_IO[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[10]}]
#Pin 14
set_property PACKAGE_PIN F21 [get_ports {DB_IO[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[11]}]
#Pin 15
set_property PACKAGE_PIN B16 [get_ports {DB_IO[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[12]}]
#Pin 16 -- Not used
#set_property PACKAGE_PIN J21 [get_ports {}]
#set_property IOSTANDARD LVCMOS18 [get_ports {}]
#Pin 17
set_property PACKAGE_PIN A19 [get_ports {DB_IO[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[13]}]
#Pin 18 -- Not used
#set_property PACKAGE_PIN J22 [get_ports {}]
#set_property IOSTANDARD LVCMOS18 [get_ports {}]
#Pin 19
set_property PACKAGE_PIN B15 [get_ports {DB_IO[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[14]}]
#Pin 20
set_property PACKAGE_PIN K21 [get_ports {DB_IO[15]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[15]}]
#Pin 21
set_property PACKAGE_PIN A16 [get_ports {DB_IO[16]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[16]}]
#Pin 22
set_property PACKAGE_PIN L22 [get_ports {DB_IO[17]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[17]}]
#Pin 23
set_property PACKAGE_PIN B17 [get_ports {DB_IO[18]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[18]}]
#Pin 24
set_property PACKAGE_PIN L21 [get_ports {DB_IO[19]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[19]}]
#Pin 25
set_property PACKAGE_PIN C15 [get_ports {DB_IO[20]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[20]}]
#Pin 26
set_property PACKAGE_PIN R18 [get_ports {DB_IO[21]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[21]}]
#Pin 27
set_property PACKAGE_PIN E18 [get_ports {DB_IO[22]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[22]}]
#Pin 28
set_property PACKAGE_PIN T18 [get_ports {DB_IO[23]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[23]}]
#Pin 29
set_property PACKAGE_PIN F18 [get_ports {DB_IO[24]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[24]}]
#Pin 30
set_property PACKAGE_PIN M20 [get_ports {DB_IO[25]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[25]}]
#Pin 31
set_property PACKAGE_PIN F17 [get_ports {DB_IO[26]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[26]}]
#Pin 32
set_property PACKAGE_PIN M15 [get_ports {DB_IO[27]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[27]}]
#Pin 33
set_property PACKAGE_PIN G17 [get_ports {DB_IO[28]}]
set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[28]}]
#Pin 34
set_property PACKAGE_PIN J18 [get_ports {DB_IO[29]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[29]}]
#Pin 35
set_property PACKAGE_PIN U5 [get_ports {DB_IO[30]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[30]}]
#Pin 36
set_property PACKAGE_PIN J20 [get_ports {DB_IO[31]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[31]}]
#Pin 37
set_property PACKAGE_PIN U6 [get_ports {DB_IO[32]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[32]}]
#Pin 38
set_property PACKAGE_PIN K19 [get_ports {DB_IO[33]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[33]}]
#Pin 39
set_property PACKAGE_PIN AB5 [get_ports {DB_IO[34]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[34]}]
#Pin 40
set_property PACKAGE_PIN K20 [get_ports {DB_IO[35]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[35]}]
#Pin 41
set_property PACKAGE_PIN AB6 [get_ports {DB_IO[36]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[36]}]
#Pin 42
set_property PACKAGE_PIN L19 [get_ports {DB_IO[37]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[37]}]
#Pin 43
set_property PACKAGE_PIN AB7 [get_ports {DB_IO[38]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[38]}]
#Pin 44
set_property PACKAGE_PIN V12 [get_ports {DB_IO[39]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[39]}]
#Pin 45
set_property PACKAGE_PIN AA4 [get_ports {DB_IO[40]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[40]}]
#Pin 46
set_property PACKAGE_PIN W12 [get_ports {DB_IO[41]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[41]}]
#Pin 47
set_property PACKAGE_PIN T6 [get_ports {DB_IO[42]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[42]}]
#Pin 48
set_property PACKAGE_PIN U11 [get_ports {DB_IO[43]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[43]}]
#Pin 49
# 1.8V
#Pin 50
set_property PACKAGE_PIN W6 [get_ports {DB_IO[44]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[44]}]
#Pin 51
# 1.8V
#Pin 52
set_property PACKAGE_PIN W5 [get_ports {DB_IO[45]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[45]}]
#Pin 53
# 5V
#Pin 54
set_property PACKAGE_PIN V7 [get_ports {DB_IO[46]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[46]}]
#Pin 55
# 5V
#Pin 56
set_property PACKAGE_PIN W7 [get_ports {DB_IO[47]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[47]}]
#Pin 57
# 5V
#Pin 58
set_property PACKAGE_PIN V4 [get_ports {DB_IO[48]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[48]}]
#Pin 59
# 5V
#Pin 60
set_property PACKAGE_PIN V5 [get_ports {DB_IO[49]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[49]}]
#Pin 61
# 1.8V
#Pin 62
set_property PACKAGE_PIN U4 [get_ports {DB_IO[50]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[50]}]
#Pin 63
# 1.8V
#Pin 64
set_property PACKAGE_PIN T4 [get_ports {DB_IO[51]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[51]}]
#Pin 65
# GND
#Pin 66
set_property PACKAGE_PIN R6 [get_ports {DB_IO[52]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[52]}]
#Pin 67
set_property PACKAGE_PIN AB1 [get_ports {DB_IO[53]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[53]}]
#Pin 68
# GND
#Pin 69
set_property PACKAGE_PIN AB4 [get_ports {DB_IO[54]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[54]}]
#Pin 70
set_property PACKAGE_PIN M19 [get_ports {DB_IO[55]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[55]}]
#Pin 71
set_property PACKAGE_PIN AB2 [get_ports {DB_IO[56]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[56]}]
#Pin 72
# GND
#Pin 73
# GND
#Pin 74
set_property PACKAGE_PIN T16 [get_ports {DB_IO[57]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[57]}]
#Pin 75
set_property PACKAGE_PIN J15 [get_ports {DB_IO[58]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[58]}]
#Pin 76
# GND
#Pin 77
set_property PACKAGE_PIN J16 [get_ports {DB_IO[59]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[59]}]
#Pin 78
set_property PACKAGE_PIN N15 [get_ports {DB_IO[60]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[60]}]
#Pin 79
set_property PACKAGE_PIN J17 [get_ports {DB_IO[61]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[61]}]
#Pin 80
set_property PACKAGE_PIN M21 [get_ports {DB_IO[62]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[62]}]
#Pin 81
set_property PACKAGE_PIN K15 [get_ports {DB_IO[63]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[63]}]
#Pin 82
set_property PACKAGE_PIN P15 [get_ports {DB_IO[64]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[64]}]
#Pin 83
set_property PACKAGE_PIN K18 [get_ports {DB_IO[65]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[65]}]
#Pin 84
set_property PACKAGE_PIN N19 [get_ports {DB_IO[66]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[66]}]
#Pin 85
set_property PACKAGE_PIN K16 [get_ports {DB_IO[67]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[67]}]
#Pin 86
set_property PACKAGE_PIN P18 [get_ports {DB_IO[68]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[68]}]
#Pin 87
set_property PACKAGE_PIN L16 [get_ports {DB_IO[69]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[69]}]
#Pin 88
set_property PACKAGE_PIN P20 [get_ports {DB_IO[70]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[70]}]
#Pin 89
set_property PACKAGE_PIN L17 [get_ports {DB_IO[71]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[71]}]
#Pin 90
set_property PACKAGE_PIN P17 [get_ports {DB_IO[72]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[72]}]
#Pin 91
set_property PACKAGE_PIN M16 [get_ports {DB_IO[73]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[73]}]
#Pin 92
set_property PACKAGE_PIN P21 [get_ports {DB_IO[74]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[74]}]
#Pin 93
set_property PACKAGE_PIN M17 [get_ports {DB_IO[75]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[75]}]
#Pin 94
set_property PACKAGE_PIN R20 [get_ports {DB_IO[76]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[76]}]
#Pin 95
set_property PACKAGE_PIN N17 [get_ports {DB_IO[77]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[77]}]
#Pin 96
set_property PACKAGE_PIN T17 [get_ports {DB_IO[78]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[78]}]
#Pin 97
set_property PACKAGE_PIN N20 [get_ports {DB_IO[79]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[79]}]
#Pin 98
set_property PACKAGE_PIN M22 [get_ports {DB_IO[80]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[80]}]
#Pin 99
set_property PACKAGE_PIN N18 [get_ports {DB_IO[81]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[81]}]
#Pin 100
set_property PACKAGE_PIN N22 [get_ports {DB_IO[82]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[82]}]
#Pin 101
set_property PACKAGE_PIN L18 [get_ports {DB_IO[83]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[83]}]
#Pin 102
set_property PACKAGE_PIN P22 [get_ports {DB_IO[84]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[84]}]
#Pin 103
# GND
#Pin 104
set_property PACKAGE_PIN R21 [get_ports {DB_IO[85]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[85]}]
#Pin 105
# 1.8V
#Pin 106
# GND
#Pin 107
set_property PACKAGE_PIN AA8 [get_ports {DB_IO[86]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[86]}]
#Pin 108
set_property PACKAGE_PIN Y11 [get_ports {DB_IO[87]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[87]}]
#Pin 109
set_property PACKAGE_PIN AA9 [get_ports {DB_IO[88]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[88]}]
#Pin 110
set_property PACKAGE_PIN AB10 [get_ports {DB_IO[89]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[89]}]
#Pin 111
set_property PACKAGE_PIN AB9 [get_ports {DB_IO[90]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[90]}]
#Pin 112
set_property PACKAGE_PIN AA12 [get_ports {DB_IO[91]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[91]}]
#Pin 113
set_property PACKAGE_PIN U10 [get_ports {DB_IO[92]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[92]}]
#Pin 114
set_property PACKAGE_PIN U12 [get_ports {DB_IO[93]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[93]}]
#Pin 115
set_property PACKAGE_PIN Y10 [get_ports {DB_IO[94]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[94]}]
#Pin 116
set_property PACKAGE_PIN AB11 [get_ports {DB_IO[95]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[95]}]
#Pin 117
set_property PACKAGE_PIN U9 [get_ports {DB_IO[96]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[96]}]
#Pin 118
set_property PACKAGE_PIN AA11 [get_ports {DB_IO[97]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[97]}]
#Pin 119
set_property PACKAGE_PIN Y4 [get_ports {DB_IO[98]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[98]}]
#Pin 120
set_property PACKAGE_PIN AB12 [get_ports {DB_IO[99]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[99]}]
### Other I/O
set_property PACKAGE_PIN A22 [get_ports AVR_CS_R]
set_property IOSTANDARD LVCMOS33 [get_ports AVR_CS_R]
set_property PACKAGE_PIN B22 [get_ports AVR_IRQ]
set_property IOSTANDARD LVCMOS33 [get_ports AVR_IRQ]
set_property PACKAGE_PIN C22 [get_ports AVR_MISO_R]
set_property IOSTANDARD LVCMOS33 [get_ports AVR_MISO_R]
set_property PACKAGE_PIN A21 [get_ports AVR_MOSI_R]
set_property IOSTANDARD LVCMOS33 [get_ports AVR_MOSI_R]
set_property PACKAGE_PIN D22 [get_ports AVR_SCK_R]
set_property IOSTANDARD LVCMOS33 [get_ports AVR_SCK_R]
set_property PACKAGE_PIN E21 [get_ports ONSWITCH_DB]
set_property IOSTANDARD LVCMOS33 [get_ports ONSWITCH_DB]
set_property PACKAGE_PIN Y9 [get_ports GPS_PPS]
set_property IOSTANDARD LVCMOS18 [get_ports GPS_PPS]
set_property PACKAGE_PIN D18 [get_ports PPS_EXT_IN]
set_property IOSTANDARD LVCMOS33 [get_ports PPS_EXT_IN]
set_property PACKAGE_PIN E16 [get_ports {PL_GPIO[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[0]}]
set_property PACKAGE_PIN C18 [get_ports {PL_GPIO[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[1]}]
set_property PACKAGE_PIN D17 [get_ports {PL_GPIO[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[2]}]
set_property PACKAGE_PIN D16 [get_ports {PL_GPIO[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[3]}]
set_property PACKAGE_PIN D15 [get_ports {PL_GPIO[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[4]}]
set_property PACKAGE_PIN E15 [get_ports {PL_GPIO[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[5]}]
set_property PULLDOWN true [get_ports {PL_GPIO[0]}]
set_property PULLDOWN true [get_ports {PL_GPIO[1]}]
set_property PULLDOWN true [get_ports {PL_GPIO[2]}]
set_property PULLDOWN true [get_ports {PL_GPIO[3]}]
set_property PULLDOWN true [get_ports {PL_GPIO[4]}]
set_property PULLDOWN true [get_ports {PL_GPIO[5]}]
top/e31x/e31x_pins.xdc
+507
View File
@@ -0,0 +1,507 @@
###############################################################################
# Pin mapping
###############################################################################
## RF board connector pins
# Pin 1
set_property PACKAGE_PIN H19 [get_ports {TX_BANDSEL[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {TX_BANDSEL[2]}]
# Pin 2
# 3.3v DB
# Pin 3
set_property PACKAGE_PIN F19 [get_ports {RX1B_BANDSEL[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RX1B_BANDSEL[0]}]
#Pin 4
# 3.3v DB
#Pin 5
set_property PACKAGE_PIN G19 [get_ports {RX1B_BANDSEL[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RX1B_BANDSEL[1]}]
#Pin 6
set_property PACKAGE_PIN E19 [get_ports {RX1_BANDSEL[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RX1_BANDSEL[0]}]
#Pin 7
set_property PACKAGE_PIN E20 [get_ports VCTXRX2_V2]
set_property IOSTANDARD LVCMOS33 [get_ports VCTXRX2_V2]
#Pin 8
set_property PACKAGE_PIN G21 [get_ports {RX1_BANDSEL[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RX1_BANDSEL[1]}]
#Pin 9
set_property PACKAGE_PIN G22 [get_ports TX_ENABLE1A]
set_property IOSTANDARD LVCMOS33 [get_ports TX_ENABLE1A]
#Pin 10
set_property PACKAGE_PIN G20 [get_ports {RX1_BANDSEL[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RX1_BANDSEL[2]}]
#Pin 11
set_property PACKAGE_PIN H22 [get_ports TX_ENABLE2A]
set_property IOSTANDARD LVCMOS33 [get_ports TX_ENABLE2A]
#Pin 12
set_property PACKAGE_PIN F22 [get_ports {TX_BANDSEL[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {TX_BANDSEL[0]}]
#Pin 13
set_property PACKAGE_PIN A17 [get_ports TX_ENABLE1B]
set_property IOSTANDARD LVCMOS33 [get_ports TX_ENABLE1B]
#Pin 14
set_property PACKAGE_PIN F21 [get_ports {TX_BANDSEL[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {TX_BANDSEL[1]}]
#Pin 15
set_property PACKAGE_PIN B16 [get_ports TX_ENABLE2B]
set_property IOSTANDARD LVCMOS33 [get_ports TX_ENABLE2B]
#Pin 16 -- Not used
#set_property PACKAGE_PIN J21 [get_ports DB_SCL]
#set_property IOSTANDARD LVCMOS18 [get_ports DB_SCL]
#Pin 17
set_property PACKAGE_PIN A19 [get_ports {RX1C_BANDSEL[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RX1C_BANDSEL[0]}]
#Pin 18 -- Not used
#set_property PACKAGE_PIN J22 [get_ports DB_SDA]
#set_property IOSTANDARD LVCMOS18 [get_ports DB_SDA]
#Pin 19
set_property PACKAGE_PIN B15 [get_ports {RX1C_BANDSEL[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RX1C_BANDSEL[1]}]
#Pin 20
set_property PACKAGE_PIN K21 [get_ports TCXO_DAC_SYNC_N]
set_property IOSTANDARD LVCMOS18 [get_ports TCXO_DAC_SYNC_N]
#Pin 21
set_property PACKAGE_PIN A16 [get_ports VCTXRX2_V1]
set_property IOSTANDARD LVCMOS33 [get_ports VCTXRX2_V1]
#Pin 22
set_property PACKAGE_PIN L22 [get_ports TCXO_DAC_SCLK]
set_property IOSTANDARD LVCMOS18 [get_ports TCXO_DAC_SCLK]
#Pin 23
set_property PACKAGE_PIN B17 [get_ports VCTXRX1_V2]
set_property IOSTANDARD LVCMOS33 [get_ports VCTXRX1_V2]
#Pin 24
set_property PACKAGE_PIN L21 [get_ports TCXO_DAC_SDIN]
set_property IOSTANDARD LVCMOS18 [get_ports TCXO_DAC_SDIN]
#Pin 25
set_property PACKAGE_PIN C15 [get_ports VCTXRX1_V1]
set_property IOSTANDARD LVCMOS33 [get_ports VCTXRX1_V1]
#Pin 26
set_property PACKAGE_PIN R18 [get_ports {DB_EXP_1_8V[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[5]}]
#Pin 27
set_property PACKAGE_PIN E18 [get_ports VCRX1_V1]
set_property IOSTANDARD LVCMOS33 [get_ports VCRX1_V1]
#Pin 28
set_property PACKAGE_PIN T18 [get_ports {DB_EXP_1_8V[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[6]}]
#Pin 29
set_property PACKAGE_PIN F18 [get_ports VCRX1_V2]
set_property IOSTANDARD LVCMOS33 [get_ports VCRX1_V2]
#Pin 30
set_property PACKAGE_PIN M20 [get_ports TCXO_CLK]
set_property IOSTANDARD LVCMOS18 [get_ports TCXO_CLK]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets TCXO_CLK]
#Pin 31
set_property PACKAGE_PIN F17 [get_ports VCRX2_V1]
set_property IOSTANDARD LVCMOS33 [get_ports VCRX2_V1]
#Pin 32
set_property PACKAGE_PIN M15 [get_ports {DB_EXP_1_8V[8]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[8]}]
#Pin 33
set_property PACKAGE_PIN G17 [get_ports VCRX2_V2]
set_property IOSTANDARD LVCMOS33 [get_ports VCRX2_V2]
#Pin 34
set_property PACKAGE_PIN J18 [get_ports {DB_EXP_1_8V[9]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[9]}]
#Pin 35
set_property PACKAGE_PIN U5 [get_ports {CAT_CTRL_IN[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_IN[2]}]
#Pin 36
set_property PACKAGE_PIN J20 [get_ports {DB_EXP_1_8V[10]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[10]}]
#Pin 37
set_property PACKAGE_PIN U6 [get_ports {CAT_CTRL_IN[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_IN[3]}]
#Pin 38
set_property PACKAGE_PIN K19 [get_ports {DB_EXP_1_8V[11]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[11]}]
#Pin 39
set_property PACKAGE_PIN AB5 [get_ports {CAT_CTRL_OUT[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[0]}]
#Pin 40
set_property PACKAGE_PIN K20 [get_ports {CAT_CTRL_OUT[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[4]}]
#Pin 41
set_property PACKAGE_PIN AB6 [get_ports {CAT_CTRL_OUT[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[1]}]
#Pin 42
set_property PACKAGE_PIN L19 [get_ports {CAT_CTRL_OUT[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[5]}]
#Pin 43
set_property PACKAGE_PIN AB7 [get_ports {CAT_CTRL_OUT[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[2]}]
#Pin 44
set_property PACKAGE_PIN V12 [get_ports {CAT_CTRL_OUT[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[6]}]
#Pin 45
set_property PACKAGE_PIN AA4 [get_ports {CAT_CTRL_OUT[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[3]}]
#Pin 46
set_property PACKAGE_PIN W12 [get_ports {CAT_CTRL_OUT[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[7]}]
#Pin 47
set_property PACKAGE_PIN T6 [get_ports {DB_EXP_1_8V[31]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[31]}]
#Pin 48
set_property PACKAGE_PIN U11 [get_ports CAT_RESET]
set_property IOSTANDARD LVCMOS18 [get_ports CAT_RESET]
#Pin 49
# 1.8V
#Pin 50
set_property PACKAGE_PIN W6 [get_ports CAT_CS]
set_property IOSTANDARD LVCMOS18 [get_ports CAT_CS]
#Pin 51
# 1.8V
#Pin 52
set_property PACKAGE_PIN W5 [get_ports CAT_SCLK]
set_property IOSTANDARD LVCMOS18 [get_ports CAT_SCLK]
#Pin 53
# 5V
#Pin 54
set_property PACKAGE_PIN V7 [get_ports CAT_MOSI]
set_property IOSTANDARD LVCMOS18 [get_ports CAT_MOSI]
#Pin 55
# 5V
#Pin 56
set_property PACKAGE_PIN W7 [get_ports CAT_MISO]
set_property IOSTANDARD LVCMOS18 [get_ports CAT_MISO]
#Pin 57
# 5V
#Pin 58
set_property PACKAGE_PIN V4 [get_ports {CAT_CTRL_IN[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_IN[0]}]
#Pin 59
# 5V
#Pin 60
set_property PACKAGE_PIN V5 [get_ports {CAT_CTRL_IN[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_IN[1]}]
#Pin 61
# 1.8V
#Pin 62
set_property PACKAGE_PIN U4 [get_ports {DB_EXP_1_8V[33]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[33]}]
#Pin 63
# 1.8V
#Pin 64
set_property PACKAGE_PIN T4 [get_ports {DB_EXP_1_8V[34]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[34]}]
#Pin 65
# GND
#Pin 66
set_property PACKAGE_PIN R6 [get_ports {DB_EXP_1_8V[32]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[32]}]
#Pin 67
set_property PACKAGE_PIN AB1 [get_ports CAT_TXNRX]
set_property IOSTANDARD LVCMOS18 [get_ports CAT_TXNRX]
#Pin 68
# GND
#Pin 69
set_property PACKAGE_PIN AB4 [get_ports CAT_ENABLE]
set_property IOSTANDARD LVCMOS18 [get_ports CAT_ENABLE]
#Pin 70
set_property PACKAGE_PIN M19 [get_ports CAT_BBCLK_OUT]
set_property IOSTANDARD LVCMOS18 [get_ports CAT_BBCLK_OUT]
#Pin 71
set_property PACKAGE_PIN AB2 [get_ports CAT_ENAGC]
set_property IOSTANDARD LVCMOS18 [get_ports CAT_ENAGC]
#Pin 72
# GND
#Pin 73
# GND
#Pin 74
set_property PACKAGE_PIN T16 [get_ports CAT_SYNC]
set_property IOSTANDARD LVCMOS18 [get_ports CAT_SYNC]
#Pin 78
set_property PACKAGE_PIN N15 [get_ports {CAT_P1_D[11]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[11]}]
#Pin 76
# GND
#Pin 100
set_property PACKAGE_PIN N22 [get_ports {CAT_P1_D[10]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[10]}]
#Pin 93
set_property PACKAGE_PIN M17 [get_ports {CAT_P0_D[11]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[11]}]
#Pin 96
set_property PACKAGE_PIN T17 [get_ports {CAT_P1_D[9]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[9]}]
#Pin 95
set_property PACKAGE_PIN N17 [get_ports {CAT_P0_D[10]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[10]}]
#Pin 98
set_property PACKAGE_PIN M22 [get_ports {CAT_P1_D[8]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[8]}]
#Pin 81
set_property PACKAGE_PIN K15 [get_ports {CAT_P0_D[9]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[9]}]
#Pin 92
set_property PACKAGE_PIN P21 [get_ports {CAT_P1_D[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[7]}]
#Pin 97
set_property PACKAGE_PIN N20 [get_ports {CAT_P0_D[8]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[8]}]
#Pin 94
set_property PACKAGE_PIN R20 [get_ports {CAT_P1_D[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[6]}]
#Pin 77
set_property PACKAGE_PIN J16 [get_ports {CAT_P0_D[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[7]}]
#Pin 86
set_property PACKAGE_PIN P18 [get_ports {CAT_P1_D[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[5]}]
#Pin 85
set_property PACKAGE_PIN K16 [get_ports {CAT_P0_D[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[6]}]
#Pin 90
set_property PACKAGE_PIN P17 [get_ports {CAT_P1_D[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[4]}]
#Pin 75
set_property PACKAGE_PIN J15 [get_ports {CAT_P0_D[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[5]}]
#Pin 82
set_property PACKAGE_PIN P15 [get_ports {CAT_P1_D[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[3]}]
#Pin 91
set_property PACKAGE_PIN M16 [get_ports {CAT_P0_D[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[4]}]
#Pin 88
set_property PACKAGE_PIN P20 [get_ports {CAT_P1_D[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[2]}]
#Pin 79
set_property PACKAGE_PIN J17 [get_ports {CAT_P0_D[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[3]}]
#Pin 80
set_property PACKAGE_PIN M21 [get_ports {CAT_P1_D[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[1]}]
#Pin 89
set_property PACKAGE_PIN L17 [get_ports {CAT_P0_D[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[2]}]
#Pin 84
set_property PACKAGE_PIN N19 [get_ports {CAT_P1_D[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[0]}]
#Pin 83
set_property PACKAGE_PIN K18 [get_ports {CAT_P0_D[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[1]}]
#Pin 102
set_property PACKAGE_PIN P22 [get_ports CAT_TX_FRAME]
set_property IOSTANDARD LVCMOS18 [get_ports CAT_TX_FRAME]
#Pin 87
set_property PACKAGE_PIN L16 [get_ports {CAT_P0_D[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[0]}]
#Pin 104
set_property PACKAGE_PIN R21 [get_ports CAT_FB_CLK]
set_property IOSTANDARD LVCMOS18 [get_ports CAT_FB_CLK]
#Pin 99
set_property PACKAGE_PIN N18 [get_ports CAT_RX_FRAME]
set_property IOSTANDARD LVCMOS18 [get_ports CAT_RX_FRAME]
#Pin 103
# GND
#Pin 101
set_property PACKAGE_PIN L18 [get_ports CAT_DATA_CLK]
set_property IOSTANDARD LVCMOS18 [get_ports CAT_DATA_CLK]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CAT_DATA_CLK]
#Pin 105
# 1.8V
#Pin 106
# GND
#Pin 107
set_property PACKAGE_PIN AA8 [get_ports {RX2_BANDSEL[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {RX2_BANDSEL[2]}]
#Pin 108
set_property PACKAGE_PIN Y11 [get_ports LED_TXRX1_TX]
set_property IOSTANDARD LVCMOS18 [get_ports LED_TXRX1_TX]
#Pin 109
set_property PACKAGE_PIN AA9 [get_ports {RX2_BANDSEL[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {RX2_BANDSEL[1]}]
#Pin 110
set_property PACKAGE_PIN AB10 [get_ports LED_TXRX1_RX]
set_property IOSTANDARD LVCMOS18 [get_ports LED_TXRX1_RX]
#Pin 111
set_property PACKAGE_PIN AB9 [get_ports {RX2_BANDSEL[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {RX2_BANDSEL[0]}]
#Pin 112
set_property PACKAGE_PIN AA12 [get_ports LED_RX1_RX]
set_property IOSTANDARD LVCMOS18 [get_ports LED_RX1_RX]
#Pin 113
set_property PACKAGE_PIN U10 [get_ports {RX2C_BANDSEL[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {RX2C_BANDSEL[1]}]
#Pin 114
set_property PACKAGE_PIN U12 [get_ports LED_TXRX2_TX]
set_property IOSTANDARD LVCMOS18 [get_ports LED_TXRX2_TX]
#Pin 115
set_property PACKAGE_PIN Y10 [get_ports {RX2C_BANDSEL[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {RX2C_BANDSEL[0]}]
#Pin 116
set_property PACKAGE_PIN AB11 [get_ports LED_TXRX2_RX]
set_property IOSTANDARD LVCMOS18 [get_ports LED_TXRX2_RX]
#Pin 117
set_property PACKAGE_PIN U9 [get_ports {RX2B_BANDSEL[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {RX2B_BANDSEL[1]}]
#Pin 118
set_property PACKAGE_PIN AA11 [get_ports LED_RX2_RX]
set_property IOSTANDARD LVCMOS18 [get_ports LED_RX2_RX]
#Pin 119
set_property PACKAGE_PIN Y4 [get_ports {RX2B_BANDSEL[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {RX2B_BANDSEL[0]}]
#Pin 120
set_property PACKAGE_PIN AB12 [get_ports {DB_EXP_1_8V[24]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[24]}]
### Other I/O
set_property PACKAGE_PIN A22 [get_ports AVR_CS_R]
set_property IOSTANDARD LVCMOS33 [get_ports AVR_CS_R]
set_property PACKAGE_PIN B22 [get_ports AVR_IRQ]
set_property IOSTANDARD LVCMOS33 [get_ports AVR_IRQ]
set_property PACKAGE_PIN C22 [get_ports AVR_MISO_R]
set_property IOSTANDARD LVCMOS33 [get_ports AVR_MISO_R]
set_property PACKAGE_PIN A21 [get_ports AVR_MOSI_R]
set_property IOSTANDARD LVCMOS33 [get_ports AVR_MOSI_R]
set_property PACKAGE_PIN D22 [get_ports AVR_SCK_R]
set_property IOSTANDARD LVCMOS33 [get_ports AVR_SCK_R]
set_property PACKAGE_PIN E21 [get_ports ONSWITCH_DB]
set_property IOSTANDARD LVCMOS33 [get_ports ONSWITCH_DB]
set_property PACKAGE_PIN Y9 [get_ports GPS_PPS]
set_property IOSTANDARD LVCMOS18 [get_ports GPS_PPS]
set_property PACKAGE_PIN D18 [get_ports PPS_EXT_IN]
set_property IOSTANDARD LVCMOS33 [get_ports PPS_EXT_IN]
set_property PACKAGE_PIN E16 [get_ports {PL_GPIO[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[0]}]
set_property PACKAGE_PIN C18 [get_ports {PL_GPIO[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[1]}]
set_property PACKAGE_PIN D17 [get_ports {PL_GPIO[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[2]}]
set_property PACKAGE_PIN D16 [get_ports {PL_GPIO[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[3]}]
set_property PACKAGE_PIN D15 [get_ports {PL_GPIO[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[4]}]
set_property PACKAGE_PIN E15 [get_ports {PL_GPIO[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[5]}]
set_property PULLDOWN true [get_ports {PL_GPIO[0]}]
set_property PULLDOWN true [get_ports {PL_GPIO[1]}]
set_property PULLDOWN true [get_ports {PL_GPIO[2]}]
set_property PULLDOWN true [get_ports {PL_GPIO[3]}]
set_property PULLDOWN true [get_ports {PL_GPIO[4]}]
set_property PULLDOWN true [get_ports {PL_GPIO[5]}]
top/e31x/e31x_rfnoc_image_core.v
+461
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//
// Copyright 2019 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfnoc_image_core (for e31x)
// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder)
// Re-running that tool will overwrite this file!
// File generated on: 2019-11-08T15:58:15.219909
// Source: ./e31x/e31x_rfnoc_image_core.yml
// Source SHA256: 48e2907163bf8462812f33b7cf995da37c44d9652ba3afa38c510910a2365c05
module rfnoc_image_core #(
parameter [15:0] PROTOVER = {8'd1, 8'd0}
)(
// Clocks
input wire chdr_aclk,
input wire ctrl_aclk,
input wire core_arst,
input wire radio_clk,
// Basic
input wire [15:0] device_id,
//// IO ports //////////////////////////////////
// ctrlport_radio
output wire [ 1-1:0] m_ctrlport_req_wr,
output wire [ 1-1:0] m_ctrlport_req_rd,
output wire [ 20-1:0] m_ctrlport_req_addr,
output wire [ 32-1:0] m_ctrlport_req_data,
output wire [ 4-1:0] m_ctrlport_req_byte_en,
output wire [ 1-1:0] m_ctrlport_req_has_time,
output wire [ 64-1:0] m_ctrlport_req_time,
input wire [ 1-1:0] m_ctrlport_resp_ack,
input wire [ 2-1:0] m_ctrlport_resp_status,
input wire [ 32-1:0] m_ctrlport_resp_data,
// time_keeper
input wire [ 64-1:0] radio_time,
// x300_radio
input wire [ 64-1:0] radio_rx_data,
input wire [ 2-1:0] radio_rx_stb,
output wire [ 2-1:0] radio_rx_running,
output wire [ 64-1:0] radio_tx_data,
input wire [ 2-1:0] radio_tx_stb,
output wire [ 2-1:0] radio_tx_running,
// Transport 0 (dma dma)
input wire [64-1:0] s_dma_tdata,
input wire s_dma_tlast,
input wire s_dma_tvalid,
output wire s_dma_tready,
output wire [64-1:0] m_dma_tdata,
output wire m_dma_tlast,
output wire m_dma_tvalid,
input wire m_dma_tready
);
localparam CHDR_W = 64;
localparam MTU = 10;
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
// ----------------------------------------------------
// CHDR Crossbar
// ----------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid;
wire xb_to_ep0_tready;
wire [CHDR_W-1:0] ep0_to_xb_tdata ;
wire ep0_to_xb_tlast ;
wire ep0_to_xb_tvalid;
wire ep0_to_xb_tready;
wire [CHDR_W-1:0] xb_to_ep1_tdata ;
wire xb_to_ep1_tlast ;
wire xb_to_ep1_tvalid;
wire xb_to_ep1_tready;
wire [CHDR_W-1:0] ep1_to_xb_tdata ;
wire ep1_to_xb_tlast ;
wire ep1_to_xb_tvalid;
wire ep1_to_xb_tready;
chdr_crossbar_nxn #(
.CHDR_W (CHDR_W),
.NPORTS (3),
.DEFAULT_PORT (0),
.MTU (MTU),
.ROUTE_TBL_SIZE (6),
.MUX_ALLOC ("ROUND-ROBIN"),
.OPTIMIZE ("AREA"),
.NPORTS_MGMT (1),
.EXT_RTCFG_PORT (0),
.PROTOVER (PROTOVER)
) chdr_xb_i (
.clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst),
.device_id (device_id),
.s_axis_tdata ({ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata}),
.s_axis_tlast ({ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast}),
.s_axis_tvalid ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid}),
.s_axis_tready ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready}),
.m_axis_tdata ({xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata}),
.m_axis_tlast ({xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast}),
.m_axis_tvalid ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid}),
.m_axis_tready ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready}),
.ext_rtcfg_stb (1'h0),
.ext_rtcfg_addr (16'h0),
.ext_rtcfg_data (32'h0),
.ext_rtcfg_ack ()
);
// ----------------------------------------------------
// Stream Endpoints
// ----------------------------------------------------
wire [CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast;
wire m_ep0_out0_tvalid;
wire m_ep0_out0_tready;
wire [CHDR_W-1:0] s_ep0_in0_tdata;
wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready;
wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ;
wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
chdr_stream_endpoint #(
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.AXIS_CTRL_EN (1),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
.NUM_DATA_O (1),
.INST_NUM (0),
.CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (14),
.MTU (MTU),
.REPORT_STRM_ERRS (1)
) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk ),
.rfnoc_chdr_rst (rfnoc_chdr_rst ),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
.device_id (device_id ),
.s_axis_chdr_tdata (xb_to_ep0_tdata ),
.s_axis_chdr_tlast (xb_to_ep0_tlast ),
.s_axis_chdr_tvalid (xb_to_ep0_tvalid ),
.s_axis_chdr_tready (xb_to_ep0_tready ),
.m_axis_chdr_tdata (ep0_to_xb_tdata ),
.m_axis_chdr_tlast (ep0_to_xb_tlast ),
.m_axis_chdr_tvalid (ep0_to_xb_tvalid ),
.m_axis_chdr_tready (ep0_to_xb_tready ),
.s_axis_data_tdata ({s_ep0_in0_tdata}),
.s_axis_data_tlast ({s_ep0_in0_tlast}),
.s_axis_data_tvalid ({s_ep0_in0_tvalid}),
.s_axis_data_tready ({s_ep0_in0_tready}),
.m_axis_data_tdata ({m_ep0_out0_tdata}),
.m_axis_data_tlast ({m_ep0_out0_tlast}),
.m_axis_data_tvalid ({m_ep0_out0_tvalid}),
.m_axis_data_tready ({m_ep0_out0_tready}),
.s_axis_ctrl_tdata (s_ep0_ctrl_tdata ),
.s_axis_ctrl_tlast (s_ep0_ctrl_tlast ),
.s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep0_ctrl_tready),
.m_axis_ctrl_tdata (m_ep0_ctrl_tdata ),
.m_axis_ctrl_tlast (m_ep0_ctrl_tlast ),
.m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep0_ctrl_tready),
.strm_seq_err_stb ( ),
.strm_data_err_stb ( ),
.strm_route_err_stb ( ),
.signal_data_err (1'b0 )
);
wire [CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid;
wire m_ep1_out0_tready;
wire [CHDR_W-1:0] s_ep1_in0_tdata;
wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready;
wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ;
wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
chdr_stream_endpoint #(
.PROTOVER (PROTOVER),
.CHDR_W (CHDR_W),
.AXIS_CTRL_EN (0),
.AXIS_DATA_EN (1),
.NUM_DATA_I (1),
.NUM_DATA_O (1),
.INST_NUM (1),
.CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (14),
.MTU (MTU),
.REPORT_STRM_ERRS (1)
) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk ),
.rfnoc_chdr_rst (rfnoc_chdr_rst ),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
.device_id (device_id ),
.s_axis_chdr_tdata (xb_to_ep1_tdata ),
.s_axis_chdr_tlast (xb_to_ep1_tlast ),
.s_axis_chdr_tvalid (xb_to_ep1_tvalid ),
.s_axis_chdr_tready (xb_to_ep1_tready ),
.m_axis_chdr_tdata (ep1_to_xb_tdata ),
.m_axis_chdr_tlast (ep1_to_xb_tlast ),
.m_axis_chdr_tvalid (ep1_to_xb_tvalid ),
.m_axis_chdr_tready (ep1_to_xb_tready ),
.s_axis_data_tdata ({s_ep1_in0_tdata}),
.s_axis_data_tlast ({s_ep1_in0_tlast}),
.s_axis_data_tvalid ({s_ep1_in0_tvalid}),
.s_axis_data_tready ({s_ep1_in0_tready}),
.m_axis_data_tdata ({m_ep1_out0_tdata}),
.m_axis_data_tlast ({m_ep1_out0_tlast}),
.m_axis_data_tvalid ({m_ep1_out0_tvalid}),
.m_axis_data_tready ({m_ep1_out0_tready}),
.s_axis_ctrl_tdata (s_ep1_ctrl_tdata ),
.s_axis_ctrl_tlast (s_ep1_ctrl_tlast ),
.s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep1_ctrl_tready),
.m_axis_ctrl_tdata (m_ep1_ctrl_tdata ),
.m_axis_ctrl_tlast (m_ep1_ctrl_tlast ),
.m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep1_ctrl_tready),
.strm_seq_err_stb ( ),
.strm_data_err_stb ( ),
.strm_route_err_stb ( ),
.signal_data_err (1'b0 )
);
// ----------------------------------------------------
// Control Crossbar
// ----------------------------------------------------
wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ;
wire m_core_ctrl_tlast , s_core_ctrl_tlast ;
wire m_core_ctrl_tvalid, s_core_ctrl_tvalid;
wire m_core_ctrl_tready, s_core_ctrl_tready;
wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ;
wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ;
wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid;
wire m_radio0_ctrl_tready, s_radio0_ctrl_tready;
axis_ctrl_crossbar_nxn #(
.WIDTH (32),
.NPORTS (3),
.TOPOLOGY ("TORUS"),
.INGRESS_BUFF_SIZE(5),
.ROUTER_BUFF_SIZE (5),
.ROUTING_ALLOC ("WORMHOLE"),
.SWITCH_ALLOC ("PRIO")
) ctrl_xb_i (
.clk (rfnoc_ctrl_clk),
.reset (rfnoc_ctrl_rst),
.s_axis_tdata ({m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
.s_axis_tvalid ({m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
.s_axis_tlast ({m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
.s_axis_tready ({m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
.m_axis_tdata ({s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
.m_axis_tvalid ({s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
.m_axis_tlast ({s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
.m_axis_tready ({s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
.deadlock_detected()
);
// ----------------------------------------------------
// RFNoC Core Kernel
// ----------------------------------------------------
wire [(512*1)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #(
.PROTOVER (PROTOVER),
.DEVICE_TYPE (16'hE310),
.DEVICE_FAMILY ("7SERIES"),
.SAFE_START_CLKS (0),
.NUM_BLOCKS (1),
.NUM_STREAM_ENDPOINTS(2),
.NUM_ENDPOINTS_CTRL (1),
.NUM_TRANSPORTS (1),
.NUM_EDGES (4),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
.ctrl_aclk (ctrl_aclk),
.ctrl_aclk_locked (1'b1),
.core_arst (core_arst),
.core_chdr_clk (rfnoc_chdr_clk),
.core_chdr_rst (rfnoc_chdr_rst),
.core_ctrl_clk (rfnoc_ctrl_clk),
.core_ctrl_rst (rfnoc_ctrl_rst),
.s_axis_ctrl_tdata (s_core_ctrl_tdata ),
.s_axis_ctrl_tlast (s_core_ctrl_tlast ),
.s_axis_ctrl_tvalid (s_core_ctrl_tvalid),
.s_axis_ctrl_tready (s_core_ctrl_tready),
.m_axis_ctrl_tdata (m_core_ctrl_tdata ),
.m_axis_ctrl_tlast (m_core_ctrl_tlast ),
.m_axis_ctrl_tvalid (m_core_ctrl_tvalid),
.m_axis_ctrl_tready (m_core_ctrl_tready),
.device_id (device_id),
.rfnoc_core_config (rfnoc_core_config),
.rfnoc_core_status (rfnoc_core_status)
);
// ----------------------------------------------------
// Blocks
// ----------------------------------------------------
// ----------------------------------------------------
// radio0
// ----------------------------------------------------
wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
wire s_radio0_in_1_tready, s_radio0_in_0_tready;
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrl_port
wire [ 1-1:0] radio0_m_ctrlport_req_wr;
wire [ 1-1:0] radio0_m_ctrlport_req_rd;
wire [ 20-1:0] radio0_m_ctrlport_req_addr;
wire [ 32-1:0] radio0_m_ctrlport_req_data;
wire [ 4-1:0] radio0_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio0_m_ctrlport_req_has_time;
wire [ 64-1:0] radio0_m_ctrlport_req_time;
wire [ 1-1:0] radio0_m_ctrlport_resp_ack;
wire [ 2-1:0] radio0_m_ctrlport_resp_status;
wire [ 32-1:0] radio0_m_ctrlport_resp_data;
// time_keeper
wire [ 64-1:0] radio0_radio_time;
// x300_radio
wire [ 64-1:0] radio0_radio_rx_data;
wire [ 2-1:0] radio0_radio_rx_stb;
wire [ 2-1:0] radio0_radio_rx_running;
wire [ 64-1:0] radio0_radio_tx_data;
wire [ 2-1:0] radio0_radio_tx_stb;
wire [ 2-1:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID(2),
.CHDR_W(CHDR_W),
.NUM_PORTS(2),
.MTU(MTU)
) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.radio_clk(radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.m_ctrlport_req_wr(radio0_m_ctrlport_req_wr),
.m_ctrlport_req_rd(radio0_m_ctrlport_req_rd),
.m_ctrlport_req_addr(radio0_m_ctrlport_req_addr),
.m_ctrlport_req_data(radio0_m_ctrlport_req_data),
.m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en),
.m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time),
.m_ctrlport_req_time(radio0_m_ctrlport_req_time),
.m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack),
.m_ctrlport_resp_status(radio0_m_ctrlport_resp_status),
.m_ctrlport_resp_data(radio0_m_ctrlport_resp_data),
.radio_time(radio0_radio_time),
.radio_rx_data(radio0_radio_rx_data),
.radio_rx_stb(radio0_radio_rx_stb),
.radio_rx_running(radio0_radio_rx_running),
.radio_tx_data(radio0_radio_tx_data),
.radio_tx_stb(radio0_radio_tx_stb),
.radio_tx_running(radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
.s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}),
.m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }),
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready(s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready(m_radio0_ctrl_tready)
);
// ----------------------------------------------------
// Static Router
// ----------------------------------------------------
assign s_radio0_in_0_tdata = m_ep0_out0_tdata ;
assign s_radio0_in_0_tlast = m_ep0_out0_tlast ;
assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
assign m_ep0_out0_tready = s_radio0_in_0_tready;
assign s_radio0_in_1_tdata = m_ep1_out0_tdata ;
assign s_radio0_in_1_tlast = m_ep1_out0_tlast ;
assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid;
assign m_ep1_out0_tready = s_radio0_in_1_tready;
assign s_ep0_in0_tdata = m_radio0_out_0_tdata ;
assign s_ep0_in0_tlast = m_radio0_out_0_tlast ;
assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid;
assign m_radio0_out_0_tready = s_ep0_in0_tready;
assign s_ep1_in0_tdata = m_radio0_out_1_tdata ;
assign s_ep1_in0_tlast = m_radio0_out_1_tlast ;
assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid;
assign m_radio0_out_1_tready = s_ep1_in0_tready;
// ----------------------------------------------------
// Unused Ports
// ----------------------------------------------------
// ----------------------------------------------------
// Clock Domains
// ----------------------------------------------------
assign radio0_radio_clk = radio_clk;
// ----------------------------------------------------
// IO Port Connection
// ----------------------------------------------------
// Master/Slave Connections:
assign m_ctrlport_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_req_rd = radio0_m_ctrlport_req_rd;
assign m_ctrlport_req_addr = radio0_m_ctrlport_req_addr;
assign m_ctrlport_req_data = radio0_m_ctrlport_req_data;
assign m_ctrlport_req_byte_en = radio0_m_ctrlport_req_byte_en;
assign m_ctrlport_req_has_time = radio0_m_ctrlport_req_has_time;
assign m_ctrlport_req_time = radio0_m_ctrlport_req_time;
assign radio0_m_ctrlport_resp_ack = m_ctrlport_resp_ack;
assign radio0_m_ctrlport_resp_status = m_ctrlport_resp_status;
assign radio0_m_ctrlport_resp_data = m_ctrlport_resp_data;
assign radio0_radio_rx_data = radio_rx_data;
assign radio0_radio_rx_stb = radio_rx_stb;
assign radio_rx_running = radio0_radio_rx_running;
assign radio_tx_data = radio0_radio_tx_data;
assign radio0_radio_tx_stb = radio_tx_stb;
assign radio_tx_running = radio0_radio_tx_running;
// Broadcaster/Listener Connections:
assign radio0_radio_time = radio_time;
endmodule
top/e31x/e31x_rfnoc_image_core.yml
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# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers
license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers
version: 1.0 # File version
rfnoc_version: 1.0 # RFNoC protocol version
chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'e31x'
default_target: 'E310_SG3'
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 16384 # Ingress buffer size for data
ep1: # Stream endpoint name
ctrl: False # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 16384 # Ingress buffer size for data
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
radio0: # NoC block name
block_desc: 'radio_2x64.yml' # Block device descriptor
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
- { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
- { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
- { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio }
- { srcblk: _device_, srcport: x300_radio, dstblk: radio0, dstport: x300_radio }
- { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
top/e31x/e31x_timing.xdc
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#
# Copyright 2018 Ettus Research, A National Instruments Company
# SPDX-License-Identifier: LGPL-3.0
#
# Description: Timing constraints for the USRP E31X
#
###############################################################################
# Input Clocks
###############################################################################
# 10MHz / PPS References
create_clock -period 100.000 -name pps_ext [get_nets PPS_EXT_IN]
create_clock -period 100.000 -name gps_pps [get_nets GPS_PPS]
# TCXO clock 40 MHz
create_clock -period 25.000 -name TCXO_CLK [get_nets TCXO_CLK]
set_input_jitter TCXO_CLK 0.100
###############################################################################
# Rename Clocks
###############################################################################
create_clock -period 10.000 \
-name bus_clk [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/FCLKCLK[0]}]
set_input_jitter bus_clk 0.300
create_clock -period 25.000 \
-name clk40 [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/FCLKCLK[1]}]
set_input_jitter clk40 0.750
#create_clock -period 5.000 \
# -name bus_clk [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/FCLKCLK[3]}]
#set_input_jitter bus_clk 0.150
###############################################################################
# Timing Constraints for E310 daughter board signals
###############################################################################
# CAT_DATA_CLK is the data clock from AD9361, sample rate dependent with a max rate of 61.44 MHz
set cat_data_clk_period 16.276;
set cat_data_clk_duty_cycle_var [expr $cat_data_clk_period * (0.55 - 0.45)];
set tcxo_jitter 0.0005; # Calculated from datasheet phase noise
create_clock -period $cat_data_clk_period -name CAT_DATA_CLK [get_ports CAT_DATA_CLK]
# Model variable duty cycle as jitter.
set_input_jitter CAT_DATA_CLK [expr $cat_data_clk_duty_cycle_var + $tcxo_jitter]
# Generate DAC output clock
create_generated_clock -name CAT_FB_CLK -multiply_by 1 -source [get_pins e310_io/oddr_clk/C] [get_ports CAT_FB_CLK]
# Asynchronous clock domains
set_clock_groups -asynchronous \
-group [get_clocks -include_generated_clocks CAT_DATA_CLK] \
-group [get_clocks -include_generated_clocks bus_clk] \
-group [get_clocks -include_generated_clocks TCXO_CLK]
set_clock_groups -asynchronous \
-group [get_clocks -include_generated_clocks *clk_200M_o] \
-group [get_clocks -include_generated_clocks pps_ext] \
-group [get_clocks -include_generated_clocks gps_pps]
#TODO: I don't think this was getting used on E310
# Logically exclusive clocks in catcodec capture interface. These two clocks are the input to a BUFG mux that
# drives radio_clk, meaning only one of the two can drive radio_clk at a time.
#set_clock_groups -logically_exclusive # -group [get_clocks -include_generated_clocks {clk0}] # -group [get_clocks -include_generated_clocks {clkdv}]
# Setup ADC (AD9361) interface constraints.
set cat_data_prog_dly 4.5; # Programmable skew in AD9361 set to delay RX data by 4.5 ns
set cat_data_clk_to_data_out_min 0;
set cat_data_clk_to_data_out_max 1.2;
set_input_delay -clock [get_clocks CAT_DATA_CLK] -max [expr $cat_data_prog_dly + $cat_data_clk_to_data_out_max] [get_ports {CAT_P0_D* CAT_RX_FRAME}]
set_input_delay -clock [get_clocks CAT_DATA_CLK] -min [expr $cat_data_prog_dly + $cat_data_clk_to_data_out_min] [get_ports {CAT_P0_D* CAT_RX_FRAME}]
set_input_delay -clock [get_clocks CAT_DATA_CLK] -max [expr $cat_data_prog_dly + $cat_data_clk_to_data_out_max] [get_ports {CAT_P0_D* CAT_RX_FRAME}] -clock_fall -add_delay
set_input_delay -clock [get_clocks CAT_DATA_CLK] -min [expr $cat_data_prog_dly + $cat_data_clk_to_data_out_min] [get_ports {CAT_P0_D* CAT_RX_FRAME}] -clock_fall -add_delay
set cat_fb_data_prog_dly 4.5; # Programmable skew in AD9361 set to delay TX data by 4.5 ns
set cat_fb_data_setup 1.0;
set cat_fb_data_hold 0;
set_output_delay -clock CAT_FB_CLK -max [expr $cat_fb_data_prog_dly + $cat_fb_data_setup] [get_ports {CAT_P1_D* CAT_TX_FRAME}]
set_output_delay -clock CAT_FB_CLK -min [expr $cat_fb_data_prog_dly - $cat_fb_data_hold] [get_ports {CAT_P1_D* CAT_TX_FRAME}]
set_output_delay -clock CAT_FB_CLK -max [expr $cat_fb_data_prog_dly + $cat_fb_data_setup] [get_ports {CAT_P1_D* CAT_TX_FRAME}] -clock_fall -add_delay;
set_output_delay -clock CAT_FB_CLK -min [expr $cat_fb_data_prog_dly - $cat_fb_data_hold] [get_ports {CAT_P1_D* CAT_TX_FRAME}] -clock_fall -add_delay;
# TODO: CAT SPI
# Xilinx doesn't allow you to fully constrain EMIO because the internal SPI
# clock is not accessible. So delay constraints are used to limit the delays to
# compatible values.
# Transceiver SPI
set_max_delay -from [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0MO] \
-to [get_ports CAT_MOSI] 10.000 -datapath_only
set_min_delay -to [get_ports CAT_MOSI] 1.000
#
set_max_delay -from [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0SCLKO] \
-to [get_ports CAT_SCLK] 10.000 -datapath_only
set_min_delay -to [get_ports CAT_SCLK] 1.000
#
set_max_delay -from [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0SSON[0]}] \
-to [get_ports CAT_CS] 10.000 -datapath_only
set_min_delay -to [get_ports CAT_CS] 1.000
#
set_max_delay -from [get_ports CAT_MISO] \
-to [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0MI] 10.000 -datapath_only
set_min_delay -from [get_ports CAT_MISO] \
-to [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0MI] 1.000
###############################################################################
# PPS and Ref Clk Input Timing
###############################################################################
# Asynchronous clock domains
set_clock_groups -asynchronous \
-group [get_clocks -include_generated_clocks bus_clk] \
-group [get_clocks -include_generated_clocks pps_ext] \
-group [get_clocks -include_generated_clocks gps_pps]
# TCXO DAC SPI
# 12 MHz SPI clock rate
set_max_delay -datapath_only -from [all_registers -edge_triggered] -to [get_ports TCXO_DAC*] 40.000
set_min_delay -from [all_registers -edge_triggered] -to [get_ports TCXO_DAC*] 1.000
# User GPIO
set_max_delay -datapath_only -to [get_ports PL_GPIO*] -from [all_registers -edge_triggered] [expr 15.0]
set_min_delay -to [get_ports PL_GPIO*] -from [all_registers -edge_triggered] 5.0
set_max_delay -datapath_only -from [get_ports PL_GPIO*] -to [all_registers -edge_triggered] [expr 15.0]
set_min_delay -from [get_ports PL_GPIO*] -to [all_registers -edge_triggered] 5.0
# GPIO muxing
set_max_delay -from [get_pins e31x_core_inst/fp_gpio_src_reg_reg[*]/C] -to [get_clocks CAT_DATA_CLK] $cat_data_clk_period -datapath_only
###############################################################################
# False Paths
###############################################################################
# Synchronizer core false paths
set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/D}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/S}]
# USR_ACCESS build date
set_false_path -through [get_pins {usr_access_i/DATA[*]}]
###############################################################################
## Asynchronous paths
###############################################################################
set_false_path -from [get_ports CAT_CTRL_OUT]
set_false_path -to [get_ports CAT_RESET]
set_false_path -to [get_ports RX*_BANDSEL*]
set_false_path -to [get_ports TX_BANDSEL*]
set_false_path -to [get_ports TX_ENABLE*]
set_false_path -to [get_ports LED_*]
set_false_path -to [get_ports VCRX*]
set_false_path -to [get_ports VCTX*]
set_false_path -from [get_ports ONSWITCH_DB]
top/e31x/ip/.gitignore
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vivado*
managed_ip_project
top/e31x/ip/Makefile.inc
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#
# Copyright 2014 Ettus Research
#
#include $(IP_DIR)/axi4_dualport_sram/Makefile.inc
#include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc
#include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc
#include $(IP_DIR)/axi_intercon_4x64_256_bd/Makefile.inc
#include $(IP_DIR)/ddr3_32bit/Makefile.inc
include $(IP_DIR)/fifo_4k_2clk/Makefile.inc
include $(IP_DIR)/fifo_short_2clk/Makefile.inc
#include $(IP_DIR)/input_sample_fifo/Makefile.inc
#include $(IP_DIR)/misc_clock_gen/Makefile.inc
#include $(IP_DIR)/axi3_to_axi4lite_protocol_converter/Makefile.inc
#include $(IP_DIR)/axis_fifo_to_axi4lite/Makefile.inc
#include $(IP_DIR)/axi4_to_axi3_protocol_converter_32/Makefile.inc
#include $(IP_DIR)/axi4_to_axi3_protocol_converter_64/Makefile.inc
include $(IP_DIR)/e31x_ps_bd/Makefile.inc
include $(IP_DIR)/mig_7series_0/Makefile.inc
BD_SRCS = \
$(IP_AXI_INTERCON_4X64_256_BD_SRCS) \
$(IP_E31X_PS_BD_SRCS)
IP_XCI_SRCS = \
$(IP_FIFO_SHORT_2CLK_SRCS) \
$(IP_AXI64_4K_2CLK_FIFO_SRCS) \
$(IP_AXI64_8K_2CLK_FIFO_SRCS) \
$(IP_MIG_7SERIES_0_SRCS) \
$(IP_FIFO_4K_2CLK_SRCS) \
#$(IP_AXI4_BRAM_SRCS) \
#$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS) \
#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_SRCS) \
#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS) \
#$(IP_AXIS_FIFO_TO_AXI4LITE_SRCS) \
#$(IP_MISC_CLOCK_GEN_SRCS) \
IP_DRAM_XCI_SRCS = \
$(IP_DDR3_32BIT_SRCS)
## Currently unused
## $(IP_INPUT_SAMPLE_FIFO_SRCS) \
IP_SYNTH_OUTPUTS = \
$(IP_FIFO_SHORT_2CLK_OUTS) \
$(IP_AXI64_4K_2CLK_FIFO_OUTS) \
$(IP_AXI64_8K_2CLK_FIFO_OUTS) \
$(IP_FIFO_4K_2CLK_OUTS) \
$(IP_MIG_7SERIES_0_OUTS) \
#$(IP_AXI4_BRAM_OUTS) \
#$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS) \
#$(IP_AXI_INTERCONNECT_OUTS) \
#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS) \
#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS) \
#$(IP_AXIS_FIFO_TO_AXI4LITE_OUTS) \
BD_OUTPUTS = \
$(IP_AXI_INTERCON_4X64_256_BD_OUTS) \
$(IP_E31X_PS_BD_OUTS)
# Currently unused
# $(IP_INPUT_SAMPLE_FIFO_OUTS) \
# $(IP_AXI_INTERCON_4X64_128_OUTS) \
ip: $(IP_SYNTH_OUTPUTS) $(BD_OUTPUTS)
.PHONY: ip
top/e31x/ip/e31x_ps_bd/Makefile.inc
+35
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#
# Copyright 2018 Ettus Research
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
include $(LIB_DIR)/rfnoc/utils/Makefile.srcs
IP_E31X_PS_ORIG_SRCS = $(addprefix $(IP_DIR)/e31x_ps_bd/, \
e31x_ps_bd.tcl \
chdr_dma_rx.tcl \
chdr_dma_tx.tcl \
chdr_dma_frame_size.tcl \
chdr_dma_top.tcl \
)
IP_E31X_PS_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/e31x_ps_bd/, \
e31x_ps_bd.tcl \
chdr_dma_rx.tcl \
chdr_dma_tx.tcl \
chdr_dma_frame_size.tcl \
chdr_dma_top.tcl \
)
IP_E31X_PS_HDL_SRCS = $(RFNOC_UTIL_SRCS)
IP_E31X_PS_BD_SRCS = $(IP_BUILD_DIR)/e31x_ps_bd/e31x_ps_bd/e31x_ps_bd.bd
BD_E31X_PS_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/e31x_ps_bd/, \
e31x_ps_bd.bd.out \
e31x_ps_bd/e31x_ps_bd_ooc.xdc \
)
$(IP_E31X_PS_BD_SRCS) $(BD_E31X_PS_BD_OUTS) $(IP_E31X_PS_BDTCL_SRCS): $(IP_E31X_PS_ORIG_SRCS) $(IP_E31X_PS_HDL_SRCS)
$(call BUILD_VIVADO_BDTCL,e31x_ps_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_E31X_PS_HDL_SRCS))
top/e31x/ip/e31x_ps_bd/chdr_dma_frame_size.tcl
+59
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@@ -0,0 +1,59 @@
# Hierarchical cell: mtu
proc create_hier_cell_mtu { parentCell nameHier numPorts } {
if { $parentCell eq "" || $nameHier eq "" } {
puts "ERROR: create_hier_cell_mtu() - Empty argument(s)!"
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
# Create cells and wire everything up
create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs
connect_bd_net -net mtu_regs_1 [get_bd_pins mtu_regs]
# BUG: Vivado 2015.4 does not connect nets the first time with just the driver
connect_bd_net -quiet -net mtu_regs_1 [get_bd_pins mtu_regs]
for {set i 0} {$i < $numPorts} {incr i} {
# Create instance: xlslice_0, and set properties
set xlslice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_$i ]
set_property -dict [ list \
CONFIG.DIN_FROM [expr $i * 32 + 15] \
CONFIG.DIN_TO [expr $i * 32] \
CONFIG.DIN_WIDTH [expr $numPorts * 32] \
CONFIG.DOUT_WIDTH {16} \
] $xlslice
connect_bd_net -net mtu_regs_1 [get_bd_pins $xlslice/Din]
create_bd_pin -dir O -from 15 -to 0 mtu$i
connect_bd_net [get_bd_pins mtu$i] [get_bd_pins $xlslice/Dout]
}
# Restore current instance
current_bd_instance $oldCurInst
}
top/e31x/ip/e31x_ps_bd/chdr_dma_rx.tcl
+339
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set scriptDir [file dirname [info script]]
source "$scriptDir/chdr_dma_frame_size.tcl"
proc create_hier_cell_rx_dma_channel { parentCell nameHier } {
if { $parentCell eq "" || $nameHier eq "" } {
puts "ERROR: create_hier_cell_dma() - Empty argument(s)!"
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
#########################
# Pin list
#########################
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_dest_axi
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
create_bd_pin -dir I -from 15 -to 0 frame_size
create_bd_pin -dir O -type intr irq
create_bd_pin -dir I -type rst m_dest_axi_aresetn
create_bd_pin -dir I -type clk s_axi_aclk
create_bd_pin -dir I -type rst s_axi_aresetn
create_bd_pin -dir I -type clk s_axis_aclk
#########################
# Instantiate IPs
#########################
set reset_inv [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 reset_inv ]
set_property -dict [ list \
CONFIG.C_SIZE {1} \
CONFIG.C_OPERATION {not} \
] $reset_inv
set chdr_padder [ create_bd_cell -type module -reference chdr_pad_packet chdr_padder ]
set_property -dict [ list \
CONFIG.CHDR_W {64} \
] $chdr_padder
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_pins chdr_padder/rst]
set axi_rx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_rx_dmac ]
set_property -dict [ list \
CONFIG.ASYNC_CLK_DEST_REQ {true} \
CONFIG.ASYNC_CLK_REQ_SRC {true} \
CONFIG.ASYNC_CLK_SRC_DEST {false} \
CONFIG.DMA_AXI_PROTOCOL_DEST {1} \
CONFIG.DMA_TYPE_SRC {1} \
CONFIG.SYNC_TRANSFER_START {false} \
] $axi_rx_dmac
#########################
# Wiring
#########################
# Top-level connections
connect_bd_net -net aclk_1 \
[get_bd_pins s_axis_aclk] \
[get_bd_pins chdr_padder/clk] \
[get_bd_pins axi_rx_dmac/m_dest_axi_aclk] \
[get_bd_pins axi_rx_dmac/s_axis_aclk]
connect_bd_net -net aresetn_1 \
[get_bd_pins m_dest_axi_aresetn] \
[get_bd_pins reset_inv/Op1] \
[get_bd_pins axi_rx_dmac/m_dest_axi_aresetn]
connect_bd_net -net areset_1 \
[get_bd_pins reset_inv/Res] \
[get_bd_pins chdr_padder/rst]
connect_bd_net -net s_axi_aclk_1 \
[get_bd_pins s_axi_aclk] \
[get_bd_pins axi_rx_dmac/s_axi_aclk]
connect_bd_net -net s_axi_aresetn_1 \
[get_bd_pins s_axi_aresetn] \
[get_bd_pins axi_rx_dmac/s_axi_aresetn]
connect_bd_net -net axi_rx_dmac_irq \
[get_bd_pins irq] \
[get_bd_pins axi_rx_dmac/irq]
connect_bd_net -net mtu \
[get_bd_pins frame_size] \
[get_bd_pins chdr_padder/len]
# Control and DMA ports
connect_bd_intf_net -intf_net axi_rx_dmac_s_axi \
[get_bd_intf_pins s_axi] \
[get_bd_intf_pins axi_rx_dmac/s_axi]
connect_bd_intf_net -intf_net axi_rx_dmac_m_dest_axi \
[get_bd_intf_pins m_dest_axi] \
[get_bd_intf_pins axi_rx_dmac/m_dest_axi]
# AXI-Stream ports
connect_bd_intf_net -intf_net s_axis_dma \
[get_bd_intf_pins S_AXIS] \
[get_bd_intf_pins chdr_padder/s_axis]
connect_bd_intf_net -intf_net s_axis_dma_padded \
[get_bd_intf_pins chdr_padder/m_axis] \
[get_bd_intf_pins axi_rx_dmac/s_axis]
# Restore current instance
current_bd_instance $oldCurInst
}
# Hierarchical cell: rx
proc create_hier_cell_rx_dma { parentCell nameHier numPorts } {
if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } {
puts "ERROR: create_hier_cell_rx() - Empty argument(s)!"
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
if { $numPorts < 1 } {
puts "ERROR: numPorts invalid: $numPorts"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
#########################
# Pin list
#########################
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_DMA
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac
create_bd_pin -dir I bus_clk
create_bd_pin -dir I bus_rstn
create_bd_pin -dir I clk40
create_bd_pin -dir I clk40_rstn
create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq
create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs
#########################
# Instantiate IPs
#########################
# For sharing one S_AXI_HP port across all RX DMA engines
set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ]
set_property -dict [ list \
CONFIG.CONNECTIVITY_MODE {SASD} \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI $numPorts \
CONFIG.R_REGISTER {1} \
] $axi_crossbar_0
# For fanning out AXI-Lite bus to all RX DMA engines
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_MI $numPorts \
] $axi_interconnect_0
# Routes AXI-Stream to appropriate RX DMA engine
set axis_switch_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_0 ]
set_property -dict [ list \
CONFIG.DECODER_REG {1} \
CONFIG.NUM_MI $numPorts \
CONFIG.NUM_SI {1} \
] $axis_switch_0
# Cross domains from incoming AXI-Stream to RX DMA engines domain
# Note that the fifo_generator_0 is hard-coded to have 4 TDEST bits, so we
# are limited to 16 RX DMA channels
set fifo_generator_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 fifo_generator_0 ]
set_property -dict [ list \
CONFIG.Clock_Type_AXI {Independent_Clock} \
CONFIG.Empty_Threshold_Assert_Value_axis {1021} \
CONFIG.Empty_Threshold_Assert_Value_rach {13} \
CONFIG.Empty_Threshold_Assert_Value_rdch {1021} \
CONFIG.Empty_Threshold_Assert_Value_wach {13} \
CONFIG.Empty_Threshold_Assert_Value_wdch {1021} \
CONFIG.Empty_Threshold_Assert_Value_wrch {13} \
CONFIG.Enable_TLAST {true} \
CONFIG.FIFO_Implementation_axis {Independent_Clocks_Block_RAM} \
CONFIG.FIFO_Implementation_rach {Independent_Clocks_Distributed_RAM} \
CONFIG.FIFO_Implementation_rdch {Independent_Clocks_Block_RAM} \
CONFIG.FIFO_Implementation_wach {Independent_Clocks_Distributed_RAM} \
CONFIG.FIFO_Implementation_wdch {Independent_Clocks_Block_RAM} \
CONFIG.FIFO_Implementation_wrch {Independent_Clocks_Distributed_RAM} \
CONFIG.Full_Flags_Reset_Value {1} \
CONFIG.Full_Threshold_Assert_Value_axis {1023} \
CONFIG.Full_Threshold_Assert_Value_rach {15} \
CONFIG.Full_Threshold_Assert_Value_wach {15} \
CONFIG.Full_Threshold_Assert_Value_wrch {15} \
CONFIG.HAS_TKEEP {false} \
CONFIG.INTERFACE_TYPE {AXI_STREAM} \
CONFIG.Input_Depth_axis {1024} \
CONFIG.Reset_Type {Asynchronous_Reset} \
CONFIG.TDATA_NUM_BYTES {8} \
CONFIG.TDEST_WIDTH {4} \
CONFIG.TKEEP_WIDTH {0} \
CONFIG.TSTRB_WIDTH {8} \
CONFIG.TUSER_WIDTH {0} \
] $fifo_generator_0
set rx_dmac_irq_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 rx_dmac_irq_concat ]
set_property -dict [ list \
CONFIG.NUM_PORTS $numPorts \
] $rx_dmac_irq_concat
create_hier_cell_mtu $hier_obj mtu $numPorts
#########################
# Wiring
#########################
connect_bd_intf_net -intf_net S00_AXIS_1 \
[get_bd_intf_pins S_AXIS_DMA] \
[get_bd_intf_pins fifo_generator_0/S_AXIS]
connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \
[get_bd_intf_pins M_AXI_RX_DMA] \
[get_bd_intf_pins axi_crossbar_0/M00_AXI]
connect_bd_intf_net -intf_net fifo_generator_0_M_AXIS \
[get_bd_intf_pins axis_switch_0/S00_AXIS] \
[get_bd_intf_pins fifo_generator_0/M_AXIS]
connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \
[get_bd_intf_pins s_axi_rx_dmac] \
[get_bd_intf_pins axi_interconnect_0/S00_AXI]
connect_bd_net -net aresetn_1 \
[get_bd_pins bus_rstn] \
[get_bd_pins fifo_generator_0/s_aresetn]
connect_bd_net -net bus_clk \
[get_bd_pins bus_clk] \
[get_bd_pins fifo_generator_0/s_aclk]
connect_bd_net -net clk40 \
[get_bd_pins clk40] \
[get_bd_pins axi_crossbar_0/aclk] \
[get_bd_pins axi_interconnect_0/ACLK] \
[get_bd_pins axi_interconnect_0/S00_ACLK] \
[get_bd_pins axis_switch_0/aclk] \
[get_bd_pins fifo_generator_0/m_aclk]
connect_bd_net -net clk40_rstn \
[get_bd_pins clk40_rstn] \
[get_bd_pins axi_crossbar_0/aresetn] \
[get_bd_pins axi_interconnect_0/ARESETN] \
[get_bd_pins axi_interconnect_0/S00_ARESETN] \
[get_bd_pins axis_switch_0/aresetn]
connect_bd_net -net mtu_regs_1 \
[get_bd_pins mtu_regs] \
[get_bd_pins mtu/mtu_regs]
connect_bd_net -net rx_dmac_irq_concat_dout \
[get_bd_pins irq] \
[get_bd_pins rx_dmac_irq_concat/dout]
#########################
# Per-port Section
#########################
for {set i 0} {$i < $numPorts} {incr i} {
puts "Instantiating rx_dma port ${i}"
create_hier_cell_rx_dma_channel $hier_obj dma$i
set_property -dict [ list \
[format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} \
] $axi_crossbar_0
connect_bd_intf_net -intf_net [format "axis_switch_0_M%02d_AXIS" ${i}] \
[get_bd_intf_pins [format "axis_switch_0/M%02d_AXIS" ${i}]] \
[get_bd_intf_pins dma${i}/S_AXIS]
connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \
[get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \
[get_bd_intf_pins dma${i}/s_axi]
connect_bd_intf_net -intf_net dma${i}_m_dest_axi \
[get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \
[get_bd_intf_pins dma${i}/m_dest_axi]
connect_bd_net -net clk40 \
[get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]] \
[get_bd_pins dma${i}/s_axi_aclk] \
[get_bd_pins dma${i}/s_axis_aclk]
connect_bd_net -net clk40_rstn \
[get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \
[get_bd_pins dma${i}/m_dest_axi_aresetn] \
[get_bd_pins dma${i}/s_axi_aresetn]
connect_bd_net -net dma${i}_irq \
[get_bd_pins dma${i}/irq] \
[get_bd_pins rx_dmac_irq_concat/In${i}]
connect_bd_net -net frame_size_${i} \
[get_bd_pins dma${i}/frame_size] \
[get_bd_pins mtu/mtu${i}]
}
# Restore current instance
current_bd_instance $oldCurInst
}
top/e31x/ip/e31x_ps_bd/chdr_dma_top.tcl
+159
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set scriptDir [file dirname [info script]]
source "$scriptDir/chdr_dma_rx.tcl"
source "$scriptDir/chdr_dma_tx.tcl"
# Hierarchical cell: dma
proc create_hier_cell_dma { parentCell nameHier numPorts } {
if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } {
puts "ERROR: create_hier_cell_dma() - Empty argument(s)!"
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
if { $numPorts < 2 } {
puts "ERROR: numPorts invalid: $numPorts"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
#########################
# Pin list
#########################
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_regfile
create_bd_pin -dir I bus_clk
create_bd_pin -dir I bus_rstn
create_bd_pin -dir I clk40
create_bd_pin -dir I clk40_rstn
create_bd_pin -dir O rx_irq
create_bd_pin -dir O tx_irq
#########################
# Instantiate IPs
#########################
# Create instance: rx
create_hier_cell_rx_dma $hier_obj rx $numPorts
# Create instance: tx
create_hier_cell_tx_dma $hier_obj tx $numPorts
# Used to set frame size of RX DMA engines
set axi_regfile_0 [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_regfile:1.0 axi_regfile_0 ]
set_property -dict [ list \
CONFIG.NUM_REGS $numPorts \
] $axi_regfile_0
set util_reduced_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_0 ]
set_property -dict [ list \
CONFIG.C_OPERATION {or} \
CONFIG.C_SIZE $numPorts \
] $util_reduced_logic_0
set util_reduced_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_1 ]
set_property -dict [ list \
CONFIG.C_OPERATION {or} \
CONFIG.C_SIZE $numPorts \
] $util_reduced_logic_1
#########################
# Wiring
#########################
# Clocks and resets
connect_bd_net -net bus_clk_1 \
[get_bd_pins bus_clk] \
[get_bd_pins rx/bus_clk] \
[get_bd_pins tx/bus_clk]
connect_bd_net -net bus_rstn_1 \
[get_bd_pins bus_rstn] \
[get_bd_pins rx/bus_rstn] \
[get_bd_pins tx/bus_rstn]
connect_bd_net -net clk40_1 \
[get_bd_pins clk40] \
[get_bd_pins rx/clk40] \
[get_bd_pins tx/clk40] \
[get_bd_pins axi_regfile_0/S_AXI_ACLK]
connect_bd_net -net clk40_rstn_1 \
[get_bd_pins clk40_rstn] \
[get_bd_pins axi_regfile_0/S_AXI_ARESETN] \
[get_bd_pins rx/clk40_rstn] \
[get_bd_pins tx/clk40_rstn]
# AXI buses
connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \
[get_bd_intf_pins s_axi_rx_dmac] \
[get_bd_intf_pins rx/s_axi_rx_dmac]
connect_bd_intf_net -intf_net rx_dma_M_AXI_RX_DMA \
[get_bd_intf_pins M_AXI_RX_DMA] \
[get_bd_intf_pins rx/M_AXI_RX_DMA]
connect_bd_intf_net -intf_net s_axi_tx_dmac_1 \
[get_bd_intf_pins s_axi_tx_dmac] \
[get_bd_intf_pins tx/s_axi_tx_dmac]
connect_bd_intf_net -intf_net tx_M_AXI_TX_DMA \
[get_bd_intf_pins M_AXI_TX_DMA] \
[get_bd_intf_pins tx/M_AXI_TX_DMA]
connect_bd_intf_net -intf_net s_axi_regfile_1 \
[get_bd_intf_pins s_axi_regfile] \
[get_bd_intf_pins axi_regfile_0/S_AXI]
# RX CHDR
connect_bd_intf_net -intf_net s_axis_dma_1 \
[get_bd_intf_pins s_axis_dma] \
[get_bd_intf_pins rx/S_AXIS_DMA]
# TX CHDR
connect_bd_intf_net -intf_net m_axis_dma_1 \
[get_bd_intf_pins tx/M_AXIS_DMA] \
[get_bd_intf_pins m_axis_dma]
# IRQs and Frame Sizes
connect_bd_net -net frame_sizes \
[get_bd_pins axi_regfile_0/regs] \
[get_bd_pins rx/mtu_regs]
connect_bd_net -net rx_irq1 \
[get_bd_pins rx/irq] \
[get_bd_pins util_reduced_logic_0/Op1]
connect_bd_net -net tx_irq1 \
[get_bd_pins tx/irq] \
[get_bd_pins util_reduced_logic_1/Op1]
connect_bd_net -net util_reduced_logic_0_Res \
[get_bd_pins rx_irq] \
[get_bd_pins util_reduced_logic_0/Res]
connect_bd_net -net util_reduced_logic_1_Res \
[get_bd_pins tx_irq] \
[get_bd_pins util_reduced_logic_1/Res]
# Restore current instance
current_bd_instance $oldCurInst
}
top/e31x/ip/e31x_ps_bd/chdr_dma_tx.tcl
+193
View File
@@ -0,0 +1,193 @@
# Hierarchical cell: tx
proc create_hier_cell_tx_dma { parentCell nameHier numPorts } {
if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } {
puts "ERROR: create_hier_cell_tx() - Empty argument(s)!"
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
if { $numPorts < 1 } {
puts "ERROR: numPorts invalid: $numPorts"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
#########################
# Pin list
#########################
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_DMA
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac
create_bd_pin -dir I bus_clk
create_bd_pin -dir I bus_rstn
create_bd_pin -dir I clk40
create_bd_pin -dir I clk40_rstn
create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq
#########################
# Instantiate IPs
#########################
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_MI $numPorts \
] $axi_interconnect_0
set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI $numPorts
] $axi_crossbar_0
set axis_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_interconnect:2.1 axis_interconnect_0 ]
set_property -dict [ list \
CONFIG.ARB_ON_TLAST {1} \
CONFIG.ARB_ON_MAX_XFERS {0} \
CONFIG.ENABLE_ADVANCED_OPTIONS {1} \
CONFIG.M00_HAS_REGSLICE {1} \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI $numPorts \
] $axis_interconnect_0
set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
set_property -dict [ list \
CONFIG.NUM_PORTS $numPorts \
] $xlconcat_0
set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
set_property -dict [ list \
CONFIG.CONST_VAL {0} \
] $xlconstant_0
#########################
# Wiring
#########################
connect_bd_net -net bus_clk \
[get_bd_pins bus_clk] \
[get_bd_pins axis_interconnect_0/ACLK] \
[get_bd_pins axis_interconnect_0/M00_AXIS_ACLK]
connect_bd_net -net bus_rstn \
[get_bd_pins bus_rstn] \
[get_bd_pins axis_interconnect_0/ARESETN] \
[get_bd_pins axis_interconnect_0/M00_AXIS_ARESETN]
connect_bd_net -net clk40 \
[get_bd_pins clk40] \
[get_bd_pins axi_crossbar_0/aclk] \
[get_bd_pins axi_interconnect_0/ACLK] \
[get_bd_pins axi_interconnect_0/S00_ACLK]
connect_bd_net -net clk40_rstn \
[get_bd_pins clk40_rstn] \
[get_bd_pins axi_crossbar_0/aresetn] \
[get_bd_pins axi_interconnect_0/ARESETN] \
[get_bd_pins axi_interconnect_0/S00_ARESETN]
connect_bd_net -net xlconstant_0_dout \
[get_bd_pins xlconstant_0/dout]
connect_bd_net -net xlconcat_0_dout \
[get_bd_pins irq] \
[get_bd_pins xlconcat_0/dout]
connect_bd_intf_net -intf_net M_AXI_TX_DMAC_1 \
[get_bd_intf_pins s_axi_tx_dmac] \
[get_bd_intf_pins axi_interconnect_0/S00_AXI]
connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \
[get_bd_intf_pins M_AXI_TX_DMA] \
[get_bd_intf_pins axi_crossbar_0/M00_AXI]
connect_bd_intf_net -intf_net axis_interconnect_0_M00_AXIS \
[get_bd_intf_pins M_AXIS_DMA] \
[get_bd_intf_pins axis_interconnect_0/M00_AXIS]
#########################
# Per-port Section
#########################
for {set i 0} {$i < $numPorts} {incr i} {
# Configure each port on axi_crossbar and axis_interconnect
puts "Creating TX dma port ${i}"
set_property [format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} $axi_crossbar_0
set_property -dict [ list \
[format "CONFIG.S%02d_HAS_REGSLICE" ${i}] {1} \
] $axis_interconnect_0
set axi_tx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_tx_dmac_$i ]
set_property -dict [ list \
CONFIG.DMA_TYPE_DEST {1} \
CONFIG.DMA_TYPE_SRC {0} \
] $axi_tx_dmac
# Add a tuser signal indicating which DMA channel originated the packet
# Hard-coded to handle up to 16 DMA channels
# Convert i (in decimal) to 4-bit binary:
binary scan [binary format c ${i}] B* i_binary
set i_binary [string range ${i_binary} end-3 end]
set tuser_appender [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_subset_converter_${i} ]
set_property -dict [ list \
CONFIG.M_TUSER_WIDTH.VALUE_SRC USER \
] $tuser_appender
set_property -dict [ list \
CONFIG.M_TUSER_WIDTH {4} \
CONFIG.TUSER_REMAP 4'b${i_binary} \
] $tuser_appender
connect_bd_intf_net -intf_net [format "axis_subset_converter_%d_S_AXIS" ${i}] \
[get_bd_intf_pins $axi_tx_dmac/m_axis] \
[get_bd_intf_pins ${tuser_appender}/S_AXIS]
connect_bd_intf_net -intf_net [format "S%02d_AXIS_1" ${i}] \
[get_bd_intf_pins ${tuser_appender}/M_AXIS] \
[get_bd_intf_pins [format "axis_interconnect_0/S%02d_AXIS" ${i}]]
connect_bd_intf_net -intf_net axi_dmac_${i}_m_src_axi \
[get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \
[get_bd_intf_pins $axi_tx_dmac/m_src_axi]
connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \
[get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \
[get_bd_intf_pins $axi_tx_dmac/s_axi]
connect_bd_net [get_bd_pins $axi_tx_dmac/irq] [get_bd_pins xlconcat_0/In${i}]
connect_bd_net -net clk40 \
[get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]]\
[get_bd_pins $axi_tx_dmac/m_axis_aclk] \
[get_bd_pins $axi_tx_dmac/m_src_axi_aclk] \
[get_bd_pins $axi_tx_dmac/s_axi_aclk] \
[get_bd_pins $tuser_appender/aclk] \
[get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ACLK" ${i}]]
connect_bd_net -net clk40_rstn \
[get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \
[get_bd_pins $axi_tx_dmac/m_src_axi_aresetn] \
[get_bd_pins $axi_tx_dmac/s_axi_aresetn] \
[get_bd_pins $tuser_appender/aresetn] \
[get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ARESETN" ${i}]]
connect_bd_net -net xlconstant_0_dout \
[get_bd_pins [format "axis_interconnect_0/S%02d_ARB_REQ_SUPPRESS" ${i}]]
}
# Restore current instance
current_bd_instance $oldCurInst
}
top/e31x/ip/e31x_ps_bd/e31x_ps.tcl
+432
View File
@@ -0,0 +1,432 @@
proc getPresetInfo {} {
return [dict create name {e31x_ps} description {e31x_ps} vlnv xilinx.com:ip:processing_system7:5.5 display_name {e31x_ps} ]
}
proc validate_preset {IPINST} { return true }
proc apply_preset {IPINST} {
return [dict create \
CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \
CONFIG.PCW_FCLK_CLK2_BUF {TRUE} \
CONFIG.PCW_FCLK_CLK3_BUF {TRUE} \
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
CONFIG.PCW_UIPARAM_DDR_CL {7} \
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.054} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.040} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.041} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.010} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.096} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.102} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.100} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.090} \
CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {1000} \
CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {144.444443} \
CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {40} \
CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {166.6667} \
CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {200} \
CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {866.666687} \
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \
CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {144.444443} \
CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {40.000000} \
CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {166.666672} \
CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {144.444443} \
CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {144.444443} \
CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {144.444443} \
CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {144.444443} \
CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {144.444443} \
CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {144.444443} \
CONFIG.PCW_CLK0_FREQ {100000000} \
CONFIG.PCW_CLK1_FREQ {40000000} \
CONFIG.PCW_CLK2_FREQ {166666672} \
CONFIG.PCW_CLK3_FREQ {200000000} \
CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {20} \
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {12} \
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {10} \
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {4} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {5} \
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {3} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {2} \
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {16} \
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {10} \
CONFIG.PCW_ARMPLL_CTRL_FBDIV {52} \
CONFIG.PCW_IOPLL_CTRL_FBDIV {60} \
CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1733.333} \
CONFIG.PCW_IO_IO_PLL_FREQMHZ {2000.000} \
CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \
CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
CONFIG.PCW_EN_EMIO_ENET0 {0} \
CONFIG.PCW_EN_EMIO_GPIO {1} \
CONFIG.PCW_EN_EMIO_I2C1 {0} \
CONFIG.PCW_EN_EMIO_PJTAG {0} \
CONFIG.PCW_EN_EMIO_SPI0 {1} \
CONFIG.PCW_EN_EMIO_SPI1 {1} \
CONFIG.PCW_EN_EMIO_UART0 {0} \
CONFIG.PCW_USE_S_AXI_GP0 {0} \
CONFIG.PCW_USE_S_AXI_GP1 {0} \
CONFIG.PCW_USE_S_AXI_HP0 {0} \
CONFIG.PCW_USE_S_AXI_HP1 {1} \
CONFIG.PCW_USE_S_AXI_HP2 {1} \
CONFIG.PCW_USE_S_AXI_HP3 {0} \
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
CONFIG.PCW_USE_HIGH_OCM {1} \
CONFIG.PCW_USE_PS_SLCR_REGISTERS {1} \
CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
CONFIG.PCW_EN_ENET0 {1} \
CONFIG.PCW_EN_GPIO {1} \
CONFIG.PCW_EN_I2C0 {1} \
CONFIG.PCW_EN_I2C1 {0} \
CONFIG.PCW_EN_PJTAG {0} \
CONFIG.PCW_EN_SDIO0 {1} \
CONFIG.PCW_EN_SPI0 {1} \
CONFIG.PCW_EN_SPI1 {1} \
CONFIG.PCW_EN_UART0 {1} \
CONFIG.PCW_EN_UART1 {1} \
CONFIG.PCW_EN_USB0 {1} \
CONFIG.PCW_EN_CLK1_PORT {1} \
CONFIG.PCW_EN_CLK2_PORT {1} \
CONFIG.PCW_EN_CLK3_PORT {1} \
CONFIG.PCW_EN_RST1_PORT {0} \
CONFIG.PCW_EN_RST2_PORT {0} \
CONFIG.PCW_EN_RST3_PORT {0} \
CONFIG.PCW_IRQ_F2P_INTR {1} \
CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
CONFIG.PCW_ENET_RESET_ENABLE {1} \
CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
CONFIG.PCW_ENET0_RESET_ENABLE {1} \
CONFIG.PCW_ENET0_RESET_IO {MIO 3} \
CONFIG.PCW_ENET1_RESET_ENABLE {0} \
CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \
CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \
CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_SPI0_SPI0_IO {EMIO} \
CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1} \
CONFIG.PCW_SPI0_GRP_SS0_IO {EMIO} \
CONFIG.PCW_SPI0_GRP_SS1_ENABLE {1} \
CONFIG.PCW_SPI0_GRP_SS1_IO {EMIO} \
CONFIG.PCW_SPI0_GRP_SS2_ENABLE {1} \
CONFIG.PCW_SPI0_GRP_SS2_IO {EMIO} \
CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_SPI1_SPI1_IO {EMIO} \
CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1} \
CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO} \
CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1} \
CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO} \
CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1} \
CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \
CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_PJTAG_PJTAG_IO {<Select>} \
CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
CONFIG.PCW_USB_RESET_ENABLE {1} \
CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
CONFIG.PCW_USB0_RESET_ENABLE {1} \
CONFIG.PCW_USB0_RESET_IO {MIO 4} \
CONFIG.PCW_USB1_RESET_ENABLE {0} \
CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_I2C0_I2C0_IO {MIO 46 .. 47} \
CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
CONFIG.PCW_I2C0_RESET_ENABLE {0} \
CONFIG.PCW_I2C0_RESET_IO {<Select>} \
CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_I2C1_I2C1_IO {<Select>} \
CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \
CONFIG.PCW_I2C_RESET_ENABLE {0} \
CONFIG.PCW_I2C_RESET_SELECT {<Select>} \
CONFIG.PCW_I2C1_RESET_ENABLE {0} \
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
CONFIG.PCW_GPIO_EMIO_GPIO_IO {64} \
CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_MIO_0_PULLUP {enabled} \
CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_0_DIRECTION {inout} \
CONFIG.PCW_MIO_0_SLEW {slow} \
CONFIG.PCW_MIO_1_PULLUP {enabled} \
CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_1_DIRECTION {inout} \
CONFIG.PCW_MIO_1_SLEW {slow} \
CONFIG.PCW_MIO_2_PULLUP {disabled} \
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_2_DIRECTION {inout} \
CONFIG.PCW_MIO_2_SLEW {slow} \
CONFIG.PCW_MIO_3_PULLUP {disabled} \
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_3_DIRECTION {out} \
CONFIG.PCW_MIO_3_SLEW {slow} \
CONFIG.PCW_MIO_4_PULLUP {disabled} \
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_4_DIRECTION {out} \
CONFIG.PCW_MIO_4_SLEW {slow} \
CONFIG.PCW_MIO_5_PULLUP {disabled} \
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_5_DIRECTION {inout} \
CONFIG.PCW_MIO_5_SLEW {slow} \
CONFIG.PCW_MIO_6_PULLUP {disabled} \
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_6_DIRECTION {inout} \
CONFIG.PCW_MIO_6_SLEW {slow} \
CONFIG.PCW_MIO_7_PULLUP {disabled} \
CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_7_DIRECTION {out} \
CONFIG.PCW_MIO_7_SLEW {slow} \
CONFIG.PCW_MIO_8_PULLUP {disabled} \
CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_8_DIRECTION {out} \
CONFIG.PCW_MIO_8_SLEW {slow} \
CONFIG.PCW_MIO_9_PULLUP {enabled} \
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_9_DIRECTION {inout} \
CONFIG.PCW_MIO_9_SLEW {slow} \
CONFIG.PCW_MIO_10_PULLUP {enabled} \
CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_10_DIRECTION {inout} \
CONFIG.PCW_MIO_10_SLEW {slow} \
CONFIG.PCW_MIO_11_PULLUP {enabled} \
CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_11_DIRECTION {inout} \
CONFIG.PCW_MIO_11_SLEW {slow} \
CONFIG.PCW_MIO_12_PULLUP {enabled} \
CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_12_DIRECTION {inout} \
CONFIG.PCW_MIO_12_SLEW {slow} \
CONFIG.PCW_MIO_13_PULLUP {enabled} \
CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_13_DIRECTION {inout} \
CONFIG.PCW_MIO_13_SLEW {slow} \
CONFIG.PCW_MIO_14_PULLUP {enabled} \
CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_14_DIRECTION {in} \
CONFIG.PCW_MIO_14_SLEW {slow} \
CONFIG.PCW_MIO_15_PULLUP {enabled} \
CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_15_DIRECTION {out} \
CONFIG.PCW_MIO_15_SLEW {slow} \
CONFIG.PCW_MIO_16_PULLUP {disabled} \
CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_16_DIRECTION {out} \
CONFIG.PCW_MIO_16_SLEW {fast} \
CONFIG.PCW_MIO_17_PULLUP {disabled} \
CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_17_DIRECTION {out} \
CONFIG.PCW_MIO_17_SLEW {fast} \
CONFIG.PCW_MIO_18_PULLUP {disabled} \
CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_18_DIRECTION {out} \
CONFIG.PCW_MIO_18_SLEW {fast} \
CONFIG.PCW_MIO_19_PULLUP {disabled} \
CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_19_DIRECTION {out} \
CONFIG.PCW_MIO_19_SLEW {fast} \
CONFIG.PCW_MIO_20_PULLUP {disabled} \
CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_20_DIRECTION {out} \
CONFIG.PCW_MIO_20_SLEW {fast} \
CONFIG.PCW_MIO_21_PULLUP {disabled} \
CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_21_DIRECTION {out} \
CONFIG.PCW_MIO_21_SLEW {fast} \
CONFIG.PCW_MIO_22_PULLUP {disabled} \
CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_22_DIRECTION {in} \
CONFIG.PCW_MIO_22_SLEW {fast} \
CONFIG.PCW_MIO_23_PULLUP {disabled} \
CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_23_DIRECTION {in} \
CONFIG.PCW_MIO_23_SLEW {fast} \
CONFIG.PCW_MIO_24_PULLUP {disabled} \
CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_24_DIRECTION {in} \
CONFIG.PCW_MIO_24_SLEW {fast} \
CONFIG.PCW_MIO_25_PULLUP {disabled} \
CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_25_DIRECTION {in} \
CONFIG.PCW_MIO_25_SLEW {fast} \
CONFIG.PCW_MIO_26_PULLUP {disabled} \
CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_26_DIRECTION {in} \
CONFIG.PCW_MIO_26_SLEW {fast} \
CONFIG.PCW_MIO_27_PULLUP {disabled} \
CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_27_DIRECTION {in} \
CONFIG.PCW_MIO_27_SLEW {fast} \
CONFIG.PCW_MIO_28_PULLUP {enabled} \
CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_28_DIRECTION {inout} \
CONFIG.PCW_MIO_28_SLEW {slow} \
CONFIG.PCW_MIO_29_PULLUP {enabled} \
CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_29_DIRECTION {in} \
CONFIG.PCW_MIO_29_SLEW {slow} \
CONFIG.PCW_MIO_30_PULLUP {enabled} \
CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_30_DIRECTION {out} \
CONFIG.PCW_MIO_30_SLEW {slow} \
CONFIG.PCW_MIO_31_PULLUP {enabled} \
CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_31_DIRECTION {in} \
CONFIG.PCW_MIO_31_SLEW {slow} \
CONFIG.PCW_MIO_32_PULLUP {enabled} \
CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_32_DIRECTION {inout} \
CONFIG.PCW_MIO_32_SLEW {slow} \
CONFIG.PCW_MIO_33_PULLUP {enabled} \
CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_33_DIRECTION {inout} \
CONFIG.PCW_MIO_33_SLEW {slow} \
CONFIG.PCW_MIO_34_PULLUP {enabled} \
CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_34_DIRECTION {inout} \
CONFIG.PCW_MIO_34_SLEW {slow} \
CONFIG.PCW_MIO_35_PULLUP {enabled} \
CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_35_DIRECTION {inout} \
CONFIG.PCW_MIO_35_SLEW {slow} \
CONFIG.PCW_MIO_36_PULLUP {enabled} \
CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_36_DIRECTION {in} \
CONFIG.PCW_MIO_36_SLEW {slow} \
CONFIG.PCW_MIO_37_PULLUP {enabled} \
CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_37_DIRECTION {inout} \
CONFIG.PCW_MIO_37_SLEW {slow} \
CONFIG.PCW_MIO_38_PULLUP {enabled} \
CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_38_DIRECTION {inout} \
CONFIG.PCW_MIO_38_SLEW {slow} \
CONFIG.PCW_MIO_39_PULLUP {enabled} \
CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_39_DIRECTION {inout} \
CONFIG.PCW_MIO_39_SLEW {slow} \
CONFIG.PCW_MIO_40_PULLUP {enabled} \
CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_40_DIRECTION {inout} \
CONFIG.PCW_MIO_40_SLEW {slow} \
CONFIG.PCW_MIO_41_PULLUP {enabled} \
CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_41_DIRECTION {inout} \
CONFIG.PCW_MIO_41_SLEW {slow} \
CONFIG.PCW_MIO_42_PULLUP {enabled} \
CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_42_DIRECTION {inout} \
CONFIG.PCW_MIO_42_SLEW {slow} \
CONFIG.PCW_MIO_43_PULLUP {enabled} \
CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_43_DIRECTION {inout} \
CONFIG.PCW_MIO_43_SLEW {slow} \
CONFIG.PCW_MIO_44_PULLUP {enabled} \
CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_44_DIRECTION {inout} \
CONFIG.PCW_MIO_44_SLEW {slow} \
CONFIG.PCW_MIO_45_PULLUP {enabled} \
CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_45_DIRECTION {inout} \
CONFIG.PCW_MIO_45_SLEW {slow} \
CONFIG.PCW_MIO_46_PULLUP {enabled} \
CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_46_DIRECTION {inout} \
CONFIG.PCW_MIO_46_SLEW {slow} \
CONFIG.PCW_MIO_47_PULLUP {enabled} \
CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_47_DIRECTION {inout} \
CONFIG.PCW_MIO_47_SLEW {slow} \
CONFIG.PCW_MIO_48_PULLUP {enabled} \
CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_48_DIRECTION {out} \
CONFIG.PCW_MIO_48_SLEW {slow} \
CONFIG.PCW_MIO_49_PULLUP {enabled} \
CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_49_DIRECTION {in} \
CONFIG.PCW_MIO_49_SLEW {slow} \
CONFIG.PCW_MIO_50_PULLUP {enabled} \
CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_50_DIRECTION {inout} \
CONFIG.PCW_MIO_50_SLEW {slow} \
CONFIG.PCW_MIO_51_PULLUP {enabled} \
CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_51_DIRECTION {inout} \
CONFIG.PCW_MIO_51_SLEW {slow} \
CONFIG.PCW_MIO_52_PULLUP {enabled} \
CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_52_DIRECTION {out} \
CONFIG.PCW_MIO_52_SLEW {slow} \
CONFIG.PCW_MIO_53_PULLUP {enabled} \
CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_53_DIRECTION {inout} \
CONFIG.PCW_MIO_53_SLEW {slow} \
CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#ENET Reset#USB Reset#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#I2C 0#I2C 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \
CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#reset#reset#gpio[5]#gpio[6]#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#scl#sda#tx#rx#gpio[50]#gpio[51]#mdc#mdio} \
CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \
CONFIG.PCW_FPGA_FCLK2_ENABLE {1} \
CONFIG.PCW_FPGA_FCLK3_ENABLE {1} \
]
}
top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl
+720
View File
@@ -0,0 +1,720 @@
# CHANGE DESIGN NAME HERE
set design_name e31x_ps_bd
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
create_bd_design $design_name
current_bd_design $design_name
if { $nRet != 0 } {
puts $errMsg
return $nRet
}
set scriptDir [file dirname [info script]]
##################################################################
# DESIGN PROCs
##################################################################
source "$scriptDir/chdr_dma_top.tcl"
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
set GPIO_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0 ]
set m_axis_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma ]
set s_axis_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma ]
set_property -dict [ list \
CONFIG.HAS_TLAST 1 \
CONFIG.TDATA_NUM_BYTES 8 \
CONFIG.TDEST_WIDTH 4 \
] $s_axis_dma
set m_axi_pmu [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_pmu ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_WSTRB {0} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_pmu
set m_axi_xbar [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_xbar ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_WSTRB {0} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_xbar
set USBIND_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:usbctrl_rtl:1.0 USBIND_0 ]
# Create ports
set DDR_VRN [ create_bd_port -dir IO DDR_VRN ]
set DDR_VRP [ create_bd_port -dir IO DDR_VRP ]
set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ]
set FCLK_CLK1 [ create_bd_port -dir O -type clk FCLK_CLK1 ]
set FCLK_CLK2 [ create_bd_port -dir O -type clk FCLK_CLK2 ]
set FCLK_CLK3 [ create_bd_port -dir O -type clk FCLK_CLK3 ]
set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ]
set IRQ_F2P [ create_bd_port -dir I -from 15 -to 0 -type intr IRQ_F2P ]
set_property -dict [ list \
CONFIG.PortWidth {16} \
CONFIG.SENSITIVITY {EDGE_RISING} \
] $IRQ_F2P
set MIO [ create_bd_port -dir IO -from 53 -to 0 MIO ]
set PS_CLK [ create_bd_port -dir IO PS_CLK ]
set PS_PORB [ create_bd_port -dir IO PS_PORB ]
set PS_SRSTB [ create_bd_port -dir IO PS_SRSTB ]
set SPI0_MISO_I [ create_bd_port -dir I SPI0_MISO_I ]
set SPI0_MISO_O [ create_bd_port -dir O SPI0_MISO_O ]
set SPI0_MISO_T [ create_bd_port -dir O SPI0_MISO_T ]
set SPI0_MOSI_I [ create_bd_port -dir I SPI0_MOSI_I ]
set SPI0_MOSI_O [ create_bd_port -dir O SPI0_MOSI_O ]
set SPI0_MOSI_T [ create_bd_port -dir O SPI0_MOSI_T ]
set SPI0_SCLK_I [ create_bd_port -dir I SPI0_SCLK_I ]
set SPI0_SCLK_O [ create_bd_port -dir O SPI0_SCLK_O ]
set SPI0_SCLK_T [ create_bd_port -dir O SPI0_SCLK_T ]
set SPI0_SS1_O [ create_bd_port -dir O SPI0_SS1_O ]
set SPI0_SS2_O [ create_bd_port -dir O SPI0_SS2_O ]
set SPI0_SS_I [ create_bd_port -dir I SPI0_SS_I ]
set SPI0_SS_O [ create_bd_port -dir O SPI0_SS_O ]
set SPI0_SS_T [ create_bd_port -dir O SPI0_SS_T ]
set SPI1_MISO_I [ create_bd_port -dir I SPI1_MISO_I ]
set SPI1_MISO_O [ create_bd_port -dir O SPI1_MISO_O ]
set SPI1_MISO_T [ create_bd_port -dir O SPI1_MISO_T ]
set SPI1_MOSI_I [ create_bd_port -dir I SPI1_MOSI_I ]
set SPI1_MOSI_O [ create_bd_port -dir O SPI1_MOSI_O ]
set SPI1_MOSI_T [ create_bd_port -dir O SPI1_MOSI_T ]
set SPI1_SCLK_I [ create_bd_port -dir I SPI1_SCLK_I ]
set SPI1_SCLK_O [ create_bd_port -dir O SPI1_SCLK_O ]
set SPI1_SCLK_T [ create_bd_port -dir O SPI1_SCLK_T ]
set SPI1_SS1_O [ create_bd_port -dir O SPI1_SS1_O ]
set SPI1_SS2_O [ create_bd_port -dir O SPI1_SS2_O ]
set SPI1_SS_I [ create_bd_port -dir I SPI1_SS_I ]
set SPI1_SS_O [ create_bd_port -dir O SPI1_SS_O ]
set SPI1_SS_T [ create_bd_port -dir O SPI1_SS_T ]
set S_AXI_GP0_ACLK [ create_bd_port -dir I -type clk S_AXI_GP0_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_RESET {S_AXI_GP0_ARESETN} \
CONFIG.FREQ_HZ {40000000} \
] $S_AXI_GP0_ACLK
set S_AXI_GP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP0_ARESETN ]
set bus_clk [ create_bd_port -dir I -type clk bus_clk ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {m_axis_dma:s_axis_dma} \
CONFIG.ASSOCIATED_RESET {bus_rstn} \
CONFIG.FREQ_HZ {200000000} \
] $bus_clk
set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ]
set clk40 [ create_bd_port -dir I -type clk clk40 ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {m_axi_xbar:m_axi_pmu} \
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
CONFIG.FREQ_HZ {40000000} \
] $clk40
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.ENABLE_ADVANCED_OPTIONS {0} \
CONFIG.NUM_MI {5} \
] $axi_interconnect_0
# Create instance: dma
create_hier_cell_dma [current_bd_instance .] dma 5
# Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
set_property -dict [ list \
CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {40.000000} \
CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {166.666672} \
CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \
CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \
CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {1000} \
CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_CLK0_FREQ {100000000} \
CONFIG.PCW_CLK1_FREQ {40000000} \
CONFIG.PCW_CLK2_FREQ {166666672} \
CONFIG.PCW_CLK3_FREQ {200000000} \
CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
CONFIG.PCW_ENET0_RESET_ENABLE {1} \
CONFIG.PCW_ENET0_RESET_IO {MIO 11} \
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_ENET1_RESET_ENABLE {0} \
CONFIG.PCW_ENET_RESET_ENABLE {1} \
CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
CONFIG.PCW_EN_CLK1_PORT {1} \
CONFIG.PCW_EN_CLK2_PORT {1} \
CONFIG.PCW_EN_CLK3_PORT {1} \
CONFIG.PCW_EN_EMIO_ENET0 {0} \
CONFIG.PCW_EN_EMIO_GPIO {1} \
CONFIG.PCW_EN_EMIO_I2C1 {0} \
CONFIG.PCW_EN_EMIO_PJTAG {0} \
CONFIG.PCW_EN_EMIO_SPI0 {1} \
CONFIG.PCW_EN_EMIO_SPI1 {1} \
CONFIG.PCW_EN_EMIO_UART0 {0} \
CONFIG.PCW_EN_ENET0 {1} \
CONFIG.PCW_EN_GPIO {1} \
CONFIG.PCW_EN_I2C0 {1} \
CONFIG.PCW_EN_I2C1 {0} \
CONFIG.PCW_EN_PJTAG {0} \
CONFIG.PCW_EN_RST1_PORT {0} \
CONFIG.PCW_EN_RST2_PORT {0} \
CONFIG.PCW_EN_RST3_PORT {0} \
CONFIG.PCW_EN_SDIO0 {1} \
CONFIG.PCW_EN_SPI0 {1} \
CONFIG.PCW_EN_SPI1 {1} \
CONFIG.PCW_EN_UART0 {1} \
CONFIG.PCW_EN_UART1 {1} \
CONFIG.PCW_EN_USB0 {1} \
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {5} \
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {3} \
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {2} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {5} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \
CONFIG.PCW_FCLK_CLK2_BUF {TRUE} \
CONFIG.PCW_FCLK_CLK3_BUF {TRUE} \
CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {40} \
CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {166.6667} \
CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {200} \
CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \
CONFIG.PCW_FPGA_FCLK2_ENABLE {1} \
CONFIG.PCW_FPGA_FCLK3_ENABLE {1} \
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
CONFIG.PCW_GPIO_EMIO_GPIO_IO {64} \
CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
CONFIG.PCW_I2C0_I2C0_IO {MIO 46 .. 47} \
CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_I2C0_RESET_ENABLE {0} \
CONFIG.PCW_I2C0_RESET_IO {<Select>} \
CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \
CONFIG.PCW_I2C1_I2C1_IO {<Select>} \
CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_I2C1_RESET_ENABLE {0} \
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_I2C_RESET_ENABLE {0} \
CONFIG.PCW_I2C_RESET_SELECT {<Select>} \
CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
CONFIG.PCW_IRQ_F2P_INTR {1} \
CONFIG.PCW_MIO_0_DIRECTION {inout} \
CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_0_PULLUP {enabled} \
CONFIG.PCW_MIO_0_SLEW {slow} \
CONFIG.PCW_MIO_10_DIRECTION {inout} \
CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_10_PULLUP {enabled} \
CONFIG.PCW_MIO_10_SLEW {slow} \
CONFIG.PCW_MIO_11_DIRECTION {out} \
CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_11_PULLUP {enabled} \
CONFIG.PCW_MIO_11_SLEW {slow} \
CONFIG.PCW_MIO_12_DIRECTION {inout} \
CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_12_PULLUP {enabled} \
CONFIG.PCW_MIO_12_SLEW {slow} \
CONFIG.PCW_MIO_13_DIRECTION {inout} \
CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_13_PULLUP {enabled} \
CONFIG.PCW_MIO_13_SLEW {slow} \
CONFIG.PCW_MIO_14_DIRECTION {in} \
CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_14_PULLUP {enabled} \
CONFIG.PCW_MIO_14_SLEW {slow} \
CONFIG.PCW_MIO_15_DIRECTION {out} \
CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_15_PULLUP {enabled} \
CONFIG.PCW_MIO_15_SLEW {slow} \
CONFIG.PCW_MIO_16_DIRECTION {out} \
CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_16_PULLUP {disabled} \
CONFIG.PCW_MIO_16_SLEW {fast} \
CONFIG.PCW_MIO_17_DIRECTION {out} \
CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_17_PULLUP {disabled} \
CONFIG.PCW_MIO_17_SLEW {fast} \
CONFIG.PCW_MIO_18_DIRECTION {out} \
CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_18_PULLUP {disabled} \
CONFIG.PCW_MIO_18_SLEW {fast} \
CONFIG.PCW_MIO_19_DIRECTION {out} \
CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_19_PULLUP {disabled} \
CONFIG.PCW_MIO_19_SLEW {fast} \
CONFIG.PCW_MIO_1_DIRECTION {inout} \
CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_1_PULLUP {enabled} \
CONFIG.PCW_MIO_1_SLEW {slow} \
CONFIG.PCW_MIO_20_DIRECTION {out} \
CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_20_PULLUP {disabled} \
CONFIG.PCW_MIO_20_SLEW {fast} \
CONFIG.PCW_MIO_21_DIRECTION {out} \
CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_21_PULLUP {disabled} \
CONFIG.PCW_MIO_21_SLEW {fast} \
CONFIG.PCW_MIO_22_DIRECTION {in} \
CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_22_PULLUP {disabled} \
CONFIG.PCW_MIO_22_SLEW {fast} \
CONFIG.PCW_MIO_23_DIRECTION {in} \
CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_23_PULLUP {disabled} \
CONFIG.PCW_MIO_23_SLEW {fast} \
CONFIG.PCW_MIO_24_DIRECTION {in} \
CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_24_PULLUP {disabled} \
CONFIG.PCW_MIO_24_SLEW {fast} \
CONFIG.PCW_MIO_25_DIRECTION {in} \
CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_25_PULLUP {disabled} \
CONFIG.PCW_MIO_25_SLEW {fast} \
CONFIG.PCW_MIO_26_DIRECTION {in} \
CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_26_PULLUP {disabled} \
CONFIG.PCW_MIO_26_SLEW {fast} \
CONFIG.PCW_MIO_27_DIRECTION {in} \
CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_27_PULLUP {disabled} \
CONFIG.PCW_MIO_27_SLEW {fast} \
CONFIG.PCW_MIO_28_DIRECTION {inout} \
CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_28_PULLUP {enabled} \
CONFIG.PCW_MIO_28_SLEW {slow} \
CONFIG.PCW_MIO_29_DIRECTION {in} \
CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_29_PULLUP {enabled} \
CONFIG.PCW_MIO_29_SLEW {slow} \
CONFIG.PCW_MIO_2_DIRECTION {inout} \
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_2_PULLUP {disabled} \
CONFIG.PCW_MIO_2_SLEW {slow} \
CONFIG.PCW_MIO_30_DIRECTION {out} \
CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_30_PULLUP {enabled} \
CONFIG.PCW_MIO_30_SLEW {slow} \
CONFIG.PCW_MIO_31_DIRECTION {in} \
CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_31_PULLUP {enabled} \
CONFIG.PCW_MIO_31_SLEW {slow} \
CONFIG.PCW_MIO_32_DIRECTION {inout} \
CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_32_PULLUP {enabled} \
CONFIG.PCW_MIO_32_SLEW {slow} \
CONFIG.PCW_MIO_33_DIRECTION {inout} \
CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_33_PULLUP {enabled} \
CONFIG.PCW_MIO_33_SLEW {slow} \
CONFIG.PCW_MIO_34_DIRECTION {inout} \
CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_34_PULLUP {enabled} \
CONFIG.PCW_MIO_34_SLEW {slow} \
CONFIG.PCW_MIO_35_DIRECTION {inout} \
CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_35_PULLUP {enabled} \
CONFIG.PCW_MIO_35_SLEW {slow} \
CONFIG.PCW_MIO_36_DIRECTION {in} \
CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_36_PULLUP {enabled} \
CONFIG.PCW_MIO_36_SLEW {slow} \
CONFIG.PCW_MIO_37_DIRECTION {inout} \
CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_37_PULLUP {enabled} \
CONFIG.PCW_MIO_37_SLEW {slow} \
CONFIG.PCW_MIO_38_DIRECTION {inout} \
CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_38_PULLUP {enabled} \
CONFIG.PCW_MIO_38_SLEW {slow} \
CONFIG.PCW_MIO_39_DIRECTION {inout} \
CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_39_PULLUP {enabled} \
CONFIG.PCW_MIO_39_SLEW {slow} \
CONFIG.PCW_MIO_3_DIRECTION {inout} \
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_3_PULLUP {disabled} \
CONFIG.PCW_MIO_3_SLEW {slow} \
CONFIG.PCW_MIO_40_DIRECTION {inout} \
CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_40_PULLUP {enabled} \
CONFIG.PCW_MIO_40_SLEW {slow} \
CONFIG.PCW_MIO_41_DIRECTION {inout} \
CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_41_PULLUP {enabled} \
CONFIG.PCW_MIO_41_SLEW {slow} \
CONFIG.PCW_MIO_42_DIRECTION {inout} \
CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_42_PULLUP {enabled} \
CONFIG.PCW_MIO_42_SLEW {slow} \
CONFIG.PCW_MIO_43_DIRECTION {inout} \
CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_43_PULLUP {enabled} \
CONFIG.PCW_MIO_43_SLEW {slow} \
CONFIG.PCW_MIO_44_DIRECTION {inout} \
CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_44_PULLUP {enabled} \
CONFIG.PCW_MIO_44_SLEW {slow} \
CONFIG.PCW_MIO_45_DIRECTION {inout} \
CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_45_PULLUP {enabled} \
CONFIG.PCW_MIO_45_SLEW {slow} \
CONFIG.PCW_MIO_46_DIRECTION {inout} \
CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_46_PULLUP {enabled} \
CONFIG.PCW_MIO_46_SLEW {slow} \
CONFIG.PCW_MIO_47_DIRECTION {inout} \
CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_47_PULLUP {enabled} \
CONFIG.PCW_MIO_47_SLEW {slow} \
CONFIG.PCW_MIO_48_DIRECTION {out} \
CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_48_PULLUP {enabled} \
CONFIG.PCW_MIO_48_SLEW {slow} \
CONFIG.PCW_MIO_49_DIRECTION {in} \
CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_49_PULLUP {enabled} \
CONFIG.PCW_MIO_49_SLEW {slow} \
CONFIG.PCW_MIO_4_DIRECTION {inout} \
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_4_PULLUP {disabled} \
CONFIG.PCW_MIO_4_SLEW {slow} \
CONFIG.PCW_MIO_50_DIRECTION {inout} \
CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_50_PULLUP {enabled} \
CONFIG.PCW_MIO_50_SLEW {slow} \
CONFIG.PCW_MIO_51_DIRECTION {inout} \
CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_51_PULLUP {enabled} \
CONFIG.PCW_MIO_51_SLEW {slow} \
CONFIG.PCW_MIO_52_DIRECTION {out} \
CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_52_PULLUP {enabled} \
CONFIG.PCW_MIO_52_SLEW {slow} \
CONFIG.PCW_MIO_53_DIRECTION {inout} \
CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_53_PULLUP {enabled} \
CONFIG.PCW_MIO_53_SLEW {slow} \
CONFIG.PCW_MIO_5_DIRECTION {inout} \
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_5_PULLUP {disabled} \
CONFIG.PCW_MIO_5_SLEW {slow} \
CONFIG.PCW_MIO_6_DIRECTION {inout} \
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_6_PULLUP {disabled} \
CONFIG.PCW_MIO_6_SLEW {slow} \
CONFIG.PCW_MIO_7_DIRECTION {out} \
CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_7_PULLUP {disabled} \
CONFIG.PCW_MIO_7_SLEW {slow} \
CONFIG.PCW_MIO_8_DIRECTION {out} \
CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_8_PULLUP {disabled} \
CONFIG.PCW_MIO_8_SLEW {slow} \
CONFIG.PCW_MIO_9_DIRECTION {out} \
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_9_PULLUP {enabled} \
CONFIG.PCW_MIO_9_SLEW {slow} \
CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#USB Reset#GPIO#ENET Reset#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#I2C 0#I2C 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \
CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#reset#gpio[10]#reset#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#scl#sda#tx#rx#gpio[50]#gpio[51]#mdc#mdio} \
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_PJTAG_PJTAG_IO {<Select>} \
CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \
CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {10} \
CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1} \
CONFIG.PCW_SPI0_GRP_SS0_IO {EMIO} \
CONFIG.PCW_SPI0_GRP_SS1_ENABLE {1} \
CONFIG.PCW_SPI0_GRP_SS1_IO {EMIO} \
CONFIG.PCW_SPI0_GRP_SS2_ENABLE {1} \
CONFIG.PCW_SPI0_GRP_SS2_IO {EMIO} \
CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_SPI0_SPI0_IO {EMIO} \
CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1} \
CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO} \
CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1} \
CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO} \
CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1} \
CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \
CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_SPI1_SPI1_IO {EMIO} \
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {6} \
CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \
CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.096} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.102} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.100} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.090} \
CONFIG.PCW_UIPARAM_DDR_CL {7} \
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.054} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.040} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.041} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.010} \
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
CONFIG.PCW_USB0_RESET_ENABLE {1} \
CONFIG.PCW_USB0_RESET_IO {MIO 9} \
CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
CONFIG.PCW_USB1_RESET_ENABLE {0} \
CONFIG.PCW_USB_RESET_ENABLE {1} \
CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
CONFIG.PCW_USE_HIGH_OCM {1} \
CONFIG.PCW_USE_PS_SLCR_REGISTERS {1} \
CONFIG.PCW_USE_S_AXI_GP0 {0} \
CONFIG.PCW_USE_S_AXI_GP1 {0} \
CONFIG.PCW_USE_S_AXI_HP0 {0} \
CONFIG.PCW_USE_S_AXI_HP1 {1} \
CONFIG.PCW_USE_S_AXI_HP2 {1} \
CONFIG.PCW_USE_S_AXI_HP3 {0} \
] $processing_system7_0
# Create instance: xlconcat_0, and set properties
set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
set_property -dict [ list \
CONFIG.IN0_WIDTH {8} \
CONFIG.NUM_PORTS {9} \
] $xlconcat_0
# Create instance: xlslice_2, and set properties
set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ]
set_property -dict [ list \
CONFIG.DIN_FROM {7} \
CONFIG.DIN_TO {0} \
CONFIG.DIN_WIDTH {16} \
CONFIG.DOUT_WIDTH {8} \
] $xlslice_2
# Create interface connections
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports m_axi_xbar] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins axi_interconnect_0/M03_AXI] [get_bd_intf_pins dma/s_axi_tx_dmac]
connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports m_axi_pmu] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
connect_bd_intf_net -intf_net dma_M_AXI_RX_DMA [get_bd_intf_pins dma/M_AXI_RX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP1]
connect_bd_intf_net -intf_net dma_M_AXI_TX_DMA [get_bd_intf_pins dma/M_AXI_TX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP2]
connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_ports s_axis_dma] [get_bd_intf_pins dma/s_axis_dma]
connect_bd_intf_net -intf_net m_axis_dma_1 [get_bd_intf_ports m_axis_dma] [get_bd_intf_pins dma/m_axis_dma]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0] [get_bd_intf_pins processing_system7_0/GPIO_0]
connect_bd_intf_net -intf_net processing_system7_0_USBIND_0 [get_bd_intf_ports USBIND_0] [get_bd_intf_pins processing_system7_0/USBIND_0]
connect_bd_intf_net -intf_net s_axi_regfile_1 [get_bd_intf_pins axi_interconnect_0/M04_AXI] [get_bd_intf_pins dma/s_axi_regfile]
connect_bd_intf_net -intf_net s_axi_rx_dmac_1 [get_bd_intf_pins axi_interconnect_0/M02_AXI] [get_bd_intf_pins dma/s_axi_rx_dmac]
# Create port connections
connect_bd_net -net IRQ_F2P_1 [get_bd_ports IRQ_F2P] [get_bd_pins xlslice_2/Din]
connect_bd_net -net SPI0_MISO_I_1 [get_bd_ports SPI0_MISO_I] [get_bd_pins processing_system7_0/SPI0_MISO_I]
connect_bd_net -net SPI0_MOSI_I_1 [get_bd_ports SPI0_MOSI_I] [get_bd_pins processing_system7_0/SPI0_MOSI_I]
connect_bd_net -net SPI0_SCLK_I_1 [get_bd_ports SPI0_SCLK_I] [get_bd_pins processing_system7_0/SPI0_SCLK_I]
connect_bd_net -net SPI0_SS_I_1 [get_bd_ports SPI0_SS_I] [get_bd_pins processing_system7_0/SPI0_SS_I]
connect_bd_net -net SPI1_MISO_I_0_1 [get_bd_ports SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MISO_I]
connect_bd_net -net SPI1_MOSI_I_0_1 [get_bd_ports SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I]
connect_bd_net -net SPI1_SCLK_I_0_1 [get_bd_ports SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I]
connect_bd_net -net SPI1_SS_I_0_1 [get_bd_ports SPI1_SS_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
connect_bd_net -net S_AXI_GP0_ACLK_1 [get_bd_ports S_AXI_GP0_ACLK] [get_bd_pins axi_interconnect_0/ACLK]
connect_bd_net -net S_AXI_GP0_ARESETN_1 [get_bd_ports S_AXI_GP0_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN]
connect_bd_net -net bus_clk [get_bd_ports bus_clk] [get_bd_pins dma/bus_clk]
connect_bd_net -net bus_rstn [get_bd_ports bus_rstn] [get_bd_pins dma/bus_rstn]
connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins dma/clk40] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK]
connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins dma/clk40_rstn]
connect_bd_net -net ddr_vrn [get_bd_ports DDR_VRN] [get_bd_pins processing_system7_0/DDR_VRN]
connect_bd_net -net ddr_vrp [get_bd_ports DDR_VRP] [get_bd_pins processing_system7_0/DDR_VRP]
connect_bd_net -net dma_tx_irq [get_bd_pins dma/tx_irq] [get_bd_pins xlconcat_0/In2]
connect_bd_net -net mio [get_bd_ports MIO] [get_bd_pins processing_system7_0/MIO]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins processing_system7_0/FCLK_CLK0]
connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_ports FCLK_CLK1] [get_bd_pins processing_system7_0/FCLK_CLK1]
connect_bd_net -net processing_system7_0_FCLK_CLK2 [get_bd_ports FCLK_CLK2] [get_bd_pins processing_system7_0/FCLK_CLK2]
connect_bd_net -net processing_system7_0_FCLK_CLK3 [get_bd_ports FCLK_CLK3] [get_bd_pins processing_system7_0/FCLK_CLK3]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_ports FCLK_RESET0_N] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
connect_bd_net -net processing_system7_0_SPI0_MISO_O [get_bd_ports SPI0_MISO_O] [get_bd_pins processing_system7_0/SPI0_MISO_O]
connect_bd_net -net processing_system7_0_SPI0_MISO_T [get_bd_ports SPI0_MISO_T] [get_bd_pins processing_system7_0/SPI0_MISO_T]
connect_bd_net -net processing_system7_0_SPI0_MOSI_O [get_bd_ports SPI0_MOSI_O] [get_bd_pins processing_system7_0/SPI0_MOSI_O]
connect_bd_net -net processing_system7_0_SPI0_MOSI_T [get_bd_ports SPI0_MOSI_T] [get_bd_pins processing_system7_0/SPI0_MOSI_T]
connect_bd_net -net processing_system7_0_SPI0_SCLK_O [get_bd_ports SPI0_SCLK_O] [get_bd_pins processing_system7_0/SPI0_SCLK_O]
connect_bd_net -net processing_system7_0_SPI0_SCLK_T [get_bd_ports SPI0_SCLK_T] [get_bd_pins processing_system7_0/SPI0_SCLK_T]
connect_bd_net -net processing_system7_0_SPI0_SS1_O [get_bd_ports SPI0_SS1_O] [get_bd_pins processing_system7_0/SPI0_SS1_O]
connect_bd_net -net processing_system7_0_SPI0_SS2_O [get_bd_ports SPI0_SS2_O] [get_bd_pins processing_system7_0/SPI0_SS2_O]
connect_bd_net -net processing_system7_0_SPI0_SS_O [get_bd_ports SPI0_SS_O] [get_bd_pins processing_system7_0/SPI0_SS_O]
connect_bd_net -net processing_system7_0_SPI0_SS_T [get_bd_ports SPI0_SS_T] [get_bd_pins processing_system7_0/SPI0_SS_T]
connect_bd_net -net processing_system7_0_SPI1_MISO_O [get_bd_ports SPI1_MISO_O] [get_bd_pins processing_system7_0/SPI1_MISO_O]
connect_bd_net -net processing_system7_0_SPI1_MISO_T [get_bd_ports SPI1_MISO_T] [get_bd_pins processing_system7_0/SPI1_MISO_T]
connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports SPI1_MOSI_O] [get_bd_pins processing_system7_0/SPI1_MOSI_O]
connect_bd_net -net processing_system7_0_SPI1_MOSI_T [get_bd_ports SPI1_MOSI_T] [get_bd_pins processing_system7_0/SPI1_MOSI_T]
connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports SPI1_SCLK_O] [get_bd_pins processing_system7_0/SPI1_SCLK_O]
connect_bd_net -net processing_system7_0_SPI1_SCLK_T [get_bd_ports SPI1_SCLK_T] [get_bd_pins processing_system7_0/SPI1_SCLK_T]
connect_bd_net -net processing_system7_0_SPI1_SS1_O [get_bd_ports SPI1_SS1_O] [get_bd_pins processing_system7_0/SPI1_SS1_O]
connect_bd_net -net processing_system7_0_SPI1_SS2_O [get_bd_ports SPI1_SS2_O] [get_bd_pins processing_system7_0/SPI1_SS2_O]
connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports SPI1_SS_O] [get_bd_pins processing_system7_0/SPI1_SS_O]
connect_bd_net -net processing_system7_0_SPI1_SS_T [get_bd_ports SPI1_SS_T] [get_bd_pins processing_system7_0/SPI1_SS_T]
connect_bd_net -net ps_clk [get_bd_ports PS_CLK] [get_bd_pins processing_system7_0/PS_CLK]
connect_bd_net -net ps_porb [get_bd_ports PS_PORB] [get_bd_pins processing_system7_0/PS_PORB]
connect_bd_net -net ps_srstb [get_bd_ports PS_SRSTB] [get_bd_pins processing_system7_0/PS_SRSTB]
connect_bd_net -net rx_dma_irq [get_bd_pins dma/rx_irq] [get_bd_pins xlconcat_0/In1]
connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout]
connect_bd_net -net xlslice_2_Dout [get_bd_pins xlconcat_0/In0] [get_bd_pins xlslice_2/Dout]
# Create address segments
create_bd_addr_seg -range 0x00004000 -offset 0x40010000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_xbar/Reg] SEG_m_axi_xbar_Reg
create_bd_addr_seg -range 0x00001000 -offset 0x42080000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_regfile_0/S_AXI/regs] SEG_axi_regfile_0_regs
create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma0/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite
create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma1/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite1
create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma2/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite2
create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma3/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite3
create_bd_addr_seg -range 0x00010000 -offset 0x43C40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma4/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite4
create_bd_addr_seg -range 0x00010000 -offset 0x43CA0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_0/s_axi/axi_lite] SEG_axi_tx_dmac_0_axi_lite
create_bd_addr_seg -range 0x00010000 -offset 0x43CB0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_1/s_axi/axi_lite] SEG_axi_tx_dmac_1_axi_lite
create_bd_addr_seg -range 0x00010000 -offset 0x43CC0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_2/s_axi/axi_lite] SEG_axi_tx_dmac_2_axi_lite
create_bd_addr_seg -range 0x00010000 -offset 0x43CD0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_3/s_axi/axi_lite] SEG_axi_tx_dmac_3_axi_lite
create_bd_addr_seg -range 0x00010000 -offset 0x43CE0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_4/s_axi/axi_lite] SEG_axi_tx_dmac_4_axi_lite
create_bd_addr_seg -range 0x00004000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_pmu/Reg] SEG_m_axi_pmu_Reg
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_0/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_1/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_2/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_3/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_4/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma0/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma1/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma2/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma3/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma4/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM
# Restore current instance
current_bd_instance $oldCurInst
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/e31x/ip/e31x_ps_bd/ps7_init.c
+13335
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File diff suppressed because it is too large Load Diff
top/e31x/ip/e31x_ps_bd/ps7_init_gpl-sg1.c
+1087
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File diff suppressed because it is too large Load Diff
top/e31x/ip/e31x_ps_bd/ps7_init_gpl-sg3.c
+1087
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File diff suppressed because it is too large Load Diff
top/e31x/ip/e31x_ps_bd/ps7_init_gpl.c
+13326
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File diff suppressed because it is too large Load Diff
top/e31x/ip/fifo_4k_2clk/Makefile.inc
+15
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@@ -0,0 +1,15 @@
#
# Copyright 2014 Ettus Research
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci
IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \
fifo_4k_2clk.xci.out \
synth/fifo_4k_2clk.vhd \
)
$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci
$(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/e31x/ip/fifo_4k_2clk/fifo_4k_2clk.xci
+575
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@@ -0,0 +1,575 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>fifo_4k_2clk</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg484</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
top/e31x/ip/fifo_short_2clk/Makefile.inc
+15
View File
@@ -0,0 +1,15 @@
#
# Copyright 2014 Ettus Research
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci
IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \
fifo_short_2clk.xci.out \
synth/fifo_short_2clk.vhd \
)
$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci
$(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/e31x/ip/fifo_short_2clk/fifo_short_2clk.xci
+577
View File
@@ -0,0 +1,577 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>fifo_short_2clk</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_short_2clk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">31</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">30</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">72</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">72</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg484</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
top/e31x/ip/mig_7series_0/Makefile.inc
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#
# Copyright 2015 Ettus Research
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_MIG_7SERIES_0_SRCS = $(IP_BUILD_DIR)/mig_7series_0/mig_7series_0.xci
IP_MIG_7SERIES_0_OUTS = $(addprefix $(IP_BUILD_DIR)/mig_7series_0/, \
mig_7series_0.xci.out \
mig_7series_0/user_design/rtl/mig_7series_0.v \
mig_7series_0/user_design/rtl/mig_7series_0_mig.v \
)
IP_MIG_7SERIES_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/mig_7series_0/, \
mig_7series_0/example_design/rtl/example_top.v \
mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v \
mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_wrapper.v \
mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen_axi.v \
mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_data_gen_chk.v \
mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_tg.v \
)
IP_MIG_7SERIES_0_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/mig_7series_0/, \
mig_7series_0/example_design/sim/ddr3_model.sv \
mig_7series_0/example_design/sim/ddr3_model_parameters.vh \
)
$(IP_MIG_7SERIES_0_SRCS) $(IP_MIG_7SERIES_0_OUTS) : $(IP_DIR)/mig_7series_0/mig_7series_0.xci $(IP_DIR)/mig_7series_0/mig_*.prj
ln -fs mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/mig_7series_0/mig_a.prj # Hack: This won't allow parallel IP builds
$(call BUILD_VIVADO_IP,mig_7series_0,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
rm -f $(IP_DIR)/mig_7series_0/mig_a.prj
top/e31x/ip/mig_7series_0/mig_7series_0.xci
+2648
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top/e31x/ip/mig_7series_0/mig_xc7z020clg484-1.prj
+140
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<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>mig_7series_0</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7z020-clg484/-1</TargetFPGA>
<Version>4.0</Version>
<SystemClock>Single-Ended</SystemClock>
<ReferenceClock>No Buffer</ReferenceClock>
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>1</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<FPGADevice>
<selected>7z/xc7z020i-clg484</selected>
</FPGADevice>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice>
<TimePeriod>2500</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>100</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>800</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>16</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<BankMachineCnt>4</BankMachineCnt>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>15</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.5V</MemoryVoltage>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V15" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y16" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W16" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W18" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W17" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB15" SLEW="" name="ddr3_addr[14]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V14" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB16" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA16" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB17" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA17" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V17" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U17" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U16" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U15" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y14" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W13" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V13" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y13" SLEW="" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y15" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="W15" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB14" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V18" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA18" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T21" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA21" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB21" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB19" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB20" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y19" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA19" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U21" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T22" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U22" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W20" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W21" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U20" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V20" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA22" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB22" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="W22" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y21" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="V22" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y20" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U14" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA14" SLEW="" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="LVCMOS15" PADName="U19" SLEW="" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA13" SLEW="" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Clock>
<Pin PADName="Y18(MRCC_P)" Bank="33" name="sys_clk_i" />
</System_Clock>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="260" trp="13.75" tras="35" trcd="13.75" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >6</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Disable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>29</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>12</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>
top/e31x/ip/mig_7series_0/mig_xc7z020clg484-3.prj
+140
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<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>mig_7series_0</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7z020-clg484/-3</TargetFPGA>
<Version>4.0</Version>
<SystemClock>Single-Ended</SystemClock>
<ReferenceClock>No Buffer</ReferenceClock>
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>1</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<FPGADevice>
<selected>7z/xc7z020i-clg484</selected>
</FPGADevice>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice>
<TimePeriod>2500</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>100</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>800</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>16</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<BankMachineCnt>4</BankMachineCnt>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>15</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.5V</MemoryVoltage>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V15" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y16" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W16" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W18" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W17" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB15" SLEW="" name="ddr3_addr[14]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V14" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB16" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA16" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB17" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA17" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V17" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U17" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U16" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U15" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y14" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W13" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V13" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y13" SLEW="" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y15" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="W15" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB14" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V18" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA18" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T21" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA21" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB21" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB19" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB20" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y19" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA19" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U21" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T22" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U22" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W20" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W21" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U20" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V20" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA22" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB22" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="W22" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y21" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="V22" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="Y20" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U14" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA14" SLEW="" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="LVCMOS15" PADName="U19" SLEW="" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA13" SLEW="" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Clock>
<Pin PADName="Y18(MRCC_P)" Bank="33" name="sys_clk_i" />
</System_Clock>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="260" trp="13.75" tras="35" trcd="13.75" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >6</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Disable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>29</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>12</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>
top/e31x/ppsloop.v
+415
View File
@@ -0,0 +1,415 @@
//
// Copyright 2015 Ettus Research
//
`timescale 1ns / 1ps
module ppsloop(
input reset,
input xoclk, // 40 MHz from VCTCXO
input ppsgps,
input ppsext,
input [1:0] refsel,
output reg lpps,
output reg is10meg,
output reg ispps,
output reg reflck,
output plllck,// status of things
output sclk,
output mosi,
output sync_n,
input [15:0] dac_dflt
);
wire ppsref = (refsel==2'b00)?ppsgps:
(refsel==2'b11)?ppsext:
1'b0;
// reference pps to discilpline the VCTX|CXO to, from GPS or EXT in
wire clk_200M_o, clk;
BUFG x_clk_gen ( .I(clk_200M_o), .O(clk));
wire clk_40M;
wire n_pps = (refsel==2'b01) | (refsel==2'b10);
reg _npps, no_pps;
always @(posedge clk) { no_pps, _npps } <= { _npps, n_pps };
PLLE2_ADV #(.BANDWIDTH("OPTIMIZED"), .COMPENSATION("INTERNAL"),
.DIVCLK_DIVIDE(1),
.CLKFBOUT_MULT(30),
.CLKOUT0_DIVIDE(6),
.CLKOUT1_DIVIDE(30),
.CLKIN1_PERIOD(25.0)
)
clkgen (
.PWRDWN(1'b0), .RST(1'b0),
.CLKIN1(xoclk),
.CLKOUT0(clk_200M_o),
.CLKOUT1(clk_40M),
.LOCKED(plllck)
);
// state machine to manage reference detection and xo adjustment steps
reg [2:0] sstate, nxt_sstate;
localparam REFDET=3'b000;
localparam CFADJ=3'b001;
localparam SLEDGEA=3'b010;
localparam SLEDGEB=3'b011;
localparam FINEADJ=3'b100;
// state machine to manage lead-lag count
reg [1:0] llstate, nxt_llstate;
localparam READY=2'b00;
localparam COUNT=2'b01;
localparam DONE=2'b11;
localparam WAIT=2'b10;
/* Counter generating a local pps for the xo derived clock domains.
nxt_lcnt is manipulated by a state machine (sstate) to allow
quick re-alignment of the local pps rising edge with that of
the reference.
*/
reg [27:0] lcnt, nxt_lcnt;
wire recycle = (28'd199_999_999==lcnt); // sets the period, 1 sec
always @(posedge clk) begin
sstate <= nxt_sstate;
lcnt <= nxt_lcnt;
lpps <= lcnt > 28'd150_000_000; // ~25% duty cycle
end
/* Reference signal detection:
* Count the time interval between rising edges on the reference
* signal. The interval counter "rcnt" is restarted at rising edges
* of ppsref. "ppsref" could be either a pps signal, or a 10 MHz clock.
* Register "rlst" captures the value of rcnt at each rising edge.
* From this count value, we know the reference frequency.
*/
reg [27:0] rcnt, rlst;
reg signed [28:0] rdiff;
wire signed [28:0] srlst = { 1'b0, rlst }; // sign extended version of rlst
wire [27:0] nxt_rcnt;
reg rcnt_ovfl;
reg [3:0] ple; // pipeline from reference rising edge det.
wire valid_ref = is10meg | ispps;
/* If the reference is at 10 MHz, derive a reference pps using a counter
* to feed the frequency control logic. To detect a 0.5 ppm deviation
* on a 10 MHz signal using counters requires the better part of a second
* anyway, so samples at a 1 Hz rate are appropriate. This allows much of
* the same logic to be used for pps or 10 Mhz references.
*/
reg [23:0] tcnt;
reg tpps;
wire [23:0] nxt_tcnt = (~is10meg | tcnt==24'd9999999) ? 24'b0 : tcnt+1'b1;
always @(posedge ppsref) begin
/* note this is clocked by the reference signal and is not useful when
* the reference is a pps.
*/
tcnt <= nxt_tcnt;
tpps <= (tcnt>24'd7499999);
end
/* The reference needs to be synchronized into the local clock domain,
* and while the local 'pps' is generated synchronously within this
* domain, it gets passed through identical stages to maintain
* the time relationship between detected rising edges.
*/
reg [2:0] refsmp;
reg [2:0] tsmp;
reg [2:0] xosmp;
always @(posedge clk) begin
// apply same sync delay to all pps flavors
refsmp <= { refsmp[1:0], ppsref};
tsmp <= { tsmp[1:0], tpps};
xosmp <= { xosmp[1:0], lpps };
end
wire rising_r = (refsmp[2:1]==2'b01);
wire rising_t = (tsmp[2:1]==2'b01);
wire rising_ref = is10meg ? rising_t : rising_r;
wire rising_xo = (xosmp[2:1]==2'b01);
wire lead = rising_xo & ~rising_ref;
wire lag = ~rising_xo & rising_ref;
wire trig = rising_xo ^ rising_ref;
wire dtrig = rising_xo & rising_ref;
wire untrig = rising_xo | rising_ref;
wire llrdy = (is10meg ? ~tsmp[2] : ~refsmp[2]) & ~xosmp[2];
wire rhigh = is10meg ? tsmp[1] : refsmp[1];
reg [5:0] pcnt;
reg pcnt_ovfl;
wire [5:0] nxt_pcnt = (rising_r | pcnt_ovfl) ? 6'b0 : pcnt+1'b1;
always @(posedge clk) begin
pcnt <= nxt_pcnt;
if (rcnt_ovfl)
is10meg <= 1'b0;
else if (pcnt == 6'b111111) begin
pcnt_ovfl <= 1'b1;
is10meg <= 1'b0;
end
else if (rising_r) begin
is10meg <= (pcnt > 6'd16) & (pcnt < 6'd24);
pcnt_ovfl <= 1'b0;
end
end
reg rr;
assign nxt_rcnt = rr ? 28'b0 : rcnt+1'b1;
always @(posedge clk) begin
rr <= rising_ref;
ple[3:0] <= {ple[2:0],rising_ref & valid_ref};
rcnt <= nxt_rcnt;
// set the overflow flag if no reference edge is detected and
// hold it asserted until an edge does arrive. This allows clearing of
// the other flags, even if there is no reference.
if (rcnt==28'b1111111111111111111111111111)
rcnt_ovfl <= 1'b1;
else if (rr)
rcnt_ovfl <= 1'b0;
if (rr) begin
// a rising edge arrived, grab the count and compare to bounds
rlst <= rcnt;
end
if (rr | rcnt_ovfl) begin
ispps <= ~is10meg & ~rcnt_ovfl & (rcnt > 28'd199997000) & (rcnt < 200003000);
/* reference frequency detect limits:
* 10M sampled with 200M should be 20 cycles, 16-24 provides xtra margin
* to allow for tolerances and possibly sampling at jittery edges
* allow +- 15 ppm on a pps signal
*/
end
end
reg signed [27:0] coarse;
reg [15:0] dacv = 16'd32767; // power-on default mid-scale
wire signed [16:0] sdacv = { 1'b0, dacv};
/* to exit coarse adjustment, the frequency error shall be small for
* several cycles
*/
reg esmall;
reg [2:0] es;
reg pr;
/* The xo can be on-frequency while the rising edges are still
* out-of-phase, so a phase detector is also required. The
* counter "llcnt" accumulates how many ticks local pps leads
* or lags the reference pps . The range of this counter
* need not be as large as "rcnt". The count increments
* or decrements based upon which signal has a rising edge first,
* and the count is halted when the other rising edge occurs.
* Both signals are required to transition back to the low state
* to re-arm the detection state machine.
*/
reg llcntena;
reg lead_lagn;
reg signed [11:0] llcnt, nxt_llcnt;
wire signed [11:0] incr = lead_lagn ? -12'sd1 : 12'sd1; // -1 lead, +1 lag
reg [3:0] llsmall;
reg llovfl;
reg [2:0] refs1, refs0;
reg refchanged;
reg refinternal;
always @(posedge clk) begin
refs1 <= { refs1[1:0], refsel[1] };
refs0 <= { refs0[1:0], refsel[0] };
refchanged <= { refs1[2], refs0[2] } != { refs1[1], refs0[1] };
refinternal <= refs1[2] ^ refs0[2]; // not gps or external
// compute how far off the expected period we are
if (ple[1]) begin
rdiff <= srlst-29'd199999999;
end
// compute an adjustment for the dac
if (ple[2]) begin
// if rdiff is (+), the xo is fast
// include a bit of gain for quick adjustment
// an approximate gain was initially determined by 'theory' using
// the xo tuning sensitivity, and was find-tuned 'by hand'
// by observing the loop behaviour (with rdiff instrumented and
// pps signals connected out to an oscilloscope).
coarse <= sdacv - (rdiff <<< 3);
end
// determine when the period error is small
if (ple[2] | rcnt_ovfl) begin
es <= { es[1:0], (rdiff<29'sd8 && rdiff>-29'sd8) };
esmall <= valid_ref & ~rcnt_ovfl & (es[2:0] == 3'b111);
end
else if (sstate==REFDET) begin
es <= 3'b0;
esmall <= 1'b0;
end
// assign the dac value when doing coarse-adjustment
// in the fine-adjust phaase, the PI control filtering takes over
if (ple[3] & (sstate==CFADJ)) begin
dacv <= coarse[15:0];
end
else if (sstate==REFDET) begin
dacv <= 16'd32767; // center the DAC
end
end
always @(*) begin
nxt_sstate=sstate;
pr = 1'b0;
nxt_lcnt = recycle ? 26'd0 : lcnt + 1'b1;
case (sstate)
REFDET: begin // determine reference type
pr = 1'b0;
if (valid_ref) nxt_sstate = CFADJ;
end
CFADJ: begin // coarse freqency adjustment
pr = 1'b1;
if (esmall) nxt_sstate = SLEDGEA;
end
SLEDGEA: begin // ensure local pps is low and wait for a ref edge
pr = 1'b1; // preload the integrator
if (rhigh) nxt_sstate = SLEDGEB;
end
SLEDGEB: begin // force local pps rising edge to match reference
nxt_lcnt = 26'd0;
pr = 1'b1; // preload the integrator
if(rhigh) begin
nxt_lcnt = 28'd149_999_998; // force rising edge in a couple cycles
nxt_sstate = FINEADJ;
end
end
FINEADJ: begin // wide-ish bandwidth PI control
if (~valid_ref | llovfl) nxt_sstate = REFDET;
end
default: begin
nxt_sstate = REFDET;
end
endcase
// overriding conditions:
if (refinternal | refchanged | rcnt_ovfl ) nxt_sstate = REFDET;
end
reg llsena;
always @(posedge clk) begin
llstate <= nxt_llstate;
if (llcntena) llcnt <= nxt_llcnt;
if (llstate==READY) lead_lagn <= lead;
if (llsena) llsmall <= { (llsmall[2:0] == 3'b111), llsmall[1:0],
(llcnt < 12'sd3)&(llcnt > -12'sd3)};
if (llcntena) llovfl <= (llcnt>12'sd1800) | (llcnt< -12'sd1800);
end
reg ppsfltena;
always @(*) begin
// values to hold by default:
nxt_llstate = llstate;
llcntena=1'b0;
nxt_llcnt=llcnt;
ppsfltena = 1'b0;
llsena = 1'b0;
case (llstate)
READY: begin
nxt_llcnt=12'b0;
if (trig | dtrig) begin
nxt_llstate = trig ? COUNT : DONE;
llcntena=1'b1;
// even if dtrig, set llcnt to 0 to feed the filter pipe
end
end
COUNT: begin
if (untrig) begin // the second edge arrived
nxt_llstate = DONE;
end
else begin
llcntena=1'b1;
nxt_llcnt=llcnt+incr;
end
end
DONE: begin
nxt_llstate = WAIT;
ppsfltena = 1'b1;
end
WAIT: begin
if (llrdy) begin
nxt_llstate = READY;
llsena = 1'b1;
end
end
endcase
if (sstate==REFDET) begin
nxt_llstate = READY;
llcntena=1'b0;
ppsfltena = 1'b0;
llsena = 1'b0;
end
end
reg[15:0] daco;
reg [1:0] enchain=2'b00;
always @(posedge clk) enchain <= { enchain[1:0], ppsfltena & (enchain==2'b00) };
reg signed [23:0] integ;
reg signed [23:0] prop;
wire signed [23:0] nxt_integ = integ + (llcnt <<< 6);
wire signed [23:0] nxt_prop = (llcnt <<< 7);
wire signed [23:0] eff = integ + prop;
wire urng = eff[23], orng = eff[23:22]==2'b01;
reg erng;
/* The values for proportional and integral gain terms were originally
* estimated using a model that accounted for the xo tuning sensitivity.
* When implemented, the loop dynamics observed differed significantly
* from model results, probably as a result of the Xilinx PLL
* (which was not modelled) being present in the loop. The gain values
* were find-tuned 'by hand' by observing the loop behaviour (with llcnt
* instrumented) and pps signals connected out to an oscilloscope).
*/
always @(posedge clk) begin
if (no_pps) begin
daco <= dac_dflt;
end
else if (pr) begin
integ <= { 2'b00, dacv, 6'b0 }; // precharge the accumulator
daco <= dacv;
end
else begin
if (enchain[0]) begin
integ <= nxt_integ;
prop <= nxt_prop;
end
if (enchain[1]) begin
daco <= eff[21:6];
erng <= urng | orng;
end
end
end
wire fadj= (sstate==FINEADJ);
always @(posedge clk) begin
reflck <= refinternal | fadj;
end
ad5662_auto_spi dac
(
.clk(clk),
.dat(daco),
.sclk(sclk),
.mosi(mosi),
.sync_n(sync_n)
);
endmodule
top/e31x/setupenv.sh
+11
View File
@@ -0,0 +1,11 @@
#!/bin/bash
VIVADO_VER=2019.1
DISPLAY_NAME="USRP-E31x"
REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)
declare -A PRODUCT_ID_MAP
PRODUCT_ID_MAP["E310_SG1"]="zynq/xc7z020/clg484/-1"
PRODUCT_ID_MAP["E310_SG3"]="zynq/xc7z020/clg484/-3"
source $REPO_BASE_PATH/tools/scripts/setupenv_base.sh
top/e31x/sim/dram_test/Makefile
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#
# Copyright 2015 Ettus Research LLC
#
#-------------------------------------------------
# Top-of-Makefile
#-------------------------------------------------
# Define BASE_DIR to point to the "top" dir
BASE_DIR = $(abspath ../../..)
# Include viv_sim_preample after defining BASE_DIR
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
#-------------------------------------------------
# Design Specific
#-------------------------------------------------
# Define part using PART_ID (<device>/<package>/<speedgrade>)
ARCH = zynq
PART_ID= xc7z020/clg484/-1
# Include makefiles and sources for the DUT and its dependencies
include $(BASE_DIR)/../lib/fifo/Makefile.srcs
include $(BASE_DIR)/../lib/axi/Makefile.srcs
include $(BASE_DIR)/../lib/control/Makefile.srcs
DESIGN_SRCS = $(abspath \
$(FIFO_SRCS) \
$(AXI_SRCS) \
$(CONTROL_LIB_SRCS) \
)
#-------------------------------------------------
# IP Specific
#-------------------------------------------------
# If simulation contains IP, define the IP_DIR and point
# it to the base level IP directory
IP_DIR = ../../ip
# Include makefiles and sources for all IP components
# *after* defining the IP_DIR
include $(IP_DIR)/mig_7series_0/Makefile.inc
DESIGN_SRCS += $(abspath \
$(IP_MIG_7SERIES_0_SRCS) \
)
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
SIM_TOP = dram_test_tb
SIM_SRCS = \
$(abspath dram_test_tb.sv) \
$(IP_MIG_7SERIES_0_SIM_OUTS) \
$(IP_MIG_7SERIES_TG_SRCS) \
$(SIM_GENERAL_SRCS) \
$(SIM_AXI_SRCS)
#-------------------------------------------------
# Bottom-of-Makefile
#-------------------------------------------------
# Include all simulator specific makefiles here
# Each should define a unique target to simulate
# e.g. xsim, vsim, etc and a common "clean" target
include $(BASE_DIR)/../tools/make/viv_simulator.mak
top/e31x/sim/dram_test/dram_test_tb.sv
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//
// Copyright 2016 Ettus Research
//
`timescale 1ns/1ps
`define SIM_TIMEOUT_US 10000
`define NS_PER_TICK 1
`define NUM_TEST_CASES 3
`define SIM_RUNTIME_US 100
`include "sim_clks_rsts.vh"
`include "sim_exec_report.vh"
module dram_test_tb();
`TEST_BENCH_INIT("dram_test_tb",`NUM_TEST_CASES,`NS_PER_TICK)
// Define all clocks and resets
`DEFINE_CLK(sys_clk, 10, 50) //100MHz sys_clk to generate DDR3 clocking
`DEFINE_CLK(ref_clk, 5, 50) //200MHz ref_clk to generate DDR3 clocking
`DEFINE_RESET(sys_rst, 0, 250000) //100ns for GSR to deassert
// Initialize DUT
wire calib_complete;
wire [15:0] ddr3_dq; // Data pins. Input for Reads; Output for Writes.
wire [1:0] ddr3_dqs_n; // Data Strobes. Input for Reads; Output for Writes.
wire [1:0] ddr3_dqs_p;
wire [14:0] ddr3_addr; // Address
wire [2:0] ddr3_ba; // Bank Address
wire ddr3_ras_n; // Row Address Strobe.
wire ddr3_cas_n; // Column address select
wire ddr3_we_n; // Write Enable
wire ddr3_reset_n; // SDRAM reset pin.
wire [0:0] ddr3_ck_p; // Differential clock
wire [0:0] ddr3_ck_n;
wire [0:0] ddr3_cke; // Clock Enable
wire [0:0] ddr3_cs_n; // Chip Select
wire [3:0] ddr3_dm; // Data Mask [3] = UDM.U26; [2] = LDM.U26;
wire [0:0] ddr3_odt; // On-Die termination enable.
ddr3_model #(
.DEBUG(1) //Disable verbose prints
) sdram_i0 (
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p),
.ck_n (ddr3_ck_n),
.cke (ddr3_cke),
.cs_n (1'b0),
.ras_n (ddr3_ras_n),
.cas_n (ddr3_cas_n),
.we_n (ddr3_we_n),
.dm_tdqs (ddr3_dm[1:0]),
.ba (ddr3_ba),
.addr (ddr3_addr),
.dq (ddr3_dq[15:0]),
.dqs (ddr3_dqs_p[1:0]),
.dqs_n (ddr3_dqs_n[1:0]),
.tdqs_n (), // Unused on x16
.odt (ddr3_odt)
);
example_top inst_example_top
(
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_we_n (ddr3_we_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_cke (ddr3_cke),
.ddr3_dm (ddr3_dm),
.ddr3_odt (ddr3_odt),
.sys_clk_i (sys_clk),
.clk_ref_i (ref_clk),
.tg_compare_error (tg_compare_error),
.init_calib_complete (calib_complete),
.sys_rst (sys_rst)
);
//
//Make sure we catch the error condition
//
reg tg_compare_error_reg;
always @ (posedge sys_clk)
if (sys_rst)
tg_compare_error_reg = 1'b0;
else
tg_compare_error_reg = tg_compare_error | tg_compare_error_reg;
//------------------------------------------
//Main thread for testbench execution
//------------------------------------------
initial begin : tb_main
`TEST_CASE_START("Wait for reset");
while (sys_rst) @(posedge sys_clk);
`TEST_CASE_DONE((~sys_rst));
repeat (200) @(posedge sys_clk);
`TEST_CASE_START("Wait for initial calibration to complete");
while (calib_complete !== 1'b1) @(posedge sys_clk);
`TEST_CASE_DONE(calib_complete);
`TEST_CASE_START("Run for a while, then check for error");
repeat (2_000_000) @(posedge sys_clk);
`ASSERT_ERROR(tg_compare_error_reg == 1'b0, "Test generator reported error");
`TEST_CASE_DONE(1'b1);
`TEST_BENCH_DONE;
end
endmodule
top/e31x/sim/e310_io_tb/Makefile
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#
# Copyright 2015 Ettus Research LLC
#
#-------------------------------------------------
# Top-of-Makefile
#-------------------------------------------------
# Define BASE_DIR to point to the "top" dir
BASE_DIR = $(abspath ../../..)
# Include viv_sim_preample after defining BASE_DIR
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
#-------------------------------------------------
# Design Specific
#-------------------------------------------------
# Define part using PART_ID (<device>/<package>/<speedgrade>)
ARCH = zynq
PART_ID= xc7z020/clg484/-1
DESIGN_SRCS = $(abspath ../../e310_io.v) \
$(abspath $(addprefix $(BASE_DIR)/../lib/control/, \
synchronizer.v \
synchronizer_impl.v))
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
SIM_TOP = e310_io_tb
SIM_SRCS = \
$(abspath e310_io_tb.sv)
#-------------------------------------------------
# Bottom-of-Makefile
#-------------------------------------------------
# Include all simulator specific makefiles here
# Each should define a unique target to simulate
# e.g. xsim, vsim, etc and a common "clean" target
include $(BASE_DIR)/../tools/make/viv_simulator.mak
top/e31x/sim/e310_io_tb/e310_io_tb.sv
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//
// Copyright 2015 Ettus Research
//
// Test bench for E310 I/O interface to AD9361.
`timescale 1ns/1ps
`define SIM_TIMEOUT_US 20
`define NS_PER_TICK 1
`define NUM_TEST_CASES 6
`include "sim_clks_rsts.vh"
`include "sim_exec_report.vh"
module e310_io_tb();
`TEST_BENCH_INIT("e310_io_tb",`NUM_TEST_CASES,`NS_PER_TICK)
// Define all clocks and resets
`DEFINE_CLK(rx_clk, 16.27, 50) // ~61.44 MHz clock from AD9361
`DEFINE_RESET(areset, 0, 100) // 100ns reset
reg mimo;
wire radio_clk, radio_rst;
wire [11:0] rx_i0, rx_i1, rx_q0, rx_q1;
wire rx_stb;
reg [11:0] tx_i0, tx_i1, tx_q0, tx_q1;
wire tx_stb;
reg rx_frame;
reg [11:0] rx_data;
wire tx_clk;
wire tx_frame;
wire [11:0] tx_data;
e310_io e310_io (
.areset(areset),
.mimo(mimo),
.radio_clk(radio_clk),
.radio_rst(radio_rst),
.rx_i0(rx_i0),
.rx_q0(rx_q0),
.rx_i1(rx_i1),
.rx_q1(rx_q1),
.rx_stb(rx_stb),
.tx_i0(tx_i0),
.tx_q0(tx_q0),
.tx_i1(tx_i1),
.tx_q1(tx_q1),
.tx_stb(tx_stb),
.rx_clk(rx_clk),
.rx_frame(rx_frame),
.rx_data(rx_data),
.tx_clk(tx_clk),
.tx_frame(tx_frame),
.tx_data(tx_data));
/********************************************************
** Test Bench
********************************************************/
initial begin : tb_main
mimo <= 1'b0;
tx_i0 <= 'd0;
tx_q0 <= 'd0;
tx_i1 <= 'd0;
tx_q1 <= 'd0;
rx_data <= 'd0;
rx_frame <= 1'b0;
`TEST_CASE_START("Wait for reset");
while (areset) @(posedge radio_clk);
`TEST_CASE_DONE((~areset));
repeat (10) @(posedge radio_clk);
`TEST_CASE_START("Test RX channel 0,1");
mimo <= 1'b0;
rx_data <= 'd0;
repeat (10) @(posedge radio_clk);
fork
begin
for (int i = 1; i < 64; i = i + 2) begin
@(posedge radio_clk);
rx_frame <= 1'b1;
rx_data <= i;
@(negedge radio_clk);
rx_frame <= 1'b0;
rx_data <= i+1;
end
end
begin
while ({rx_i0, rx_q0} == 24'd0) @(posedge radio_clk);
for (int i = 1; i < 64; i = i + 2) begin
// RX should be replicated across both ports
`ASSERT_ERROR(rx_i0 == i, "RX0 I incorrect!");
`ASSERT_ERROR(rx_q0 == i+1, "RX0 Q incorrect!");
`ASSERT_ERROR(rx_i1 == i, "RX1 I incorrect!");
`ASSERT_ERROR(rx_q1 == i+1, "RX1 Q incorrect!");
@(posedge radio_clk);
end
end
join
`TEST_CASE_DONE(1);
`TEST_CASE_START("Test RX channels 0 & 1 (MIMO mode)");
mimo <= 1'b1;
rx_frame <= 1'b0;
rx_data <= 'd0;
repeat (10) @(posedge radio_clk);
fork
begin
for (int i = 1; i < 64; i = i + 2) begin
@(posedge radio_clk);
rx_frame <= ~rx_frame;
rx_data <= i;
@(negedge radio_clk);
rx_data <= i+1;
end
end
begin
while ({rx_i0, rx_q0} == 24'd0) @(posedge radio_clk);
for (int i = 1; i < 32; i = i + 4) begin
// RX should be replicated across both ports
`ASSERT_ERROR(rx_i0 == i, "RX0 I incorrect!");
`ASSERT_ERROR(rx_q0 == i+1, "RX0 Q incorrect!");
@(posedge radio_clk);
`ASSERT_ERROR(rx_i1 == i+2, "RX1 I incorrect!");
`ASSERT_ERROR(rx_q1 == i+3, "RX1 Q incorrect!");
@(posedge radio_clk);
end
end
join
`TEST_CASE_DONE(1);
`TEST_CASE_START("Test TX channel 0");
mimo <= 1'b0;
tx_i0 <= 'd0;
tx_q0 <= 'd0;
tx_i1 <= 'd0;
tx_q1 <= 'd0;
repeat (10) @(posedge radio_clk);
// TX0
fork
begin
for (int i = 1; i < 64; i = i + 2) begin
tx_i0 <= i;
tx_q0 <= i+1;
@(posedge radio_clk);
end
end
begin
while (tx_data == 12'd0) @(posedge tx_clk);
for (int i = 1; i < 64; i = i + 2) begin
// RX should be replicated across both ports
`ASSERT_ERROR(tx_data == i, "TX0 I data incorrect!");
`ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
@(negedge tx_clk);
`ASSERT_ERROR(tx_data == i+1, "TX0 Q data incorrect!");
`ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
@(posedge tx_clk);
end
end
join
`TEST_CASE_DONE(1);
`TEST_CASE_START("Test TX channel 1");
mimo <= 1'b0;
tx_i0 <= 'd0;
tx_q0 <= 'd0;
tx_i1 <= 'd0;
tx_q1 <= 'd0;
repeat (10) @(posedge radio_clk);
fork
begin
for (int i = 1; i < 64; i = i + 2) begin
tx_i1 <= i;
tx_q1 <= i+1;
@(posedge radio_clk);
end
end
begin
while (tx_data == 12'd0) @(posedge tx_clk);
for (int i = 1; i < 64; i = i + 2) begin
`ASSERT_ERROR(tx_data == i, "TX1 I data incorrect!");
`ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
@(negedge tx_clk);
`ASSERT_ERROR(tx_data == i+1, "TX1 Q data incorrect!");
`ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
@(posedge tx_clk);
end
end
join
`TEST_CASE_DONE(1);
`TEST_CASE_START("Test TX channel 0 & 1 (MIMO)");
mimo <= 1'b1;
tx_i0 <= 'd0;
tx_q0 <= 'd0;
tx_i1 <= 'd0;
tx_q1 <= 'd0;
repeat (10) @(posedge radio_clk);
fork
begin
for (int i = 1; i < 32; i = i + 4) begin
tx_i0 <= i;
tx_q0 <= i+1;
tx_i1 <= i+2;
tx_q1 <= i+3;
@(posedge radio_clk);
while (tx_stb) @(posedge radio_clk);
end
end
begin
while (tx_data == 12'd0) @(posedge tx_clk);
for (int i = 1; i < 32; i = i + 4) begin
`ASSERT_ERROR(tx_data == i, "TX0 I data incorrect!");
`ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
@(negedge tx_clk);
`ASSERT_ERROR(tx_data == i+1, "TX0 Q data incorrect!");
`ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect");
@(posedge tx_clk);
`ASSERT_ERROR(tx_data == i+2, "TX1 I data incorrect!");
`ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
@(negedge tx_clk);
`ASSERT_ERROR(tx_data == i+3, "TX1 Q data incorrect!");
`ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect");
@(posedge tx_clk);
end
end
join
`TEST_CASE_DONE(1);
`TEST_BENCH_DONE;
end
endmodule
top/e31x/sim/e3x0/catcap_ddr_cmos/catcap_tb.build
Executable
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#!/bin/sh
rm -rf isim*
rm -rf catcap_tb
rm -rf fuse*
\
# --sourcelibdir ../../models \
vlogcomp \
--sourcelibext .v \
--sourcelibdir ../../../top/e300/coregen \
--sourcelibdir ../../control_lib \
--sourcelibdir ../../../top/e300/ \
--sourcelibdir $XILINX/verilog/src \
--sourcelibdir $XILINX/verilog/src/unisims \
--work work \
catcap_tb.v
fuse -o catcap_tb catcap_tb
top/e31x/sim/e3x0/catcap_ddr_cmos/catcap_tb.v
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//
// Copyright 2014 Ettus Research, a National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
`timescale 1ns/1ps
module catcap_tb();
wire GSR, GTS;
glbl glbl( );
reg clk = 0;
reg ddrclk = 0;
reg reset = 1;
always #100 clk = ~clk;
always @(negedge clk) ddrclk <= ~ddrclk;
initial $dumpfile("catcap_tb.vcd");
initial $dumpvars(0,catcap_tb);
wire [11:0] i0 = {4'hA,count};
wire [11:0] q0 = {4'hB,count};
wire [11:0] i1 = {4'hC,count};
wire [11:0] q1 = {4'hD,count};
reg mimo;
reg [11:0] pins;
reg frame;
reg [7:0] count;
initial
begin
#1000 reset = 0;
MIMO_BURST(4);
MIMO_BURST(5);
BURST(4);
BURST(5);
#2000;
$finish;
end
task BURST;
input [7:0] len;
begin
frame <= 0;
@(posedge clk);
@(posedge clk);
mimo <= 0;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge ddrclk);
count <= 0;
repeat(len)
begin
@(posedge clk);
pins <= i0;
frame <= 1;
@(posedge clk);
pins <= q0;
frame <= 0;
count <= count + 1;
end
end
endtask // BURST
task MIMO_BURST;
input [7:0] len;
begin
frame <= 0;
@(posedge clk);
@(posedge clk);
mimo <= 1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge ddrclk);
count <= 0;
repeat(len)
begin
@(posedge clk);
pins <= i0;
frame <= 1;
@(posedge clk);
pins <= q0;
@(posedge clk);
pins <= i1;
frame <= 0;
@(posedge clk);
pins <= q1;
count <= count + 1;
end
@(posedge clk);
@(posedge clk);
end
endtask // MIMO_BURST
wire rx_clk, rx_strobe;
wire [11:0] i0o,i1o,q0o,q1o;
catcap_ddr_cmos catcap
(.data_clk(ddrclk),
.reset(reset),
.mimo(mimo),
.rx_frame(frame),
.rx_d(pins),
.rx_clk(rx_clk),
.rx_strobe(rx_strobe),
.i0(i0o),.q0(q0o),
.i1(i1o),.q1(q1o));
endmodule // hb_chain_tb
top/e31x/sim/e3x0/catgen_ddr_cmos/catgen_tb.build
Executable
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#!/bin/sh
rm -rf isim*
rm -rf catgen_tb
rm -rf fuse*
\
# --sourcelibdir ../../models \
vlogcomp \
--sourcelibext .v \
--sourcelibdir ../../../top/e300/coregen \
--sourcelibdir ../../control_lib \
--sourcelibdir ../../../top/e300 \
--sourcelibdir $XILINX/verilog/src \
--sourcelibdir $XILINX/verilog/src/unisims \
--work work \
catgen_tb.v
fuse -o catgen_tb catgen_tb
top/e31x/sim/e3x0/catgen_ddr_cmos/catgen_tb.v
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//
// Copyright 2014 Ettus Research, a National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
`timescale 1ns/1ps
module catgen_tb();
wire GSR, GTS;
glbl glbl( );
reg clk = 0;
reg reset = 1;
wire ddrclk;
always #100 clk = ~clk;
initial $dumpfile("catgen_tb.vcd");
initial $dumpvars(0,catgen_tb);
wire [11:0] pins;
wire frame;
reg mimo;
reg [7:0] count;
reg tx_strobe;
wire [11:0] i0 = {4'hA,count};
wire [11:0] q0 = {4'hB,count};
wire [11:0] i1 = {4'hC,count};
wire [11:0] q1 = {4'hD,count};
initial
begin
#1000 reset = 0;
BURST(4);
BURST(5);
MIMO_BURST(4);
MIMO_BURST(5);
#2000;
$finish;
end
task BURST;
input [7:0] len;
begin
tx_strobe <= 0;
mimo <= 0;
count <= 0;
@(posedge clk);
@(posedge clk);
repeat(len)
begin
tx_strobe <= 1;
@(posedge clk);
count <= count + 1;
end
tx_strobe <= 0;
@(posedge clk);
@(posedge clk);
@(posedge clk);
end
endtask // BURST
task MIMO_BURST;
input [7:0] len;
begin
tx_strobe <= 0;
mimo <= 1;
count <= 0;
@(posedge clk);
@(posedge clk);
repeat(len)
begin
tx_strobe <= 1;
@(posedge clk);
tx_strobe <= 0;
@(posedge clk);
count <= count + 1;
end
tx_strobe <= 0;
@(posedge clk);
@(posedge clk);
@(posedge clk);
end
endtask // BURST
catgen_ddr_cmos catgen
(.data_clk(ddrclk),
.reset(reset),
.mimo(mimo),
.tx_frame(frame),
.tx_d(pins),
.tx_clk(clk),
.tx_strobe(tx_strobe),
.i0(i0),.q0(q0),
.i1(i1),.q1(q1));
endmodule // hb_chain_tb
top/e31x/spi_slave.v
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//
// Copyright 2015 Ettus Research LLC
//
`ifndef LOG2
`define LOG2(N) (\
N < 2 ? 0 : \
N < 4 ? 1 : \
N < 8 ? 2 : \
N < 16 ? 3 : \
N < 32 ? 4 : \
N < 64 ? 5 : \
N < 128 ? 6 : \
N < 256 ? 7 : \
N < 512 ? 8 : \
N < 1024 ? 9 : \
10)
`endif
module spi_slave
#(
parameter DEPTH = 64
)
(
// sys connect
input clk,
input rst,
// spi slave port
input ss,
input mosi,
output miso,
input sck,
// parallel data io port
output parallel_stb,
input [DEPTH-1:0] parallel_din,
output [DEPTH-1:0] parallel_dout
);
reg mosi_d, mosi_q;
reg ss_d, ss_q;
reg sck_d, sck_q;
reg sck_old_d, sck_old_q;
reg miso_d, miso_q;
reg [DEPTH-1:0] data_d, data_q;
reg parallel_stb_d, parallel_stb_q;
reg [`LOG2(DEPTH)-1:0] bit_ct_d, bit_ct_q;
reg [DEPTH-1:0] parallel_dout_d, parallel_dout_q;
assign miso = miso_q;
assign parallel_stb = parallel_stb_q;
assign parallel_dout = parallel_dout_q;
always @(*) begin
ss_d = ss;
mosi_d = mosi;
miso_d = miso_q;
sck_d = sck;
sck_old_d = sck_q;
data_d = data_q;
parallel_stb_d = 1'b0;
bit_ct_d = bit_ct_q;
parallel_dout_d = parallel_dout_q;
if (ss_q) begin
bit_ct_d = 'h0;
data_d = parallel_din;
miso_d = data_q[DEPTH-1];
end
else begin
if (!sck_old_q && sck_q) begin // rising edge
data_d = {data_q[DEPTH-1-1:0], mosi_q};
bit_ct_d = bit_ct_q + 1'b1;
if (bit_ct_q == (DEPTH - 1)) begin
parallel_dout_d = {data_q[DEPTH-1-1:0], mosi_q};
parallel_stb_d = 1'b1;
data_d = parallel_din;
end
end
else if (sck_old_q && !sck_q) begin // falling edge
miso_d = data_q[DEPTH-1];
end
end
end
always @(posedge clk) begin
if (rst) begin
parallel_stb_q <= 1'b0;
bit_ct_q <= 'h0;
parallel_dout_q <= 'h0;
miso_q <= 1'b1;
end else begin
parallel_stb_q <= parallel_stb_d;
bit_ct_q <= bit_ct_d;
parallel_dout_q <= parallel_dout_d;
miso_q <= miso_d;
end
sck_q <= sck_d;
mosi_q <= mosi_d;
ss_q <= ss_d;
data_q <= data_d;
sck_old_q <= sck_old_d;
end
endmodule