Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,7 @@
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build*
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catcap_tb
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catgen_tb
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fuse*
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isim*
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_impact*
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coregen.log
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@@ -0,0 +1,91 @@
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#
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# Copyright 2015 Ettus Research LLC
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#
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# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
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##-------------------
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##USRP B2XXXmini FPGA Help
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##-------------------
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##Usage:
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## make <Targets> <Options>
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##
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##Output:
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## build/usrp_<product>_fpga.bit: Configuration bitstream with header
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## build/usrp_<product>_fpga.bin: Configuration bitstream without header
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## build/usrp_<product>_fpga.syr: Xilinx system report
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## build/usrp_<product>_fpga.twr: Xilinx timing report
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print_report = \
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echo "========================================================================"; \
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cat $(1)/b205.syr | grep "Device utilization summary:" -A 30; \
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echo "========================================================================"; \
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echo "Timing Summary:\n"; \
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cat $(1)/b205.twr | grep constraint | grep met | grep -v "*"; \
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echo "========================================================================";
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# pre_build($1=Device)
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ifeq ($(EXPORT_ONLY),1)
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pre_build = @test -s build-$(1)/b205.bit || { echo "EXPORT_ONLY requires the project in build-$(1) to be fully built."; false; }
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else
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pre_build = @echo "ISE Version: $(shell xtclsh -h | head -n1)"
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endif
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# ise_build($1=Device, $2=Definitions)
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ifeq ($(PROJECT_ONLY),1)
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ise_build = make -f Makefile.b205.inc proj NAME=$@ DEVICE=$1
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else ifeq ($(EXPORT_ONLY),1)
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ise_build = @echo "Skipping ISE build and exporting pre-built files.";
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else
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ise_build = make -f Makefile.b205.inc bin NAME=$@ DEVICE=$1
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endif
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# post_build($1=Device)
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ifeq ($(PROJECT_ONLY),1)
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post_build = \
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@echo "Generated $(shell pwd)/build-$(1)/b205.xise"; \
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echo "\nProject Generation DONE ... $(1)\n";
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else
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post_build = \
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@$(call print_report,build-$(1)) \
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mkdir -p build; \
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echo "Exporting bitstream files..."; \
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cp build-$(1)/b205.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga.bin; \
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cp build-$(1)/b205.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga.bit; \
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echo "Exporting logs..."; \
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cp build-$(1)/b205.syr build/usrp_`echo $(1) | tr A-Z a-z`_fpga.syr; \
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cp build-$(1)/b205.twr build/usrp_`echo $(1) | tr A-Z a-z`_fpga.twr; \
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echo "\nBuild DONE ... $(1)\n";
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endif
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##
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##Supported Targets
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##-----------------
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all: B200mini B205mini ##(Default target)
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B200mini: ##Build USRP B200mini design.
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$(call pre_build,B200mini)
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$(call ise_build,XC6SLX75)
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$(call post_build,B200mini)
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B205mini: ##Build USRP B205mini design.
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$(call pre_build,B205mini)
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$(call ise_build,XC6SLX150)
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$(call post_build,B205mini)
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clean: ##Clean up all build output.
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rm -rf build-*
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rm -rf build
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help: ## Show this help message.
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@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
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##
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##Supported Options
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##-----------------
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##PROJECT_ONLY=1 Only create a Xilinx project for the specified target(s).
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## Useful for use with the ISE GUI.
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##EXPORT_ONLY=1 Export build targets from a GUI build to the build directory.
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## Requires the project in build-*_* to be built.
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.PHONY: all clean help B200mini B205mini
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@@ -0,0 +1,129 @@
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#
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# Copyright 2012-2013 Ettus Research LLC
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#
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##################################################
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# Project Setup
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##################################################
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TOP_MODULE := b205
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BUILD_DIR := build-$(NAME)/
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export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
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# set me in a custom makefile
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CUSTOM_SRCS =
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CUSTOM_DEFS =
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include ../Makefile.common
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include ../../lib/gpif2/Makefile.srcs
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include ../../lib/fifo/Makefile.srcs
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include ../../lib/fifo_200/Makefile.srcs
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include ../../lib/dsp/Makefile.srcs
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include ../../lib/control/Makefile.srcs
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include ../../lib/control_200/Makefile.srcs
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include ../../lib/packet_proc/Makefile.srcs
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include ../../lib/packet_proc_200/Makefile.srcs
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include ../../lib/timing/Makefile.srcs
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include ../../lib/vita_200/Makefile.srcs
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include ../../lib/wishbone/Makefile.srcs
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include ../../lib/axi/Makefile.srcs
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include ../../lib/radio_200/Makefile.srcs
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include coregen_dsp/Makefile.srcs
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B205_COREGEN_SRCS = \
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coregen/b205_clk_gen.v \
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coregen/fifo_4k_2clk.xco \
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coregen/fifo_short_2clk.xco \
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coregen/chipscope_icon.xco \
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coregen/chipscope_ila.xco
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##################################################
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# Project Properties
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##################################################
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export PROJECT_PROPERTIES := \
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family "Spartan6" \
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device $(DEVICE) \
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package csg484 \
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speed -3 \
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top_level_module_type "HDL" \
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synthesis_tool "XST (VHDL/Verilog)" \
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simulator "ISE Simulator (VHDL/Verilog)" \
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"Preferred Language" "Verilog" \
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"Enable Message Filtering" FALSE \
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"Display Incremental Messages" FALSE
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##################################################
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# Sources
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##################################################
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TOP_SRCS = \
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b205.v \
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b205_ref_pll.v \
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b205_core.v \
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b205_io.v \
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b205.ucf \
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timing.ucf \
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../b200/S6CLK2PIN.v \
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$(B205_COREGEN_SRCS)
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SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) $(FIFO_200_SRCS) \
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$(CONTROL_LIB_SRCS) $(CONTROL_LIB_200_SRCS) $(SDR_LIB_SRCS) \
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$(TIMING_SRCS) $(OPENCORES_SRCS) \
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$(VRT_SRCS) \
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$(GPIF2_SRCS) $(PACKET_PROC_SRCS) $(PACKET_PROC_200_SRCS) \
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$(WISHBONE_SRCS) \
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$(TIMING_SRCS) \
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$(DSP_SRCS) \
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$(VITA_200_SRCS) \
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$(AXI_SRCS) \
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$(RADIO_200_SRCS) \
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$(CAT_CAP_GEN_SRCS) \
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$(COREGEN_DSP_SRCS)
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##################################################
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# Process Properties
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##################################################
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SYNTHESIZE_PROPERTIES = \
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"Pack I/O Registers into IOBs" Yes \
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"Optimization Effort" High \
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"Optimize Instantiated Primitives" TRUE \
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"Register Balancing" Yes \
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"Use Clock Enable" Auto \
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"Use Synchronous Reset" Auto \
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"Use Synchronous Set" Auto \
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"Verilog Macros" "SPARTAN6=1 $(EXTRA_DEFS) $(CUSTOM_DEFS)" \
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"Other XST Command Line Options" "-loop_iteration_limit 16385"
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#"Number of Clock Buffers" 8 \
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TRANSLATE_PROPERTIES = \
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"Macro Search Path" "$(shell pwd)/../../coregen/"
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MAP_PROPERTIES = \
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"Generate Detailed MAP Report" TRUE \
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"Allow Logic Optimization Across Hierarchy" TRUE \
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"Map to Input Functions" 4 \
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"Optimization Strategy (Cover Mode)" Speed \
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"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
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"Perform Timing-Driven Packing and Placement" TRUE \
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"Map Effort Level" High \
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"Extra Effort" Normal \
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"Combinatorial Logic Optimization" TRUE \
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"Register Duplication" TRUE
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PLACE_ROUTE_PROPERTIES = \
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"Place & Route Effort Level (Overall)" High
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STATIC_TIMING_PROPERTIES = \
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"Number of Paths in Error/Verbose Report" 10 \
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"Report Type" "Error Report"
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GEN_PROG_FILE_PROPERTIES = \
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"Create Binary Configuration File" TRUE \
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"Done (Output Events)" 5 \
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"Enable Bitstream Compression" TRUE \
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"Unused IOB Pins" "Pull Up"
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#"Configuration Rate" 6 \
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#"Enable Outputs (Output Events)" 6 \
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SIM_MODEL_PROPERTIES = ""
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@@ -0,0 +1,157 @@
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#### FX3 Lines ##############################################################
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# GPIF Data lines
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NET "FX3_DQ<0>" LOC = "T22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<1>" LOC = "T21" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<2>" LOC = "M19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<3>" LOC = "R22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<4>" LOC = "R20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<5>" LOC = "R19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<6>" LOC = "P20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<7>" LOC = "N19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<8>" LOC = "P22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<9>" LOC = "N20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<10>" LOC = "P21" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<11>" LOC = "M21" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<12>" LOC = "N22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<13>" LOC = "L22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<14>" LOC = "M22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<15>" LOC = "P19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<16>" LOC = "D21" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<17>" LOC = "F22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<18>" LOC = "C22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<19>" LOC = "D22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<20>" LOC = "E22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<21>" LOC = "B22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<22>" LOC = "B21" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<23>" LOC = "F20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<24>" LOC = "G19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<25>" LOC = "D20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<26>" LOC = "E20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<27>" LOC = "D19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<28>" LOC = "J19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<29>" LOC = "C20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<30>" LOC = "F19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_DQ<31>" LOC = "C18" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data
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NET "FX3_PCLK" LOC = "H20" | IOSTANDARD = LVCMOS18 | DRIVE = 6 | SLEW = SLOW; # FX3 Data Synchronization Clock, called IFCLK in B200
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# GPIF Control Lines
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NET "FX3_CTL0" LOC = "M20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # SLCSn
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NET "FX3_CTL1" LOC = "J22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # SLWRn
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NET "FX3_CTL2" LOC = "J21" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # SLOEn
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NET "FX3_CTL3" LOC = "K22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # SLRDn
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NET "FX3_CTL4" LOC = "M18" | IOSTANDARD = LVCMOS18 ; # FLAG_A
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NET "FX3_CTL5" LOC = "L19" | IOSTANDARD = LVCMOS18 ; # FLAG_B
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NET "FX3_CTL6" LOC = "H22" | IOSTANDARD = LVCMOS18 ; #
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NET "FX3_CTL7" LOC = "L20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # PKTENDn
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NET "FX3_CTL8" LOC = "K19" | IOSTANDARD = LVCMOS18 ; #
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NET "FX3_CTL9" LOC = "K20" | IOSTANDARD = LVCMOS18 ; #
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##FX3_CTL10 is not for general signaling
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NET "FX3_CTL11" LOC = "H21" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # A1
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NET "FX3_CTL12" LOC = "G22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # A0
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|
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|
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#### AD9364 #################################################################
|
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NET "CAT_RESETn" LOC = "T3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Global Reset
|
||||
NET "CAT_EN_AGC" LOC = "AA4" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver AGC Enable
|
||||
NET "CAT_EN" LOC = "V3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Globe Enable
|
||||
NET "CAT_TXnRX" LOC = "Y4" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Globe TX and RX control
|
||||
|
||||
# SPI
|
||||
NET "CAT_SPI_EN" LOC = "T4" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Controller SPI Latch
|
||||
NET "CAT_SPI_CLK" LOC = "Y3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Controller SPI Serial Clock
|
||||
NET "CAT_SPI_DI" LOC = "AA2" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Controller SPI Data In
|
||||
NET "CAT_SPI_DO" LOC = "U4" | IOSTANDARD = LVCMOS18 | PULLUP; # Transceiver Controller SPI Data Out
|
||||
|
||||
# Control Lines
|
||||
NET "CAT_CTL_OUT<0>" LOC = "D2" | IOSTANDARD = LVCMOS18 ; #
|
||||
NET "CAT_CTL_OUT<1>" LOC = "AB4" | IOSTANDARD = LVCMOS18 ; #
|
||||
NET "CAT_CTL_OUT<2>" LOC = "AB3" | IOSTANDARD = LVCMOS18 ; #
|
||||
NET "CAT_CTL_OUT<3>" LOC = "K3" | IOSTANDARD = LVCMOS18 ; #
|
||||
NET "CAT_CTL_OUT<4>" LOC = "AB2" | IOSTANDARD = LVCMOS18 ; #
|
||||
NET "CAT_CTL_OUT<5>" LOC = "T7" | IOSTANDARD = LVCMOS18 ; #
|
||||
NET "CAT_CTL_OUT<6>" LOC = "U8" | IOSTANDARD = LVCMOS18 ; #
|
||||
NET "CAT_CTL_OUT<7>" LOC = "W4" | IOSTANDARD = LVCMOS18 ; #
|
||||
NET "CAT_CTL_IN<0>" LOC = "H5" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; #
|
||||
NET "CAT_CTL_IN<1>" LOC = "H3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; #
|
||||
NET "CAT_CTL_IN<2>" LOC = "J4" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; #
|
||||
NET "CAT_CTL_IN<3>" LOC = "D1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; #
|
||||
|
||||
# Rx Bus
|
||||
NET "CAT_P0_D<0>" LOC = "H1" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P0_D<1>" LOC = "H2" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P0_D<2>" LOC = "G1" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LT.
|
||||
NET "CAT_P0_D<3>" LOC = "G3" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LT.
|
||||
NET "CAT_P0_D<4>" LOC = "F1" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LT.
|
||||
NET "CAT_P0_D<5>" LOC = "F2" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LT.
|
||||
NET "CAT_P0_D<6>" LOC = "E1" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LT.
|
||||
NET "CAT_P0_D<7>" LOC = "E3" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LT.
|
||||
NET "CAT_P0_D<8>" LOC = "L1" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P0_D<9>" LOC = "L3" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P0_D<10>" LOC = "M1" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P0_D<11>" LOC = "M2" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LB.
|
||||
|
||||
# Tx Bus
|
||||
NET "CAT_P1_D<0>" LOC = "T1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P1_D<1>" LOC = "T2" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P1_D<2>" LOC = "U1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P1_D<3>" LOC = "U3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P1_D<4>" LOC = "V1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P1_D<5>" LOC = "V2" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P1_D<6>" LOC = "W1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P1_D<7>" LOC = "W3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P1_D<8>" LOC = "Y1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P1_D<9>" LOC = "Y2" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P1_D<10>" LOC = "R1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB.
|
||||
NET "CAT_P1_D<11>" LOC = "R3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB.
|
||||
|
||||
# Frame syncs
|
||||
NET "CAT_TX_FR_N" LOC = "K1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Bank3 LB.
|
||||
NET "CAT_TX_FR_P" LOC = "K2" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Bank3 LB.
|
||||
#NET "CAT_RX_FR_N" LOC = "P1" | IOSTANDARD = LVCMOS18; # Bank3 LB.
|
||||
NET "CAT_RX_FR_P" LOC = "P2" | IOSTANDARD = LVCMOS18; # Bank3 LB.
|
||||
|
||||
# Clocks ('N' clock lines are currently unused)
|
||||
#NET "CAT_DCLK_N" LOC = "P3" | IOSTANDARD = LVCMOS18; # Data Clock
|
||||
NET "CAT_DCLK_P" LOC = "N4" | IOSTANDARD = LVCMOS18; # Data Clock
|
||||
NET "CAT_FBCLK_P" LOC = "J3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Clock to AD9364. Bank3 LB.
|
||||
NET "CAT_FBCLK_N" LOC = "J1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Clock to AD9364. Bank3 LB.
|
||||
|
||||
#### Peripherals ############################################################
|
||||
# Radio Switchery
|
||||
NET "cFE_SEL_TRX_TX" LOC = "A5" | IOSTANDARD = LVCMOS33 | DRIVE = 2 | SLEW = SLOW; # TRX Switch, high to enable TX path (Always on for Duplex) (high for now)
|
||||
NET "cFE_SEL_TRX_RX" LOC = "A6" | IOSTANDARD = LVCMOS33 | DRIVE = 2 | SLEW = SLOW; # TRX Switch, high to enable RX path (Always off for Duplex) (low for now)
|
||||
NET "cFE_SEL_RX_TRX" LOC = "B3" | IOSTANDARD = LVCMOS33 | DRIVE = 2 | SLEW = SLOW; # high to enable RX path to TRX switch (Always off for Duplex) (low for now)
|
||||
NET "cFE_SEL_RX_RX2" LOC = "C5" | IOSTANDARD = LVCMOS33 | DRIVE = 2 | SLEW = SLOW; # high to enable RX path to RX2 port (Always on for Duplex) (high for now)
|
||||
NET "cTXDRV_PWEN" LOC = "A4" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; # high to enable power to TX power amplifier (high for now)
|
||||
|
||||
# LEDs R: 5mA / G: 1.25mA / B: 2.5mA (the mcd is equalized with this number), set by resistor already, with LVTTL logic (3.3V)
|
||||
NET "cLED_TRX_G" LOC = "A7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on TRX port LED green
|
||||
NET "cLED_TRX_B" LOC = "B6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on TRX port LED blue
|
||||
NET "cLED_TRX_R" LOC = "C6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on TRX port LED red
|
||||
NET "cLED_RX2_G" LOC = "A9" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on RX2 port LED green
|
||||
NET "cLED_RX2_B" LOC = "B8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on RX2 port LED blue
|
||||
NET "cLED_RX2_R" LOC = "A8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on RX2 port LED red
|
||||
NET "cLED_S0" LOC = "B10" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on S0 port LED red
|
||||
NET "cLED_S1" LOC = "A10" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on S1 port LED red
|
||||
|
||||
|
||||
# Clocking
|
||||
NET "CLK_40MHz_FPGA" LOC = "AA10" | IOSTANDARD = LVCMOS18; # 40MHz VCTCXO clock feed back
|
||||
NET "PPS_IN" LOC = "B12" | IOSTANDARD = LVCMOS33; # Pulse per second input (external)
|
||||
NET "CLKIN_10MHz" LOC = "E6" | IOSTANDARD = LVCMOS18; # 10MHz from external source
|
||||
NET "CLKIN_10MHz_REQ" LOC = "E5" | IOSTANDARD = LVCMOS18; # select 10MHz from external source
|
||||
NET "CLK_40M_DAC_nSYNC" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 2 | SLEW = SLOW; # 40MHz VCTCXO triming DAC serial frame/data latch (high for now)
|
||||
NET "CLK_40M_DAC_SCLK" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 2 | SLEW = SLOW; # 40MHz VCTCXO triming DAC serial data clock (low for now)
|
||||
NET "CLK_40M_DAC_DIN" LOC = "C16" | IOSTANDARD = LVCMOS33 | DRIVE = 2 | SLEW = SLOW; # 40MHz VCTCXO triming DAC serial data (low for now)
|
||||
|
||||
## GPIO bus
|
||||
NET "fp_gpio<0>" LOC = "A18" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "fp_gpio<1>" LOC = "A17" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "fp_gpio<2>" LOC = "B16" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "fp_gpio<3>" LOC = "B18" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "fp_gpio<4>" LOC = "C15" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "fp_gpio<5>" LOC = "A15" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "fp_gpio<6>" LOC = "A16" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "fp_gpio<7>" LOC = "A13" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
@@ -0,0 +1,298 @@
|
||||
//
|
||||
// Copyright 2015 Ettus Research, a National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
|
||||
/***********************************************************
|
||||
* B205 Module Declaration
|
||||
**********************************************************/
|
||||
module b205 (
|
||||
// AD9364 - SPI Interface:
|
||||
output CAT_SPI_EN, // Enable
|
||||
input CAT_SPI_DO, // MISO
|
||||
output CAT_SPI_DI, // MOSI
|
||||
output CAT_SPI_CLK, // SPI Clk
|
||||
|
||||
// AD9364 - Control:
|
||||
output CAT_EN,
|
||||
output CAT_EN_AGC,
|
||||
output CAT_RESETn,
|
||||
output CAT_TXnRX,
|
||||
output [3:0] CAT_CTL_IN, // These should be outputs
|
||||
input [7:0] CAT_CTL_OUT, // MUST BE INPUT
|
||||
|
||||
// AD9364 - Data:
|
||||
input CAT_DCLK_P, // Clock from AD9364 (RX)
|
||||
output CAT_FBCLK_P, // Clock to AD9364 (TX)
|
||||
output CAT_FBCLK_N,
|
||||
input [11:0] CAT_P0_D, // RX data is on Port 0
|
||||
output [11:0] CAT_P1_D, // TX data is on Port 1
|
||||
input CAT_RX_FR_P,
|
||||
output CAT_TX_FR_P,
|
||||
output CAT_TX_FR_N,
|
||||
|
||||
// AD9364 - Always on 40MHz clock:
|
||||
input CLK_40MHz_FPGA,
|
||||
|
||||
// GPIF, FX3 Slave FIFO
|
||||
output FX3_PCLK, // pclk
|
||||
output FX3_CTL0, // n_slcs
|
||||
output FX3_CTL1, // n_slwr
|
||||
output FX3_CTL2, // n_sloe
|
||||
output FX3_CTL3, // n_slrd
|
||||
output FX3_CTL7, // n_pktend
|
||||
input FX3_CTL4, // slfifo_flags[0]
|
||||
input FX3_CTL5, // slfifo_flags[1]
|
||||
input FX3_CTL6, // Serial settings bus from FX3. SDA
|
||||
input FX3_CTL8, // Serial settings bus from FX3. SCL
|
||||
output FX3_CTL11, // slfifo_addr[1]
|
||||
output FX3_CTL12, // slfifo_addr[0]
|
||||
inout [31:0] FX3_DQ,
|
||||
input FX3_CTL9, // global_reset
|
||||
|
||||
// LEDs
|
||||
output cLED_TRX_G,
|
||||
output cLED_TRX_B,
|
||||
output cLED_TRX_R,
|
||||
output cLED_RX2_G,
|
||||
output cLED_RX2_B,
|
||||
output cLED_RX2_R,
|
||||
output cLED_S0,
|
||||
output cLED_S1,
|
||||
|
||||
// GPIO
|
||||
inout [7:0] fp_gpio,
|
||||
|
||||
// PPS or 10 MHz (need to choose from SW)
|
||||
input PPS_IN,
|
||||
input CLKIN_10MHz,
|
||||
output CLKIN_10MHz_REQ,
|
||||
|
||||
// Clock disciplining / AD5662 controls
|
||||
output CLK_40M_DAC_nSYNC,
|
||||
output CLK_40M_DAC_SCLK,
|
||||
output CLK_40M_DAC_DIN,
|
||||
|
||||
// RF Hardware Control
|
||||
output cFE_SEL_TRX_TX, // Select TX/RX port for Tx
|
||||
output cFE_SEL_TRX_RX, // Select TX/RX port for Rx
|
||||
output cFE_SEL_RX_TRX, // Select TX/RX port for Rx
|
||||
output cFE_SEL_RX_RX2, // Select RX2 port for Rx
|
||||
output cTXDRV_PWEN // Tx PA enable
|
||||
|
||||
);
|
||||
|
||||
wire reset_global = FX3_CTL9;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// generate clocks from always on codec main clk
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire bus_clk, radio_clk;
|
||||
wire locked;
|
||||
wire int_40mhz;
|
||||
wire ref_pll_clk;
|
||||
b205_clk_gen gen_clks
|
||||
(
|
||||
.CLK_IN1_40(CLK_40MHz_FPGA), // No differential input!
|
||||
.CLK_OUT1_40_int(int_40mhz), .CLK_OUT2_100_bus(bus_clk), .CLK_OUT3_200_ref_pll(ref_pll_clk),
|
||||
.RESET(reset_global), .LOCKED(locked)
|
||||
);
|
||||
|
||||
//hold-off logic for clocks ready
|
||||
reg [15:0] clocks_ready_count;
|
||||
reg clocks_ready;
|
||||
always @(posedge bus_clk or posedge reset_global or negedge locked) begin
|
||||
if (reset_global | !locked) begin
|
||||
clocks_ready_count <= 16'b0;
|
||||
clocks_ready <= 1'b0;
|
||||
end
|
||||
else if (!clocks_ready) begin
|
||||
clocks_ready_count <= clocks_ready_count + 1'b1;
|
||||
clocks_ready <= (clocks_ready_count == 16'hffff);
|
||||
end
|
||||
end
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// drive output clocks
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
ODDR2 #(
|
||||
.DDR_ALIGNMENT("NONE"), // to "NONE", "C0" or "C1"
|
||||
.INIT(1'b0), // output to 1'b0 or 1'b1
|
||||
.SRTYPE("ASYNC") // set/reset "SYNC" or "ASYNC"
|
||||
)
|
||||
ODDR2_S6CLK2PIN
|
||||
(
|
||||
.Q(FX3_PCLK), // 1-bit DDR output data
|
||||
.C0(bus_clk), // 1-bit clock input
|
||||
.C1(~bus_clk), // 1-bit clock input
|
||||
.CE(1'b1), // 1-bit clock enable input
|
||||
.D0(1'b1), // 1-bit data input (associated with C0)
|
||||
.D1(1'b0), // 1-bit data input (associated with C1)
|
||||
.R(1'b0), // 1-bit reset input
|
||||
.S(1'b0) // 1-bit set input
|
||||
);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// Create sync reset signals
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire bus_rst, ref_pll_rst, radio_rst;
|
||||
reset_sync bus_sync(.clk(bus_clk), .reset_in(!clocks_ready), .reset_out(bus_rst));
|
||||
reset_sync ref_pll_sync(.clk(ref_pll_clk), .reset_in(!clocks_ready), .reset_out(ref_pll_rst));
|
||||
reset_sync radio_sync(.clk(radio_clk), .reset_in(!clocks_ready), .reset_out(radio_rst));
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// reference clock PLL
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire ref_sel;
|
||||
wire ext_ref_is_pps;
|
||||
wire ext_ref_locked;
|
||||
wire ext_ref = ext_ref_is_pps ? PPS_IN : ref_sel ? CLKIN_10MHz : 1'b0;
|
||||
b205_ref_pll ref_pll
|
||||
(
|
||||
.reset(ref_pll_rst),
|
||||
.clk(ref_pll_clk),
|
||||
.refclk(int_40mhz),
|
||||
.ref(ext_ref),
|
||||
.locked(ext_ref_locked),
|
||||
.sclk(CLK_40M_DAC_SCLK),
|
||||
.mosi(CLK_40M_DAC_DIN),
|
||||
.sync_n(CLK_40M_DAC_nSYNC)
|
||||
);
|
||||
assign CLKIN_10MHz_REQ = ref_sel;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// AD9364 I/O
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire [31:0] rx_data;
|
||||
wire [31:0] tx_data;
|
||||
|
||||
b205_io b205_io_i0
|
||||
(
|
||||
.reset(reset_global),
|
||||
// Baseband sample interface
|
||||
.radio_clk(radio_clk),
|
||||
.rx_i0(rx_data[31:20]),
|
||||
.rx_q0(rx_data[15:4]),
|
||||
.tx_i0(tx_data[31:20]),
|
||||
.tx_q0(tx_data[15:4]),
|
||||
// Catalina interface
|
||||
.rx_clk(CAT_DCLK_P),
|
||||
.rx_frame(CAT_RX_FR_P),
|
||||
.rx_data(CAT_P0_D),
|
||||
|
||||
.tx_clk(CAT_FBCLK_P),
|
||||
.tx_frame(CAT_TX_FR_P),
|
||||
.tx_data(CAT_P1_D)
|
||||
);
|
||||
|
||||
assign {rx_data[19:16],rx_data[3:0]} = 8'h0;
|
||||
assign CAT_FBCLK_N = 1'b0;
|
||||
assign CAT_TX_FR_N = 1'b0;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// SPI connections
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire mosi, miso, sclk;
|
||||
wire [7:0] sen;
|
||||
|
||||
// AD9364 Slave (it's the only slave for B205)
|
||||
assign CAT_SPI_EN = sen[0];
|
||||
assign CAT_SPI_DI = ~sen[0] & mosi;
|
||||
assign CAT_SPI_CLK = ~sen[0] & sclk;
|
||||
assign miso = CAT_SPI_DO;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// bus signals
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire [63:0] ctrl_tdata, resp_tdata, rx_tdata, tx_tdata;
|
||||
wire ctrl_tlast, resp_tlast, rx_tlast, tx_tlast;
|
||||
wire ctrl_tvalid, resp_tvalid, rx_tvalid, tx_tvalid;
|
||||
wire ctrl_tready, resp_tready, rx_tready, tx_tready;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// frontend assignments
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire [7:0] fe_gpio_out;
|
||||
reg [7:0] fe_gpio_reg;
|
||||
|
||||
//Register in IOB
|
||||
always @(posedge radio_clk)
|
||||
fe_gpio_reg <= fe_gpio_out;
|
||||
|
||||
assign {cTXDRV_PWEN, cFE_SEL_RX_RX2, cFE_SEL_TRX_TX, cFE_SEL_RX_TRX, cFE_SEL_TRX_RX} = fe_gpio_reg[7:3];
|
||||
assign cLED_TRX_R = ~fe_gpio_reg[0];
|
||||
assign cLED_TRX_G = ~fe_gpio_reg[1];
|
||||
assign cLED_TRX_B = 1'b1;
|
||||
assign cLED_RX2_R = 1'b1;
|
||||
assign cLED_RX2_G = ~fe_gpio_reg[2];
|
||||
assign cLED_RX2_B = 1'b1;
|
||||
assign cLED_S0 = ~ext_ref_locked;
|
||||
assign cLED_S1 = ~(ext_ref);
|
||||
|
||||
wire [31:0] misc_outs;
|
||||
reg [31:0] misc_outs_r;
|
||||
always @(posedge bus_clk) misc_outs_r <= misc_outs; //register misc ios to ease routing to flop
|
||||
assign ref_sel = misc_outs_r[0];
|
||||
|
||||
wire codec_arst = misc_outs_r[2];
|
||||
|
||||
assign CAT_CTL_IN = 4'b1;
|
||||
assign CAT_EN_AGC = 1'b1;
|
||||
assign CAT_TXnRX = 1'b1;
|
||||
assign CAT_EN = 1'b1;
|
||||
assign CAT_RESETn = ~codec_arst; // Codec Reset // RESETB // Operates active-low
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// b205 core
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire [7:0] fp_gpio_in, fp_gpio_out, fp_gpio_ddr;
|
||||
b205_core #(.EXTRA_BUFF_SIZE(12)) b205_core
|
||||
(
|
||||
.bus_clk(bus_clk), .bus_rst(bus_rst),
|
||||
.tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
|
||||
.rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready),
|
||||
.ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast), .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready),
|
||||
.resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready),
|
||||
|
||||
.radio_clk(radio_clk), .radio_rst(radio_rst),
|
||||
.rx0(rx_data),
|
||||
.tx0(tx_data),
|
||||
.fe_gpio_out(fe_gpio_out),
|
||||
.fp_gpio_in(fp_gpio_in), .fp_gpio_out(fp_gpio_out), .fp_gpio_ddr(fp_gpio_ddr),
|
||||
.ext_ref_is_pps(ext_ref_is_pps),
|
||||
.pps_ext(PPS_IN),
|
||||
|
||||
.sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso),
|
||||
.rb_misc({31'b0,ext_ref_locked}), .misc_outs(misc_outs),
|
||||
|
||||
.lock_signals(CAT_CTL_OUT[7:6]),
|
||||
|
||||
.debug()
|
||||
);
|
||||
|
||||
gpio_atr_io #(.WIDTH(8)) gpio_atr_io_inst (
|
||||
.clk(radio_clk), .gpio_pins(fp_gpio),
|
||||
.gpio_ddr(fp_gpio_ddr), .gpio_out(fp_gpio_out), .gpio_in(fp_gpio_in)
|
||||
);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// GPIF2
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
gpif2_slave_fifo32 #(.DATA_RX_FIFO_SIZE(13), .DATA_TX_FIFO_SIZE(13)) slave_fifo32
|
||||
(
|
||||
.gpif_clk(bus_clk), .gpif_rst(bus_rst), .gpif_enb(1'b1),
|
||||
.gpif_ctl({FX3_CTL8, FX3_CTL6, FX3_CTL5, FX3_CTL4}), .fifoadr({FX3_CTL11, FX3_CTL12}),
|
||||
.slwr(FX3_CTL1), .sloe(FX3_CTL2), .slcs(FX3_CTL0), .slrd(FX3_CTL3), .pktend(FX3_CTL7),
|
||||
.gpif_d(FX3_DQ),
|
||||
|
||||
.fifo_clk(bus_clk), .fifo_rst(bus_rst),
|
||||
.tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
|
||||
.rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready),
|
||||
.ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast), .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready),
|
||||
.resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready),
|
||||
|
||||
.debug()
|
||||
);
|
||||
|
||||
endmodule // B205
|
||||
@@ -0,0 +1,250 @@
|
||||
//
|
||||
// Copyright 2015 Ettus Research, a National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
|
||||
|
||||
/***********************************************************
|
||||
* B205 Core Guts
|
||||
**********************************************************/
|
||||
module b205_core
|
||||
#(
|
||||
parameter R0_CTRL_SID = 8'h10,
|
||||
parameter U0_CTRL_SID = 8'h30,
|
||||
parameter L0_CTRL_SID = 8'h40,
|
||||
parameter R0_DATA_SID = 8'h50,
|
||||
parameter R1_DATA_SID = 8'h60,
|
||||
parameter DEMUX_SID_MASK = 8'hf0,
|
||||
parameter EXTRA_BUFF_SIZE = 0,
|
||||
parameter RADIO_FIFO_SIZE = 11,
|
||||
parameter SAMPLE_FIFO_SIZE = 11
|
||||
|
||||
)
|
||||
(
|
||||
////////////////////////////////////////////////////////////////////
|
||||
// bus interfaces
|
||||
////////////////////////////////////////////////////////////////////
|
||||
input bus_clk,
|
||||
input bus_rst,
|
||||
|
||||
input [63:0] tx_tdata, input tx_tlast, input tx_tvalid, output tx_tready,
|
||||
output [63:0] rx_tdata, output rx_tlast, output rx_tvalid, input rx_tready,
|
||||
input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output ctrl_tready,
|
||||
output [63:0] resp_tdata, output resp_tlast, output resp_tvalid, input resp_tready,
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
// radio interfaces
|
||||
////////////////////////////////////////////////////////////////////
|
||||
input radio_clk,
|
||||
input radio_rst,
|
||||
|
||||
input [31:0] rx0,
|
||||
output [31:0] tx0,
|
||||
output [7:0] fe_gpio_out,
|
||||
input [7:0] fp_gpio_in, output [7:0] fp_gpio_out, output [7:0] fp_gpio_ddr,
|
||||
output ext_ref_is_pps,
|
||||
input pps_ext,
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
// core interfaces
|
||||
////////////////////////////////////////////////////////////////////
|
||||
output [7:0] sen, output sclk, output mosi, input miso,
|
||||
input [31:0] rb_misc,
|
||||
output [31:0] misc_outs,
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
// fe lock signals
|
||||
////////////////////////////////////////////////////////////////////
|
||||
input [1:0] lock_signals,
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
// debug signals
|
||||
////////////////////////////////////////////////////////////////////
|
||||
output [63:0] debug
|
||||
);
|
||||
localparam SR_CORE_SPI = 8'd8;
|
||||
localparam SR_CORE_MISC = 8'd16;
|
||||
localparam SR_CORE_COMPAT = 8'd24;
|
||||
localparam SR_CORE_READBACK = 8'd32;
|
||||
localparam SR_CORE_GPSDO_ST = 8'd40;
|
||||
localparam SR_CORE_SYNC = 8'd48;
|
||||
localparam COMPAT_MAJOR = 16'h0007;
|
||||
localparam COMPAT_MINOR = 16'h0000;
|
||||
|
||||
reg [1:0] lock_state;
|
||||
reg [1:0] lock_state_r;
|
||||
|
||||
always @(posedge bus_clk)
|
||||
if (bus_rst)
|
||||
{lock_state_r, lock_state} <= 4'h0;
|
||||
else
|
||||
{lock_state_r, lock_state} <= {lock_state, lock_signals};
|
||||
|
||||
|
||||
/*******************************************************************
|
||||
* PPS Timing stuff
|
||||
******************************************************************/
|
||||
|
||||
// Generate an internal PPS signal
|
||||
wire int_pps;
|
||||
pps_generator #(.CLK_FREQ(100000000)) pps_gen
|
||||
(.clk(bus_clk), .pps(int_pps));
|
||||
|
||||
// Flop PPS signals into radio clock domain
|
||||
reg [1:0] ext_pps_del, int_pps_del;
|
||||
always @(posedge radio_clk) ext_pps_del[1:0] <= {ext_pps_del[0], pps_ext};
|
||||
always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], int_pps};
|
||||
|
||||
// PPS mux
|
||||
wire [1:0] pps_select;
|
||||
wire pps = (pps_select == 2'b01)? ext_pps_del[1] :
|
||||
(pps_select == 2'b10)? int_pps_del[1] :
|
||||
1'b0;
|
||||
assign ext_ref_is_pps = (pps_select == 2'b01);
|
||||
|
||||
/*******************************************************************
|
||||
* Response mux Routing logic
|
||||
******************************************************************/
|
||||
wire [63:0] r0_resp_tdata; wire r0_resp_tlast, r0_resp_tvalid, r0_resp_tready;
|
||||
wire [63:0] l0_resp_tdata; wire l0_resp_tlast, l0_resp_tvalid, l0_resp_tready;
|
||||
|
||||
axi_mux4 #(.WIDTH(64), .BUFFER(1)) mux_for_resp
|
||||
(
|
||||
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
|
||||
.i0_tdata(r0_resp_tdata), .i0_tlast(r0_resp_tlast), .i0_tvalid(r0_resp_tvalid), .i0_tready(r0_resp_tready),
|
||||
.i1_tdata(l0_resp_tdata), .i1_tlast(l0_resp_tlast), .i1_tvalid(l0_resp_tvalid), .i1_tready(l0_resp_tready),
|
||||
.i2_tdata(64'd0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(),
|
||||
.i3_tdata(64'd0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(),
|
||||
.o_tdata(resp_tdata), .o_tlast(resp_tlast), .o_tvalid(resp_tvalid), .o_tready(resp_tready)
|
||||
);
|
||||
|
||||
/*******************************************************************
|
||||
* Control demux Routing logic
|
||||
******************************************************************/
|
||||
wire [63:0] r0_ctrl_tdata; wire r0_ctrl_tlast, r0_ctrl_tvalid, r0_ctrl_tready;
|
||||
wire [63:0] l0_ctrl_tdata; wire l0_ctrl_tlast, l0_ctrl_tvalid, l0_ctrl_tready;
|
||||
|
||||
wire [63:0] ctrl_hdr;
|
||||
wire [1:0] ctrl_dst =
|
||||
((ctrl_hdr[7:0] & DEMUX_SID_MASK) == R0_CTRL_SID)? 0 : (
|
||||
((ctrl_hdr[7:0] & DEMUX_SID_MASK) == L0_CTRL_SID)? 1 : (
|
||||
3));
|
||||
axi_demux4 #(.ACTIVE_CHAN(4'b1111), .WIDTH(64), .BUFFER(1)) demux_for_ctrl
|
||||
(
|
||||
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
|
||||
.header(ctrl_hdr), .dest(ctrl_dst),
|
||||
.i_tdata(ctrl_tdata), .i_tlast(ctrl_tlast), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready),
|
||||
.o0_tdata(r0_ctrl_tdata), .o0_tlast(r0_ctrl_tlast), .o0_tvalid(r0_ctrl_tvalid), .o0_tready(r0_ctrl_tready),
|
||||
.o1_tdata(l0_ctrl_tdata), .o1_tlast(l0_ctrl_tlast), .o1_tvalid(l0_ctrl_tvalid), .o1_tready(l0_ctrl_tready),
|
||||
.o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1),
|
||||
.o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1)
|
||||
);
|
||||
|
||||
/*******************************************************************
|
||||
* Misc controls
|
||||
******************************************************************/
|
||||
wire set_stb;
|
||||
wire [7:0] set_addr;
|
||||
wire [31:0] set_data;
|
||||
|
||||
wire spi_ready;
|
||||
wire [31:0] spi_readback;
|
||||
|
||||
wire [1:0] rb_addr;
|
||||
reg [63:0] rb_data;
|
||||
|
||||
wire [63:0] l0i_ctrl_tdata; wire l0i_ctrl_tlast, l0i_ctrl_tvalid, l0i_ctrl_tready;
|
||||
|
||||
wire time_sync, time_sync_r;
|
||||
|
||||
synchronizer time_sync_synchronizer
|
||||
(.clk(radio_clk), .rst(radio_rst), .in(time_sync), .out(time_sync_r));
|
||||
|
||||
axi_fifo #(.WIDTH(65), .SIZE(0)) radio_ctrl_proc_timing_fifo
|
||||
(
|
||||
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
|
||||
.i_tdata({l0_ctrl_tlast, l0_ctrl_tdata}), .i_tvalid(l0_ctrl_tvalid), .i_tready(l0_ctrl_tready), .space(),
|
||||
.o_tdata({l0i_ctrl_tlast, l0i_ctrl_tdata}), .o_tvalid(l0i_ctrl_tvalid), .o_tready(l0i_ctrl_tready), .occupied()
|
||||
);
|
||||
|
||||
radio_ctrl_proc radio_ctrl_proc
|
||||
(
|
||||
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
|
||||
.ctrl_tdata(l0i_ctrl_tdata), .ctrl_tlast(l0i_ctrl_tlast), .ctrl_tvalid(l0i_ctrl_tvalid), .ctrl_tready(l0i_ctrl_tready),
|
||||
.resp_tdata(l0_resp_tdata), .resp_tlast(l0_resp_tlast), .resp_tvalid(l0_resp_tvalid), .resp_tready(l0_resp_tready),
|
||||
.vita_time(64'b0),
|
||||
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
|
||||
.ready(spi_ready), .readback(rb_data),
|
||||
.debug()
|
||||
);
|
||||
|
||||
setting_reg #(.my_addr(SR_CORE_MISC), .awidth(8), .width(32), .at_reset(8'h0)) sr_misc
|
||||
(
|
||||
.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||
.out(misc_outs), .changed()
|
||||
);
|
||||
|
||||
setting_reg #(.my_addr(SR_CORE_READBACK), .awidth(8), .width(2)) sr_rdback
|
||||
(
|
||||
.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||
.out(rb_addr), .changed()
|
||||
);
|
||||
|
||||
setting_reg #(.my_addr(SR_CORE_SYNC), .awidth(8), .width(3)) sr_sync
|
||||
(
|
||||
.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||
.out({time_sync,pps_select}), .changed()
|
||||
);
|
||||
|
||||
simple_spi_core #(.BASE(SR_CORE_SPI), .WIDTH(8), .CLK_IDLE(0), .SEN_IDLE(8'hFF)) misc_spi
|
||||
(
|
||||
.clock(bus_clk), .reset(bus_rst),
|
||||
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
|
||||
.readback(spi_readback), .ready(spi_ready),
|
||||
.sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso),
|
||||
.debug()
|
||||
);
|
||||
|
||||
always @*
|
||||
case(rb_addr)
|
||||
2'd0 : rb_data <= { 32'hACE0BA5E, COMPAT_MAJOR, COMPAT_MINOR };
|
||||
2'd1 : rb_data <= { 32'b0, spi_readback };
|
||||
2'd2 : rb_data <= { 16'b0, 8'd1, 8'd0, rb_misc };
|
||||
2'd3 : rb_data <= { 30'h0, lock_state_r };
|
||||
default : rb_data <= 64'd0;
|
||||
endcase // case (rb_addr)
|
||||
|
||||
/*******************************************************************
|
||||
* Radio
|
||||
******************************************************************/
|
||||
wire [31:0] fe_gpio_out32;
|
||||
wire [9:0] fp_gpio_out10, fp_gpio_ddr10;
|
||||
assign fe_gpio_out = fe_gpio_out32[7:0];
|
||||
assign fp_gpio_out = fp_gpio_out10[7:0];
|
||||
assign fp_gpio_ddr = fp_gpio_ddr10[7:0];
|
||||
|
||||
radio_legacy #(
|
||||
.RADIO_FIFO_SIZE(RADIO_FIFO_SIZE),
|
||||
.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE),
|
||||
.FP_GPIO(1),
|
||||
.NEW_HB_INTERP(1),
|
||||
.NEW_HB_DECIM(1),
|
||||
.SOURCE_FLOW_CONTROL(0),
|
||||
.USER_SETTINGS(0),
|
||||
.DEVICE("SPARTAN6")
|
||||
) radio (
|
||||
.radio_clk(radio_clk), .radio_rst(radio_rst),
|
||||
.rx(rx0), .tx(tx0), .pps(pps), .time_sync(time_sync_r),
|
||||
.fe_gpio_in(32'h00000000), .fe_gpio_out(fe_gpio_out32), .fe_gpio_ddr(/* Always assumed to be outputs */),
|
||||
.fp_gpio_in({2'b00, fp_gpio_in}), .fp_gpio_out(fp_gpio_out10), .fp_gpio_ddr(fp_gpio_ddr10),
|
||||
.bus_clk(bus_clk), .bus_rst(bus_rst),
|
||||
.tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
|
||||
.rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready),
|
||||
.ctrl_tdata(r0_ctrl_tdata), .ctrl_tlast(r0_ctrl_tlast), .ctrl_tvalid(r0_ctrl_tvalid), .ctrl_tready(r0_ctrl_tready),
|
||||
.resp_tdata(r0_resp_tdata), .resp_tlast(r0_resp_tlast), .resp_tvalid(r0_resp_tvalid), .resp_tready(r0_resp_tready),
|
||||
.debug()
|
||||
);
|
||||
|
||||
|
||||
endmodule // b205_core
|
||||
@@ -0,0 +1,459 @@
|
||||
//
|
||||
// Copyright 2015 Ettus Research, a National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// NOTE: B205 is a SISO only device. MIMO references are unused code branches.
|
||||
//
|
||||
// In SISO mode, we output a clock thats 1x the frequency of the Catalina
|
||||
// source-synchronous bus clock to be used as the radio_clk.
|
||||
//
|
||||
//------------------------------------------------------------------
|
||||
|
||||
module b205_io
|
||||
(
|
||||
input reset,
|
||||
|
||||
// Baseband sample interface
|
||||
output radio_clk,
|
||||
output [11:0] rx_i0,
|
||||
output [11:0] rx_q0,
|
||||
input [11:0] tx_i0,
|
||||
input [11:0] tx_q0,
|
||||
|
||||
// Catalina interface
|
||||
input rx_clk,
|
||||
input rx_frame,
|
||||
input [11:0] rx_data,
|
||||
output tx_clk,
|
||||
output tx_frame,
|
||||
output [11:0] tx_data
|
||||
);
|
||||
|
||||
|
||||
genvar z;
|
||||
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// Clock Buffering.
|
||||
// BUFIO2 drives all IDDR2 and ODDR2 cells directly in bank3.
|
||||
// Need two pairs of BUFIO2 one pair each for Top Left and Bottom Left half banks.
|
||||
//------------------------------------------------------------------
|
||||
wire rx_clk_buf;
|
||||
wire siso_clk_unbuf;
|
||||
wire siso_clk2_unbuf;
|
||||
|
||||
IBUFG clk_ibufg (.O(rx_clk_buf), .I(rx_clk));
|
||||
|
||||
//------------------------------------------------------------------
|
||||
//
|
||||
// Buffers for LEFT TOP half bank pins
|
||||
// BUFIO2_X0Y22
|
||||
//
|
||||
//------------------------------------------------------------------
|
||||
BUFIO2 #(
|
||||
.DIVIDE(4),
|
||||
.DIVIDE_BYPASS("FALSE"),
|
||||
.I_INVERT("FALSE"),
|
||||
.USE_DOUBLER("TRUE"))
|
||||
clk_bufio_lt
|
||||
(
|
||||
.IOCLK(io_clk_lt),
|
||||
.DIVCLK(),
|
||||
.SERDESSTROBE(),
|
||||
.I(rx_clk_buf)
|
||||
);
|
||||
|
||||
// BUFIO2_X0Y23
|
||||
BUFIO2 #(
|
||||
.DIVIDE(1),
|
||||
.DIVIDE_BYPASS("FALSE"),
|
||||
.I_INVERT("TRUE"),
|
||||
.USE_DOUBLER("FALSE"))
|
||||
clk_bufio_lt_b
|
||||
(
|
||||
.IOCLK(io_clk_lt_b),
|
||||
.DIVCLK(siso_clk2_unbuf), // Inverted source of 1x interface clock for radio_clk
|
||||
.SERDESSTROBE(),
|
||||
.I(rx_clk_buf)
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------
|
||||
//
|
||||
// Buffers for LEFT BOTTOM half bank pins
|
||||
// BUFIO2_X1Y14
|
||||
//
|
||||
//------------------------------------------------------------------
|
||||
BUFIO2 #(
|
||||
.DIVIDE(1),
|
||||
.DIVIDE_BYPASS("FALSE"),
|
||||
.I_INVERT("FALSE"),
|
||||
.USE_DOUBLER("FALSE"))
|
||||
clk_bufio_lb
|
||||
(
|
||||
.IOCLK(io_clk_lb),
|
||||
.DIVCLK(siso_clk_unbuf), // Non-inverted source of 1x interface clock for local IO use
|
||||
.SERDESSTROBE(),
|
||||
.I(rx_clk_buf)
|
||||
);
|
||||
|
||||
// BUFIO2_X1Y15
|
||||
BUFIO2 #(
|
||||
.DIVIDE(1),
|
||||
.DIVIDE_BYPASS("FALSE"),
|
||||
.I_INVERT("TRUE"),
|
||||
.USE_DOUBLER("FALSE"))
|
||||
clk_bufio_lb_b
|
||||
(
|
||||
.IOCLK(io_clk_lb_b),
|
||||
.DIVCLK(/*siso_clk2_unbuf*/),
|
||||
.SERDESSTROBE(),
|
||||
.I(rx_clk_buf)
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// Always-on SISO clk needed to load/unload DDR2 I/O Regs
|
||||
//------------------------------------------------------------------
|
||||
BUFG siso_clk_bufg (
|
||||
.I(siso_clk_unbuf),
|
||||
.O(siso_clk)
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// BUFG to drive global radio_clk.
|
||||
//------------------------------------------------------------------
|
||||
BUFG radio_clk_bufg (
|
||||
.I(siso_clk2_unbuf),
|
||||
.O(radio_clk)
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// RX Frame Signal - In bank 3 LB
|
||||
//------------------------------------------------------------------
|
||||
wire rx_frame_0, rx_frame_1;
|
||||
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_frame (
|
||||
.Q0(rx_frame_1),
|
||||
.Q1(rx_frame_0),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_frame),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
reg rx_frame_d1, rx_frame_d2;
|
||||
always @(posedge siso_clk)
|
||||
{ rx_frame_d2, rx_frame_d1 } <= { rx_frame_1, 1'b0 };
|
||||
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// RX Data Bus - In bank3 both LT and LB
|
||||
//------------------------------------------------------------------
|
||||
wire [11:0] rx_i,rx_q;
|
||||
|
||||
// Bit0 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i0 (
|
||||
.Q0(rx_q[0]),
|
||||
.Q1(rx_i[0]),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[0]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit1 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i1 (
|
||||
.Q0(rx_q[1]),
|
||||
.Q1(rx_i[1]),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[1]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit2 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i2 (
|
||||
.Q0(rx_q[2]),
|
||||
.Q1(rx_i[2]),
|
||||
.C0(io_clk_lt),
|
||||
.C1(io_clk_lt_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[2]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit3 LT
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i3 (
|
||||
.Q0(rx_q[3]),
|
||||
.Q1(rx_i[3]),
|
||||
.C0(io_clk_lt),
|
||||
.C1(io_clk_lt_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[3]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit4 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i4 (
|
||||
.Q0(rx_q[4]),
|
||||
.Q1(rx_i[4]),
|
||||
.C0(io_clk_lt),
|
||||
.C1(io_clk_lt_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[4]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit5 LT
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i5 (
|
||||
.Q0(rx_q[5]),
|
||||
.Q1(rx_i[5]),
|
||||
.C0(io_clk_lt),
|
||||
.C1(io_clk_lt_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[5]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit6 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i6 (
|
||||
.Q0(rx_q[6]),
|
||||
.Q1(rx_i[6]),
|
||||
.C0(io_clk_lt),
|
||||
.C1(io_clk_lt_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[6]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit7 LT
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i7 (
|
||||
.Q0(rx_q[7]),
|
||||
.Q1(rx_i[7]),
|
||||
.C0(io_clk_lt),
|
||||
.C1(io_clk_lt_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[7]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit8 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i8 (
|
||||
.Q0(rx_q[8]),
|
||||
.Q1(rx_i[8]),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[8]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit9 LT
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i9 (
|
||||
.Q0(rx_q[9]),
|
||||
.Q1(rx_i[9]),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[9]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit10 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i10 (
|
||||
.Q0(rx_q[10]),
|
||||
.Q1(rx_i[10]),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[10]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit11 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i11 (
|
||||
.Q0(rx_q[11]),
|
||||
.Q1(rx_i[11]),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[11]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
//------------------------------------------------------------------
|
||||
//
|
||||
// De-mux I & Q onto fullrate clock.
|
||||
//
|
||||
// We grab data from the IDDR2 using negedge of siso_clk.
|
||||
// IDDR2 updates all Q pins on posedge of io_clk. siso_clk does not have aligned phase
|
||||
// with io_clk...siso_clk is always a little more delayed than io_clk.
|
||||
// This small delay is always much smaller than half a clk cycle. Thus by sampling the Q outputs
|
||||
// with negedge siso_clk we avoid any risk of a race condition (hold violation on receiveing register).
|
||||
//
|
||||
//------------------------------------------------------------------
|
||||
reg [11:0] rx_i_del, rx_q_del;
|
||||
reg [11:0] rx_i0_siso_pos;
|
||||
reg [11:0] rx_q0_siso_pos;
|
||||
reg [11:0] rx_i0_siso_neg;
|
||||
reg [11:0] rx_q0_siso_neg;
|
||||
reg [11:0] rx_i0_siso;
|
||||
reg [11:0] rx_q0_siso;
|
||||
|
||||
always @(negedge siso_clk)
|
||||
begin
|
||||
rx_i0_siso[11:0] <= rx_i[11:0];
|
||||
rx_q0_siso[11:0] <= rx_q[11:0];
|
||||
end // else: !if(rx_frame_0)
|
||||
|
||||
//------------------------------------------------------------------
|
||||
//
|
||||
// Now prepare data for crossing into radio_clk domain which is always for SISO mode (inverted) siso_clk.
|
||||
// (Note: posedge is used so that we have massive margin against a fast-path race condition
|
||||
// betwwen siso_clk and radio_clk).
|
||||
//
|
||||
//------------------------------------------------------------------
|
||||
|
||||
// This code block only relevent in SISO mode.
|
||||
always @(posedge siso_clk)
|
||||
begin
|
||||
rx_i0_siso_pos[11:0] <= rx_i0_siso[11:0];
|
||||
rx_q0_siso_pos[11:0] <= rx_q0_siso[11:0];
|
||||
end
|
||||
|
||||
assign rx_i0 = rx_i0_siso_pos;
|
||||
assign rx_q0 = rx_q0_siso_pos;
|
||||
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// TX Data Bus - In bank3 LB
|
||||
//------------------------------------------------------------------
|
||||
reg [11:0] tx_i,tx_q;
|
||||
|
||||
generate
|
||||
for(z = 0; z < 12; z = z + 1)
|
||||
begin : gen_pins
|
||||
ODDR2 #(
|
||||
.DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC"))
|
||||
oddr2 (
|
||||
.Q(tx_data[z]), .C0(io_clk_lb), .C1(io_clk_lb_b),
|
||||
.CE(1'b1), .D0(tx_i[z]), .D1(tx_q[z]), .R(1'b0), .S(1'b0));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// TX Frame Signal - In bank 3 LB
|
||||
//------------------------------------------------------------------
|
||||
ODDR2 #(
|
||||
.DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC"))
|
||||
oddr2_frame (
|
||||
.Q(tx_frame), .C0(io_clk_lb), .C1(io_clk_lb_b),
|
||||
.CE(1'b1), .D0(1'b1), .D1(1'b0), .R(1'b0), .S(1'b0));
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// TX Clock Signal - In bank 3 LB
|
||||
//------------------------------------------------------------------
|
||||
ODDR2 #(
|
||||
.DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC"))
|
||||
oddr2_clk (
|
||||
.Q(tx_clk), .C0(io_clk_lb), .C1(io_clk_lb_b),
|
||||
.CE(1'b1), .D0(1'b1), .D1(1'b0), .R(1'b0), .S(1'b0));
|
||||
|
||||
//------------------------------------------------------------------
|
||||
//
|
||||
// Mux I & Q, onto fullrate clock TX bus to AD9361
|
||||
//
|
||||
//------------------------------------------------------------------
|
||||
|
||||
always @(posedge siso_clk)
|
||||
begin
|
||||
{tx_i,tx_q} <= {tx_i0,tx_q0};
|
||||
end
|
||||
|
||||
//
|
||||
// Debug
|
||||
//
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
wire [35:0] CONTROL0;
|
||||
reg [11:0] tx_i_del_debug, tx_q_del_debug;
|
||||
reg [11:0] tx_i_debug,tx_q_debug;
|
||||
reg [11:0] tx_i0_debug,tx_q0_debug;
|
||||
reg find_radio_clk_phase_debug;
|
||||
reg find_radio_clk_phase_del_debug;
|
||||
reg tx_strobe_debug;
|
||||
reg tx_strobe_del_debug;
|
||||
|
||||
|
||||
always @(posedge siso_clk) begin
|
||||
tx_i_del_debug <= tx_i_del;
|
||||
tx_q_del_debug <= tx_q_del;
|
||||
tx_i_debug <= tx_i;
|
||||
tx_q_debug <= tx_q;
|
||||
tx_i0_debug <=tx_i0;
|
||||
tx_q0_debug <= tx_q0;
|
||||
find_radio_clk_phase_debug <= find_radio_clk_phase;
|
||||
find_radio_clk_phase_del_debug <= find_radio_clk_phase_del;
|
||||
tx_strobe_debug <= tx_strobe;
|
||||
tx_strobe_del_debug <= tx_strobe_del;
|
||||
end
|
||||
|
||||
|
||||
|
||||
chipscope_icon chipscope_icon_i0
|
||||
(
|
||||
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
|
||||
);
|
||||
|
||||
chipscope_ila_128 chipscope_ila_i0
|
||||
(
|
||||
.CONTROL(CONTROL0), // INOUT BUS [35:0]
|
||||
.CLK(siso_clk), // IN
|
||||
.TRIG0(
|
||||
{
|
||||
tx_i_del_debug[11:0],
|
||||
tx_q_del_debug[11:0],
|
||||
tx_i_debug[11:0],
|
||||
tx_q_debug[11:0],
|
||||
tx_i0_debug[11:0],
|
||||
tx_q0_debug[11:0],
|
||||
find_radio_clk_phase_debug,
|
||||
find_radio_clk_phase_del_debug,
|
||||
tx_strobe_debug,
|
||||
tx_strobe_del_debug
|
||||
}
|
||||
)
|
||||
|
||||
);
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
endmodule
|
||||
@@ -0,0 +1,278 @@
|
||||
//
|
||||
// Copyright 2015 Ettus Research, a National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
|
||||
module b205_ref_pll(
|
||||
input reset,
|
||||
input clk, // 200 MHz sample clock
|
||||
input refclk, // 40 MHz reference clock
|
||||
input ref, // PPS or 10 MHz external reference
|
||||
output reg locked,
|
||||
|
||||
// SPI lines to AD5662
|
||||
output sclk,
|
||||
output mosi,
|
||||
output sync_n
|
||||
);
|
||||
|
||||
// Base parameters
|
||||
localparam SAMPLE_CLOCK_FREQ=200_000_000;
|
||||
localparam REF_FREQ_PPS=1;
|
||||
localparam REF_FREQ_10MHZ=10_000_000;
|
||||
localparam REF_CLK_FREQ=40_000_000;
|
||||
localparam PFD_FREQ_PPS=1;
|
||||
localparam PFD_FREQ_10MHZ=10;
|
||||
|
||||
// Lock detection parameters
|
||||
localparam LOCK_TOLERANCE_PPM=1;
|
||||
localparam LOCK_MARGIN_PPS=(SAMPLE_CLOCK_FREQ/PFD_FREQ_PPS)*LOCK_TOLERANCE_PPM/1_000_000;
|
||||
localparam LOCK_MARGIN_10MHZ=(SAMPLE_CLOCK_FREQ/PFD_FREQ_10MHZ)*LOCK_TOLERANCE_PPM/1_000_000;
|
||||
|
||||
// Reference frequency detection parameters
|
||||
// References are only valid if they are +/-5ppm because that is the range of the VCTXCO
|
||||
localparam REF_PERIOD_PPS=SAMPLE_CLOCK_FREQ/REF_FREQ_PPS;
|
||||
localparam REF_PERIOD_10MHZ=SAMPLE_CLOCK_FREQ/REF_FREQ_10MHZ;
|
||||
localparam REF_PERIOD_PPS_MIN=REF_PERIOD_PPS-(REF_PERIOD_PPS*5/1_000_000)-1;
|
||||
localparam REF_PERIOD_PPS_MAX=REF_PERIOD_PPS+(REF_PERIOD_PPS*5/1_000_000)+1;
|
||||
localparam REF_PERIOD_10MHZ_MIN=REF_PERIOD_10MHZ-(REF_PERIOD_10MHZ*5/1_000_000)-1;
|
||||
localparam REF_PERIOD_10MHZ_MAX=REF_PERIOD_10MHZ+(REF_PERIOD_10MHZ*5/1_000_000)+1;
|
||||
|
||||
// R divider parameters
|
||||
localparam RDIV_PPS=REF_FREQ_PPS/PFD_FREQ_PPS;
|
||||
localparam RDIV_10MHZ=REF_FREQ_10MHZ/PFD_FREQ_10MHZ;
|
||||
|
||||
// N divider parameters (refclk is divided by 2)
|
||||
localparam NDIV_PPS=REF_CLK_FREQ/2/PFD_FREQ_PPS;
|
||||
localparam NDIV_10MHZ=REF_CLK_FREQ/2/PFD_FREQ_10MHZ;
|
||||
|
||||
// PFD parameters
|
||||
localparam PFD_PERIOD_PPS=SAMPLE_CLOCK_FREQ/PFD_FREQ_PPS;
|
||||
localparam PFD_PERIOD_10MHZ=SAMPLE_CLOCK_FREQ/PFD_FREQ_10MHZ;
|
||||
|
||||
|
||||
// Initial divide by 2 for 40 MHz clock
|
||||
// (since refclk cannot be sampled directly)
|
||||
reg refclk_div;
|
||||
always @(posedge refclk) begin
|
||||
refclk_div <= ~refclk_div;
|
||||
end
|
||||
|
||||
// flop signals into sample clock domain together
|
||||
reg [3:0] refsmp;
|
||||
reg [3:0] refclksmp;
|
||||
always @(posedge clk) begin
|
||||
refsmp <= {refsmp[2:0],ref};
|
||||
refclksmp <= {refclksmp[2:0],refclk_div};
|
||||
end
|
||||
|
||||
// rising edge detection
|
||||
wire ref_rising = (refsmp[3:2] == 2'b01);
|
||||
wire refclk_rising = (refclksmp[3:2] == 2'b01);
|
||||
|
||||
// reference frequency detection
|
||||
reg [27:0] refcnt;
|
||||
reg ref_detected;
|
||||
reg ref_is_10M;
|
||||
reg ref_is_pps;
|
||||
wire valid_ref = ref_is_10M | ref_is_pps;
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
refcnt <= 28'd0;
|
||||
ref_detected <= 1'b0;
|
||||
ref_is_10M <= 1'b0;
|
||||
ref_is_pps <= 1'b0;
|
||||
end
|
||||
else if (ref_rising) begin
|
||||
refcnt <= 28'd1;
|
||||
ref_detected <= 1'b1;
|
||||
ref_is_10M <= ((refcnt >= REF_PERIOD_10MHZ_MIN) && (refcnt <= REF_PERIOD_10MHZ_MAX));
|
||||
ref_is_pps <= ((refcnt >= REF_PERIOD_PPS_MIN) && (refcnt <= REF_PERIOD_PPS_MAX));
|
||||
end
|
||||
else if ((ref_is_10M && (refcnt > REF_PERIOD_10MHZ_MAX)) || (refcnt > REF_PERIOD_PPS_MAX)) begin
|
||||
// consider the reference lost
|
||||
refcnt <= 28'd0;
|
||||
ref_detected <= 1'b0;
|
||||
ref_is_10M <= 1'b0;
|
||||
ref_is_pps <= 1'b0;
|
||||
end
|
||||
else if (ref_detected)
|
||||
refcnt <= refcnt + 28'd1;
|
||||
end
|
||||
|
||||
// R divider
|
||||
wire [23:0] rdiv = ref_is_10M ? RDIV_10MHZ : RDIV_PPS;
|
||||
reg [23:0] rcnt;
|
||||
wire [23:0] next_rcnt = ~valid_ref ? 24'd0 : (rcnt == rdiv) ? 24'd1 : rcnt + 1'b1;
|
||||
reg r_rising;
|
||||
always @(posedge clk) begin
|
||||
if (ref_rising)
|
||||
rcnt <= next_rcnt;
|
||||
r_rising <= (ref_rising && ((ref_is_10M && (rcnt == rdiv)) || ref_is_pps));
|
||||
end
|
||||
|
||||
// N divider
|
||||
// Enable on rising edge of R after valid_ref
|
||||
// is asserted so R and N signals start aligned.
|
||||
// Disable if reference lost.
|
||||
wire [25:0] ndiv = ref_is_10M ? NDIV_10MHZ : NDIV_PPS;
|
||||
reg [25:0] ncnt;
|
||||
wire [25:0] next_ncnt = ~valid_ref ? 26'd0 : ncnt == ndiv ? 26'd1 : ncnt + 1'b1;
|
||||
reg n_rising;
|
||||
always @(posedge clk) begin
|
||||
if (refclk_rising)
|
||||
ncnt <= next_ncnt;
|
||||
n_rising <= (refclk_rising && (ncnt == ndiv));
|
||||
end
|
||||
|
||||
// Frequency Counter
|
||||
wire signed [28:0] period = ref_is_10M ? PFD_PERIOD_10MHZ : PFD_PERIOD_PPS;
|
||||
reg signed [28:0] r_period_cnt;
|
||||
reg signed [28:0] freq_err;
|
||||
always @(posedge clk) begin
|
||||
if (reset | ~valid_ref) begin
|
||||
r_period_cnt <= 28'd0;
|
||||
freq_err <= 29'sd0;
|
||||
end
|
||||
else if (r_rising) begin
|
||||
r_period_cnt <= 28'd1;
|
||||
freq_err <= period - r_period_cnt;
|
||||
end
|
||||
else
|
||||
r_period_cnt <= r_period_cnt + 28'd1;
|
||||
end
|
||||
|
||||
// Phase Counter
|
||||
reg signed [28:0] lead_cnt;
|
||||
reg lead_cnt_ena;
|
||||
reg signed [28:0] lead;
|
||||
always @(posedge clk) begin
|
||||
// Count how much N leads R
|
||||
// The count is negative because it measures
|
||||
// how much the VCTCXO must be slowed down.
|
||||
if (~valid_ref | n_rising) begin
|
||||
lead_cnt <= 29'sd0;
|
||||
lead_cnt_ena <= 1'b1;
|
||||
if (r_rising)
|
||||
lead <= 29'sd0;
|
||||
end
|
||||
else if (r_rising) begin
|
||||
if (lead_cnt_ena)
|
||||
lead <= lead_cnt - 29'sd1;
|
||||
else begin
|
||||
// R rising with no preceding N rising.
|
||||
// N has changed from leading to lagging R,
|
||||
// but we don't yet know by how much so
|
||||
// assume 1.
|
||||
lead <= 29'sd1;
|
||||
end
|
||||
lead_cnt_ena <= 1'b0;
|
||||
end
|
||||
else if (lead_cnt_ena)
|
||||
lead_cnt <= lead_cnt - 29'sd1;
|
||||
end
|
||||
|
||||
// PFD State Machine
|
||||
localparam MEASURE=4'd0;
|
||||
localparam CAPTURE=4'd1;
|
||||
localparam CAPTURE_LAG=4'd2;
|
||||
localparam CAPTURE_LEAD=4'd3;
|
||||
localparam CALCULATE_ERROR=4'd4;
|
||||
localparam CALCULATE_10M_GAIN=4'd5;
|
||||
localparam CALCULATE_ADJUSTMENT=4'd6;
|
||||
localparam CALCULATE_OUTPUT_VALUE=4'd7;
|
||||
localparam APPLY_OUTPUT_VALUE=4'd8;
|
||||
reg [3:0] state;
|
||||
reg [15:0] daco = 16'd32767;
|
||||
wire signed [28:0] lock_margin = ref_is_10M ? LOCK_MARGIN_10MHZ : LOCK_MARGIN_PPS;
|
||||
wire signed [28:0] lag = lead + period;
|
||||
reg signed [28:0] phase_err;
|
||||
reg signed [28:0] err;
|
||||
reg signed [28:0] shift;
|
||||
reg signed [28:0] adj;
|
||||
wire signed [28:0] dacv = {13'd0, daco};
|
||||
reg signed [28:0] sum;
|
||||
reg [2:0] ld;
|
||||
always @(posedge clk) begin
|
||||
if (reset || ~valid_ref) begin
|
||||
state <= MEASURE;
|
||||
daco <= 16'd32767;
|
||||
err <= 29'sd0;
|
||||
shift <= 29'sd0;
|
||||
adj <= 29'sd0;
|
||||
ld <= 3'd0;
|
||||
end
|
||||
else begin
|
||||
case(state)
|
||||
MEASURE: begin
|
||||
if (r_rising)
|
||||
state <= CAPTURE;
|
||||
end
|
||||
CAPTURE: begin
|
||||
if (lag < -lead)
|
||||
state <= CAPTURE_LAG;
|
||||
else
|
||||
state <= CAPTURE_LEAD;
|
||||
end
|
||||
CAPTURE_LAG: begin
|
||||
phase_err <= lag;
|
||||
ld <= {ld[1:0], (lag <= lock_margin)};
|
||||
state <= CALCULATE_ERROR;
|
||||
end
|
||||
CAPTURE_LEAD: begin
|
||||
phase_err <= lead;
|
||||
ld <= {ld[1:0], (-lead <= lock_margin)};
|
||||
state <= CALCULATE_ERROR;
|
||||
end
|
||||
CALCULATE_ERROR: begin
|
||||
err <= phase_err + freq_err;
|
||||
state <= ref_is_10M ? CALCULATE_10M_GAIN : CALCULATE_ADJUSTMENT;
|
||||
end
|
||||
CALCULATE_10M_GAIN: begin
|
||||
shift <= (err < -7 || err > 7) ? 7 : (err < 0 ? -err : err);
|
||||
state <= CALCULATE_ADJUSTMENT;
|
||||
end
|
||||
CALCULATE_ADJUSTMENT: begin
|
||||
// The VCTCXO is +/-5 ppm from 0.3V to 1.5V and the DAC is 16 bits,
|
||||
// which works out to 0.000228885 ppm per DAC unit.
|
||||
// The 200 MHz sampling clock means each unit of error is 0.005 ppm,
|
||||
// which works out to 21.845 DAC units to correct each unit of error.
|
||||
// Theory is nice, but the proportional and integral gains used here
|
||||
// were determined through manual tuning.
|
||||
if (ref_is_10M)
|
||||
adj <= (err <<< shift);
|
||||
else
|
||||
adj <= (err <<< 4) - err;
|
||||
state <= CALCULATE_OUTPUT_VALUE;
|
||||
end
|
||||
CALCULATE_OUTPUT_VALUE: begin
|
||||
sum <= dacv + adj;
|
||||
state <= APPLY_OUTPUT_VALUE;
|
||||
end
|
||||
APPLY_OUTPUT_VALUE: begin
|
||||
// Clip and apply
|
||||
if (sum < 29'sd0)
|
||||
daco <= 16'd0;
|
||||
else if (sum > 29'sd65535)
|
||||
daco <= 16'd65535;
|
||||
else
|
||||
daco <= sum[15:0];
|
||||
state <= MEASURE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
locked <= (ld == 3'b111);
|
||||
|
||||
ad5662_auto_spi dac
|
||||
(
|
||||
.clk(clk),
|
||||
.dat(daco),
|
||||
.sclk(sclk),
|
||||
.mosi(mosi),
|
||||
.sync_n(sync_n)
|
||||
);
|
||||
endmodule
|
||||
@@ -0,0 +1,5 @@
|
||||
/tmp
|
||||
/_xmsgs
|
||||
/*.log
|
||||
/*.gise
|
||||
/*.xise
|
||||
@@ -0,0 +1,29 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 b205_clk_gen
|
||||
RECTANGLE Normal 32 32 576 1088
|
||||
LINE Normal 0 80 32 80
|
||||
PIN 0 80 LEFT 36
|
||||
PINATTR PinName clk_in1
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 432 32 432
|
||||
PIN 0 432 LEFT 36
|
||||
PINATTR PinName reset
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 608 80 576 80
|
||||
PIN 608 80 RIGHT 36
|
||||
PINATTR PinName clk_out1
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 608 176 576 176
|
||||
PIN 608 176 RIGHT 36
|
||||
PINATTR PinName clk_out2
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 608 272 576 272
|
||||
PIN 608 272 RIGHT 36
|
||||
PINATTR PinName clk_out3
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 608 976 576 976
|
||||
PIN 608 976 RIGHT 36
|
||||
PINATTR PinName locked
|
||||
PINATTR Polarity OUT
|
||||
|
||||
Executable
+59
@@ -0,0 +1,59 @@
|
||||
# file: b205_clk_gen.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps;
|
||||
|
||||
|
||||
# FALSE PATH constraints
|
||||
PIN "RESET" TIG;
|
||||
|
||||
Executable
+158
@@ -0,0 +1,158 @@
|
||||
// file: b205_clk_gen.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1____40.000______0.000______50.0______312.078____259.584
|
||||
// CLK_OUT2___100.000______0.000______50.0______255.594____259.584
|
||||
// CLK_OUT3___200.000______0.000______50.0______225.630____259.584
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary__________40.000____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "b205_clk_gen,clk_wiz_v3_6,{component_name=b205_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
|
||||
module b205_clk_gen
|
||||
(// Clock in ports
|
||||
input CLK_IN1_40,
|
||||
// Clock out ports
|
||||
output CLK_OUT1_40_int,
|
||||
output CLK_OUT2_100_bus,
|
||||
output CLK_OUT3_200_ref_pll,
|
||||
// Status and control signals
|
||||
input RESET,
|
||||
output LOCKED
|
||||
);
|
||||
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
IBUFG clkin1_buf
|
||||
(.O (clkin1),
|
||||
.I (CLK_IN1_40));
|
||||
|
||||
|
||||
// Clocking primitive
|
||||
//------------------------------------
|
||||
// Instantiation of the PLL primitive
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire clkfbout;
|
||||
wire clkfbout_buf;
|
||||
wire clkout3_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
|
||||
PLL_BASE
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLK_FEEDBACK ("CLKFBOUT"),
|
||||
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT (10),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKOUT0_DIVIDE (10),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT1_DIVIDE (4),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.CLKOUT2_DIVIDE (2),
|
||||
.CLKOUT2_PHASE (0.000),
|
||||
.CLKOUT2_DUTY_CYCLE (0.500),
|
||||
.CLKIN_PERIOD (25.0),
|
||||
.REF_JITTER (0.010))
|
||||
pll_base_inst
|
||||
// Output clocks
|
||||
(.CLKFBOUT (clkfbout),
|
||||
.CLKOUT0 (clkout0),
|
||||
.CLKOUT1 (clkout1),
|
||||
.CLKOUT2 (clkout2),
|
||||
.CLKOUT3 (clkout3_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
// Status and control signals
|
||||
.LOCKED (LOCKED),
|
||||
.RST (RESET),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf),
|
||||
.CLKIN (clkin1));
|
||||
|
||||
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf),
|
||||
.I (clkfbout));
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (CLK_OUT1_40_int),
|
||||
.I (clkout0));
|
||||
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (CLK_OUT2_100_bus),
|
||||
.I (clkout1));
|
||||
|
||||
BUFG clkout3_buf
|
||||
(.O (CLK_OUT3_200_ref_pll),
|
||||
.I (clkout2));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
Executable
+82
@@ -0,0 +1,82 @@
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1____40.000______0.000______50.0______312.078____259.584
|
||||
// CLK_OUT2___100.000______0.000______50.0______255.594____259.584
|
||||
// CLK_OUT3___200.000______0.000______50.0______225.630____259.584
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary__________40.000____________0.010
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
b205_clk_gen instance_name
|
||||
(// Clock in ports
|
||||
.CLK_IN1_40(CLK_IN1_40), // IN
|
||||
// Clock out ports
|
||||
.CLK_OUT1_40_int(CLK_OUT1_40_int), // OUT
|
||||
.CLK_OUT2_100_bus(CLK_OUT2_100_bus), // OUT
|
||||
.CLK_OUT3_200_ref_pll(CLK_OUT3_200_ref_pll), // OUT
|
||||
// Status and control signals
|
||||
.RESET(RESET),// IN
|
||||
.LOCKED(LOCKED)); // OUT
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
@@ -0,0 +1,269 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.7
|
||||
# Date: Tue Jul 14 00:18:05 2015
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:clk_wiz:3.6
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc6slx75
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = csg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -3
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET calc_done=DONE
|
||||
CSET clk_in_sel_port=CLK_IN_SEL
|
||||
CSET clk_out1_port=CLK_OUT1_40_int
|
||||
CSET clk_out1_use_fine_ps_gui=false
|
||||
CSET clk_out2_port=CLK_OUT2_100_bus
|
||||
CSET clk_out2_use_fine_ps_gui=false
|
||||
CSET clk_out3_port=CLK_OUT3_200_ref_pll
|
||||
CSET clk_out3_use_fine_ps_gui=false
|
||||
CSET clk_out4_port=CLK_OUT4_gpif
|
||||
CSET clk_out4_use_fine_ps_gui=false
|
||||
CSET clk_out5_port=CLK_OUT5
|
||||
CSET clk_out5_use_fine_ps_gui=false
|
||||
CSET clk_out6_port=CLK_OUT6
|
||||
CSET clk_out6_use_fine_ps_gui=false
|
||||
CSET clk_out7_port=CLK_OUT7
|
||||
CSET clk_out7_use_fine_ps_gui=false
|
||||
CSET clk_valid_port=CLK_VALID
|
||||
CSET clkfb_in_n_port=CLKFB_IN_N
|
||||
CSET clkfb_in_p_port=CLKFB_IN_P
|
||||
CSET clkfb_in_port=CLKFB_IN
|
||||
CSET clkfb_in_signaling=SINGLE
|
||||
CSET clkfb_out_n_port=CLKFB_OUT_N
|
||||
CSET clkfb_out_p_port=CLKFB_OUT_P
|
||||
CSET clkfb_out_port=CLKFB_OUT
|
||||
CSET clkfb_stopped_port=CLKFB_STOPPED
|
||||
CSET clkin1_jitter_ps=250.0
|
||||
CSET clkin1_ui_jitter=0.010
|
||||
CSET clkin2_jitter_ps=100.0
|
||||
CSET clkin2_ui_jitter=0.010
|
||||
CSET clkout1_drives=BUFG
|
||||
CSET clkout1_requested_duty_cycle=50.000
|
||||
CSET clkout1_requested_out_freq=40.000
|
||||
CSET clkout1_requested_phase=0.000
|
||||
CSET clkout2_drives=BUFG
|
||||
CSET clkout2_requested_duty_cycle=50.000
|
||||
CSET clkout2_requested_out_freq=100.000
|
||||
CSET clkout2_requested_phase=0.000
|
||||
CSET clkout2_used=true
|
||||
CSET clkout3_drives=BUFG
|
||||
CSET clkout3_requested_duty_cycle=50.000
|
||||
CSET clkout3_requested_out_freq=200.000
|
||||
CSET clkout3_requested_phase=0.000
|
||||
CSET clkout3_used=true
|
||||
CSET clkout4_drives=BUFG
|
||||
CSET clkout4_requested_duty_cycle=50.000
|
||||
CSET clkout4_requested_out_freq=80.000
|
||||
CSET clkout4_requested_phase=0.000
|
||||
CSET clkout4_used=false
|
||||
CSET clkout5_drives=BUFG
|
||||
CSET clkout5_requested_duty_cycle=50.000
|
||||
CSET clkout5_requested_out_freq=100.000
|
||||
CSET clkout5_requested_phase=0.000
|
||||
CSET clkout5_used=false
|
||||
CSET clkout6_drives=BUFG
|
||||
CSET clkout6_requested_duty_cycle=50.000
|
||||
CSET clkout6_requested_out_freq=100.000
|
||||
CSET clkout6_requested_phase=0.000
|
||||
CSET clkout6_used=false
|
||||
CSET clkout7_drives=BUFG
|
||||
CSET clkout7_requested_duty_cycle=50.000
|
||||
CSET clkout7_requested_out_freq=100.000
|
||||
CSET clkout7_requested_phase=0.000
|
||||
CSET clkout7_used=false
|
||||
CSET clock_mgr_type=AUTO
|
||||
CSET component_name=b205_clk_gen
|
||||
CSET daddr_port=DADDR
|
||||
CSET dclk_port=DCLK
|
||||
CSET dcm_clk_feedback=1X
|
||||
CSET dcm_clk_out1_port=CLK0
|
||||
CSET dcm_clk_out2_port=CLKFX
|
||||
CSET dcm_clk_out3_port=CLKFX
|
||||
CSET dcm_clk_out4_port=CLK0
|
||||
CSET dcm_clk_out5_port=CLK0
|
||||
CSET dcm_clk_out6_port=CLK0
|
||||
CSET dcm_clkdv_divide=2.0
|
||||
CSET dcm_clkfx_divide=2
|
||||
CSET dcm_clkfx_multiply=5
|
||||
CSET dcm_clkgen_clk_out1_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out2_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out3_port=CLKFX
|
||||
CSET dcm_clkgen_clkfx_divide=1
|
||||
CSET dcm_clkgen_clkfx_md_max=0.000
|
||||
CSET dcm_clkgen_clkfx_multiply=4
|
||||
CSET dcm_clkgen_clkfxdv_divide=2
|
||||
CSET dcm_clkgen_clkin_period=10.000
|
||||
CSET dcm_clkgen_notes=None
|
||||
CSET dcm_clkgen_spread_spectrum=NONE
|
||||
CSET dcm_clkgen_startup_wait=false
|
||||
CSET dcm_clkin_divide_by_2=false
|
||||
CSET dcm_clkin_period=25.000
|
||||
CSET dcm_clkout_phase_shift=NONE
|
||||
CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
|
||||
CSET dcm_notes=None
|
||||
CSET dcm_phase_shift=0
|
||||
CSET dcm_pll_cascade=NONE
|
||||
CSET dcm_startup_wait=false
|
||||
CSET den_port=DEN
|
||||
CSET din_port=DIN
|
||||
CSET dout_port=DOUT
|
||||
CSET drdy_port=DRDY
|
||||
CSET dwe_port=DWE
|
||||
CSET feedback_source=FDBK_AUTO
|
||||
CSET in_freq_units=Units_MHz
|
||||
CSET in_jitter_units=Units_UI
|
||||
CSET input_clk_stopped_port=INPUT_CLK_STOPPED
|
||||
CSET jitter_options=UI
|
||||
CSET jitter_sel=No_Jitter
|
||||
CSET locked_port=LOCKED
|
||||
CSET mmcm_bandwidth=OPTIMIZED
|
||||
CSET mmcm_clkfbout_mult_f=4.000
|
||||
CSET mmcm_clkfbout_phase=0.000
|
||||
CSET mmcm_clkfbout_use_fine_ps=false
|
||||
CSET mmcm_clkin1_period=10.000
|
||||
CSET mmcm_clkin2_period=10.000
|
||||
CSET mmcm_clkout0_divide_f=4.000
|
||||
CSET mmcm_clkout0_duty_cycle=0.500
|
||||
CSET mmcm_clkout0_phase=0.000
|
||||
CSET mmcm_clkout0_use_fine_ps=false
|
||||
CSET mmcm_clkout1_divide=1
|
||||
CSET mmcm_clkout1_duty_cycle=0.500
|
||||
CSET mmcm_clkout1_phase=0.000
|
||||
CSET mmcm_clkout1_use_fine_ps=false
|
||||
CSET mmcm_clkout2_divide=1
|
||||
CSET mmcm_clkout2_duty_cycle=0.500
|
||||
CSET mmcm_clkout2_phase=0.000
|
||||
CSET mmcm_clkout2_use_fine_ps=false
|
||||
CSET mmcm_clkout3_divide=1
|
||||
CSET mmcm_clkout3_duty_cycle=0.500
|
||||
CSET mmcm_clkout3_phase=0.000
|
||||
CSET mmcm_clkout3_use_fine_ps=false
|
||||
CSET mmcm_clkout4_cascade=false
|
||||
CSET mmcm_clkout4_divide=1
|
||||
CSET mmcm_clkout4_duty_cycle=0.500
|
||||
CSET mmcm_clkout4_phase=0.000
|
||||
CSET mmcm_clkout4_use_fine_ps=false
|
||||
CSET mmcm_clkout5_divide=1
|
||||
CSET mmcm_clkout5_duty_cycle=0.500
|
||||
CSET mmcm_clkout5_phase=0.000
|
||||
CSET mmcm_clkout5_use_fine_ps=false
|
||||
CSET mmcm_clkout6_divide=1
|
||||
CSET mmcm_clkout6_duty_cycle=0.500
|
||||
CSET mmcm_clkout6_phase=0.000
|
||||
CSET mmcm_clkout6_use_fine_ps=false
|
||||
CSET mmcm_clock_hold=false
|
||||
CSET mmcm_compensation=ZHOLD
|
||||
CSET mmcm_divclk_divide=1
|
||||
CSET mmcm_notes=None
|
||||
CSET mmcm_ref_jitter1=0.010
|
||||
CSET mmcm_ref_jitter2=0.010
|
||||
CSET mmcm_startup_wait=false
|
||||
CSET num_out_clks=3
|
||||
CSET override_dcm=false
|
||||
CSET override_dcm_clkgen=false
|
||||
CSET override_mmcm=false
|
||||
CSET override_pll=false
|
||||
CSET platform=lin64
|
||||
CSET pll_bandwidth=OPTIMIZED
|
||||
CSET pll_clk_feedback=CLKFBOUT
|
||||
CSET pll_clkfbout_mult=10
|
||||
CSET pll_clkfbout_phase=0.000
|
||||
CSET pll_clkin_period=25.0
|
||||
CSET pll_clkout0_divide=10
|
||||
CSET pll_clkout0_duty_cycle=0.500
|
||||
CSET pll_clkout0_phase=0.000
|
||||
CSET pll_clkout1_divide=4
|
||||
CSET pll_clkout1_duty_cycle=0.500
|
||||
CSET pll_clkout1_phase=0.000
|
||||
CSET pll_clkout2_divide=2
|
||||
CSET pll_clkout2_duty_cycle=0.500
|
||||
CSET pll_clkout2_phase=0.000
|
||||
CSET pll_clkout3_divide=5
|
||||
CSET pll_clkout3_duty_cycle=0.500
|
||||
CSET pll_clkout3_phase=0.000
|
||||
CSET pll_clkout4_divide=1
|
||||
CSET pll_clkout4_duty_cycle=0.500
|
||||
CSET pll_clkout4_phase=0.000
|
||||
CSET pll_clkout5_divide=1
|
||||
CSET pll_clkout5_duty_cycle=0.500
|
||||
CSET pll_clkout5_phase=0.000
|
||||
CSET pll_compensation=SYSTEM_SYNCHRONOUS
|
||||
CSET pll_divclk_divide=1
|
||||
CSET pll_notes=None
|
||||
CSET pll_ref_jitter=0.010
|
||||
CSET power_down_port=POWER_DOWN
|
||||
CSET prim_in_freq=40.000
|
||||
CSET prim_in_jitter=0.010
|
||||
CSET prim_source=Single_ended_clock_capable_pin
|
||||
CSET primary_port=CLK_IN1_40
|
||||
CSET primitive=MMCM
|
||||
CSET primtype_sel=PLL_BASE
|
||||
CSET psclk_port=PSCLK
|
||||
CSET psdone_port=PSDONE
|
||||
CSET psen_port=PSEN
|
||||
CSET psincdec_port=PSINCDEC
|
||||
CSET relative_inclk=REL_PRIMARY
|
||||
CSET reset_port=RESET
|
||||
CSET secondary_in_freq=100.000
|
||||
CSET secondary_in_jitter=0.010
|
||||
CSET secondary_port=CLK_IN2
|
||||
CSET secondary_source=Single_ended_clock_capable_pin
|
||||
CSET ss_mod_freq=250
|
||||
CSET ss_mode=CENTER_HIGH
|
||||
CSET status_port=STATUS
|
||||
CSET summary_strings=empty
|
||||
CSET use_clk_valid=false
|
||||
CSET use_clkfb_stopped=false
|
||||
CSET use_dyn_phase_shift=false
|
||||
CSET use_dyn_reconfig=false
|
||||
CSET use_freeze=false
|
||||
CSET use_freq_synth=true
|
||||
CSET use_inclk_stopped=false
|
||||
CSET use_inclk_switchover=false
|
||||
CSET use_locked=true
|
||||
CSET use_max_i_jitter=false
|
||||
CSET use_min_o_jitter=false
|
||||
CSET use_min_power=false
|
||||
CSET use_phase_alignment=true
|
||||
CSET use_power_down=false
|
||||
CSET use_reset=true
|
||||
CSET use_spread_spectrum=false
|
||||
CSET use_spread_spectrum_1=false
|
||||
CSET use_status=false
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-05-10T12:44:55Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 14fd4cf9
|
||||
Executable
+67
@@ -0,0 +1,67 @@
|
||||
# file: b205_clk_gen.xdc
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
create_clock -name CLK_IN1 -period 25.0 [get_ports CLK_IN1]
|
||||
set_propagated_clock CLK_IN1
|
||||
set_input_jitter CLK_IN1 0.25
|
||||
|
||||
set_false_path -from [get_ports "RESET"]
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
# automatically propogated by the tools
|
||||
# However, if you'd like to use them for module level testing, you
|
||||
# can copy them into your module level timing checks
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
@@ -0,0 +1,184 @@
|
||||
CHANGE LOG for LogiCORE Clocking Wizard V3.6
|
||||
|
||||
Release Date: June 19, 2013
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
|
||||
|
||||
................................................................................
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
|
||||
|
||||
Zynq-7000 devices
|
||||
Zynq-7000
|
||||
Defense Grade Zynq-7000Q (XQ)
|
||||
|
||||
|
||||
All Virtex-6 devices
|
||||
|
||||
|
||||
All Spartan-6 devices
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- Spread Spectrum support for 7 series MMCME2
|
||||
|
||||
- ISE 14.2 software support
|
||||
|
||||
................................................................................
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
Resolved issue with example design becoming core top in planAhead
|
||||
|
||||
Resolved issue with Virtex6 MMCM instantiation for VHDL project
|
||||
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
|
||||
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
|
||||
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
|
||||
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
|
||||
01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
|
||||
06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
|
||||
03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
|
||||
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
|
||||
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
|
||||
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
|
||||
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
|
||||
04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
@@ -0,0 +1,184 @@
|
||||
CHANGE LOG for LogiCORE Clocking Wizard V3.6
|
||||
|
||||
Release Date: June 19, 2013
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
|
||||
|
||||
................................................................................
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
|
||||
|
||||
Zynq-7000 devices
|
||||
Zynq-7000
|
||||
Defense Grade Zynq-7000Q (XQ)
|
||||
|
||||
|
||||
All Virtex-6 devices
|
||||
|
||||
|
||||
All Spartan-6 devices
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- Spread Spectrum support for 7 series MMCME2
|
||||
|
||||
- ISE 14.2 software support
|
||||
|
||||
................................................................................
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
Resolved issue with example design becoming core top in planAhead
|
||||
|
||||
Resolved issue with Virtex6 MMCM instantiation for VHDL project
|
||||
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
|
||||
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
|
||||
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
|
||||
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
|
||||
01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
|
||||
06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
|
||||
03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
|
||||
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
|
||||
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
|
||||
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
|
||||
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
|
||||
04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
@@ -0,0 +1,195 @@
|
||||
<HTML>
|
||||
<HEAD>
|
||||
<TITLE>clk_wiz_v3_6_vinfo</TITLE>
|
||||
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
|
||||
</HEAD>
|
||||
<BODY>
|
||||
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
|
||||
CHANGE LOG for LogiCORE Clocking Wizard V3.6
|
||||
|
||||
Release Date: June 19, 2013
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
|
||||
|
||||
For system requirements:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
<A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
|
||||
|
||||
Zynq-7000 devices
|
||||
Zynq-7000
|
||||
Defense Grade Zynq-7000Q (XQ)
|
||||
|
||||
|
||||
All Virtex-6 devices
|
||||
|
||||
|
||||
All Spartan-6 devices
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- Spread Spectrum support for 7 series MMCME2
|
||||
|
||||
- ISE 14.2 software support
|
||||
|
||||
................................................................................
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
Resolved issue with example design becoming core top in planAhead
|
||||
|
||||
Resolved issue with Virtex6 MMCM instantiation for VHDL project
|
||||
Please refer to AR 50719 - <A HREF="http://www.xilinx.com/support/answers/50719.htm">www.xilinx.com/support/answers/50719.htm</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes Guide
|
||||
located at
|
||||
|
||||
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
|
||||
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
|
||||
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
|
||||
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
|
||||
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
|
||||
01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
|
||||
06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
|
||||
03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
|
||||
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
|
||||
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
|
||||
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
|
||||
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
|
||||
04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
</FONT>
|
||||
</PRE>
|
||||
</BODY>
|
||||
</HTML>
|
||||
Binary file not shown.
@@ -0,0 +1,60 @@
|
||||
# file: b205_clk_gen_exdes.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps;
|
||||
|
||||
|
||||
# FALSE PATH constraints
|
||||
PIN "COUNTER_RESET" TIG;
|
||||
PIN "RESET" TIG;
|
||||
|
||||
@@ -0,0 +1,178 @@
|
||||
// file: b205_clk_gen_exdes.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Clocking wizard example design
|
||||
//----------------------------------------------------------------------------
|
||||
// This example design instantiates the created clocking network, where each
|
||||
// output clock drives a counter. The high bit of each counter is ported.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module b205_clk_gen_exdes
|
||||
#(
|
||||
parameter TCQ = 100
|
||||
)
|
||||
(// Clock in ports
|
||||
input CLK_IN1,
|
||||
// Reset that only drives logic in example design
|
||||
input COUNTER_RESET,
|
||||
output [3:1] CLK_OUT,
|
||||
// High bits of counters driven by clocks
|
||||
output [3:1] COUNT,
|
||||
// Status and control signals
|
||||
input RESET,
|
||||
output LOCKED
|
||||
);
|
||||
|
||||
// Parameters for the counters
|
||||
//-------------------------------
|
||||
// Counter width
|
||||
localparam C_W = 16;
|
||||
// Number of counters
|
||||
localparam NUM_C = 3;
|
||||
genvar count_gen;
|
||||
// When the clock goes out of lock, reset the counters
|
||||
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
|
||||
|
||||
reg [NUM_C:1] rst_sync;
|
||||
reg [NUM_C:1] rst_sync_int;
|
||||
reg [NUM_C:1] rst_sync_int1;
|
||||
reg [NUM_C:1] rst_sync_int2;
|
||||
|
||||
|
||||
// Declare the clocks and counters
|
||||
wire [NUM_C:1] clk_int;
|
||||
wire [NUM_C:1] clk_n;
|
||||
wire [NUM_C:1] clk;
|
||||
reg [C_W-1:0] counter [NUM_C:1];
|
||||
|
||||
// Instantiation of the clocking network
|
||||
//--------------------------------------
|
||||
b205_clk_gen clknetwork
|
||||
(// Clock in ports
|
||||
.CLK_IN1_40 (CLK_IN1),
|
||||
// Clock out ports
|
||||
.CLK_OUT1_40_int (clk_int[1]),
|
||||
.CLK_OUT2_100_bus (clk_int[2]),
|
||||
.CLK_OUT3_200_ref_pll (clk_int[3]),
|
||||
// Status and control signals
|
||||
.RESET (RESET),
|
||||
.LOCKED (LOCKED));
|
||||
|
||||
genvar clk_out_pins;
|
||||
|
||||
generate
|
||||
for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1)
|
||||
begin: gen_outclk_oddr
|
||||
assign clk_n[clk_out_pins] = ~clk[clk_out_pins];
|
||||
|
||||
ODDR2 clkout_oddr
|
||||
(.Q (CLK_OUT[clk_out_pins]),
|
||||
.C0 (clk[clk_out_pins]),
|
||||
.C1 (clk_n[clk_out_pins]),
|
||||
.CE (1'b1),
|
||||
.D0 (1'b1),
|
||||
.D1 (1'b0),
|
||||
.R (1'b0),
|
||||
.S (1'b0));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Connect the output clocks to the design
|
||||
//-----------------------------------------
|
||||
assign clk[1] = clk_int[1];
|
||||
assign clk[2] = clk_int[2];
|
||||
assign clk[3] = clk_int[3];
|
||||
|
||||
|
||||
// Reset synchronizer
|
||||
//-----------------------------------
|
||||
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
|
||||
always @(posedge reset_int or posedge clk[count_gen]) begin
|
||||
if (reset_int) begin
|
||||
rst_sync[count_gen] <= 1'b1;
|
||||
rst_sync_int[count_gen]<= 1'b1;
|
||||
rst_sync_int1[count_gen]<= 1'b1;
|
||||
rst_sync_int2[count_gen]<= 1'b1;
|
||||
end
|
||||
else begin
|
||||
rst_sync[count_gen] <= 1'b0;
|
||||
rst_sync_int[count_gen] <= rst_sync[count_gen];
|
||||
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
|
||||
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// Output clock sampling
|
||||
//-----------------------------------
|
||||
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
|
||||
|
||||
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
|
||||
if (rst_sync_int2[count_gen]) begin
|
||||
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
|
||||
end else begin
|
||||
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
|
||||
end
|
||||
end
|
||||
// alias the high bit of each counter to the corresponding
|
||||
// bit in the output bus
|
||||
assign COUNT[count_gen] = counter[count_gen][C_W-1];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,69 @@
|
||||
# file: b205_clk_gen_exdes.xdc
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
create_clock -name CLK_IN1 -period 25.0 [get_ports CLK_IN1]
|
||||
set_propagated_clock CLK_IN1
|
||||
set_input_jitter CLK_IN1 0.25
|
||||
|
||||
# FALSE PATH constraint added on COUNTER_RESET
|
||||
set_false_path -from [get_ports "COUNTER_RESET"]
|
||||
set_false_path -from [get_ports "RESET"]
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
# automatically propogated by the tools
|
||||
# However, if you'd like to use them for module level testing, you
|
||||
# can copy them into your module level timing checks
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
@@ -0,0 +1,90 @@
|
||||
REM file: implement.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM -----------------------------------------------------------------------------
|
||||
REM Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
REM -----------------------------------------------------------------------------
|
||||
|
||||
REM Clean up the results directory
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
|
||||
REM Copy unisim_comp.v file to results directory
|
||||
copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
|
||||
|
||||
REM Synthesize the Verilog Wrapper Files
|
||||
echo 'Synthesizing Clocking Wizard design with XST'
|
||||
xst -ifn xst.scr
|
||||
move b205_clk_gen_exdes.ngc results\
|
||||
|
||||
REM Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
copy ..\example_design\b205_clk_gen_exdes.ucf results\
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
ngdbuild -uc b205_clk_gen_exdes.ucf b205_clk_gen_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map -timing -pr b b205_clk_gen_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par -w mapped.ncd routed mapped.pcf
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed -o routed mapped.pcf
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level model for the clocking wizard example design'
|
||||
netgen -ofmt verilog -sim -sdf_anno false -tm b205_clk_gen_exdes -w routed.ncd routed.v
|
||||
cd ..
|
||||
|
||||
@@ -0,0 +1,91 @@
|
||||
#!/bin/sh
|
||||
# file: implement.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
# Clean up the results directory
|
||||
rm -rf results
|
||||
mkdir results
|
||||
|
||||
# Copy unisim_comp.v file to results directory
|
||||
cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
|
||||
|
||||
# Synthesize the Verilog Wrapper Files
|
||||
echo 'Synthesizing Clocking Wizard design with XST'
|
||||
xst -ifn xst.scr
|
||||
mv b205_clk_gen_exdes.ngc results/
|
||||
|
||||
# Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
cp ../example_design/b205_clk_gen_exdes.ucf results/
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
ngdbuild -uc b205_clk_gen_exdes.ucf b205_clk_gen_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map -timing b205_clk_gen_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par -w mapped.ncd routed mapped.pcf
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed -o routed mapped.pcf
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level model for the clocking wizard example design'
|
||||
netgen -ofmt verilog -sim -sdf_anno false -tm b205_clk_gen_exdes -w routed.ncd routed.v
|
||||
|
||||
cd ..
|
||||
@@ -0,0 +1,58 @@
|
||||
REM file: planAhead_ise.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM-----------------------------------------------------------------------------
|
||||
REM Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
REM-----------------------------------------------------------------------------
|
||||
|
||||
del \f results
|
||||
mkdir results
|
||||
cd results
|
||||
|
||||
planAhead -mode batch -source ..\planAhead_ise.tcl
|
||||
@@ -0,0 +1,59 @@
|
||||
#!/bin/sh
|
||||
# file: planAhead_ise.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
rm -rf results
|
||||
mkdir results
|
||||
cd results
|
||||
|
||||
planAhead -mode batch -source ../planAhead_ise.tcl
|
||||
@@ -0,0 +1,78 @@
|
||||
# file: planAhead_ise.tcl
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
set projDir [file dirname [info script]]
|
||||
set projName b205_clk_gen
|
||||
set topName b205_clk_gen_exdes
|
||||
set device xc6slx75csg484-3
|
||||
|
||||
create_project $projName $projDir/results/$projName -part $device
|
||||
|
||||
set_property design_mode RTL [get_filesets sources_1]
|
||||
|
||||
## Source files
|
||||
#set verilogSources [glob $srcDir/*.v]
|
||||
import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/b205_clk_gen_exdes.v
|
||||
import_files -fileset [get_filesets sources_1] -force -norecurse ../../../b205_clk_gen.v
|
||||
|
||||
|
||||
#UCF file
|
||||
import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/b205_clk_gen_exdes.ucf
|
||||
|
||||
set_property top $topName [get_property srcset [current_run]]
|
||||
|
||||
launch_runs -runs synth_1
|
||||
wait_on_run synth_1
|
||||
|
||||
set_property add_step Bitgen [get_runs impl_1]
|
||||
launch_runs -runs impl_1
|
||||
wait_on_run impl_1
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,58 @@
|
||||
REM file: planAhead_rdn.sh
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM-----------------------------------------------------------------------------
|
||||
REM Script to synthesize and implement the RTL provided for the XADC wizard
|
||||
REM-----------------------------------------------------------------------------
|
||||
|
||||
del \f results
|
||||
mkdir results
|
||||
cd results
|
||||
|
||||
planAhead -mode batch -source ..\planAhead_rdn.tcl
|
||||
@@ -0,0 +1,57 @@
|
||||
#!/bin/sh
|
||||
# file: planAhead_rdn.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the RTL provided for the XADC wizard
|
||||
#-----------------------------------------------------------------------------
|
||||
rm -rf results
|
||||
mkdir results
|
||||
cd results
|
||||
planAhead -mode batch -source ../planAhead_rdn.tcl
|
||||
@@ -0,0 +1,69 @@
|
||||
# file : planAhead_rdn.tcl
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
set device xc6slx75csg484-3
|
||||
set projName b205_clk_gen
|
||||
set design b205_clk_gen
|
||||
set projDir [file dirname [info script]]
|
||||
create_project $projName $projDir/results/$projName -part $device -force
|
||||
set_property design_mode RTL [current_fileset -srcset]
|
||||
set top_module b205_clk_gen_exdes
|
||||
set_property top b205_clk_gen_exdes [get_property srcset [current_run]]
|
||||
add_files -norecurse {../../../b205_clk_gen.v}
|
||||
add_files -norecurse {../../example_design/b205_clk_gen_exdes.v}
|
||||
import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/b205_clk_gen_exdes.xdc}
|
||||
synth_design
|
||||
opt_design
|
||||
place_design
|
||||
route_design
|
||||
write_sdf -rename_top_module b205_clk_gen_exdes -file routed.sdf
|
||||
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module b205_clk_gen_exdes -file routed.v
|
||||
report_timing -nworst 30 -path_type full -file routed.twr
|
||||
report_drc -file report.drc
|
||||
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
verilog work ../../b205_clk_gen.v
|
||||
verilog work ../example_design/b205_clk_gen_exdes.v
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
run
|
||||
-ifmt MIXED
|
||||
-top b205_clk_gen_exdes
|
||||
-p xc6slx75-csg484-3
|
||||
-ifn xst.prj
|
||||
-ofn b205_clk_gen_exdes
|
||||
-keep_hierarchy soft
|
||||
-equivalent_register_removal no
|
||||
-max_fanout 65535
|
||||
@@ -0,0 +1,143 @@
|
||||
// file: b205_clk_gen_tb.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Clocking wizard demonstration testbench
|
||||
//----------------------------------------------------------------------------
|
||||
// This demonstration testbench instantiates the example design for the
|
||||
// clocking wizard. Input clocks are toggled, which cause the clocking
|
||||
// network to lock and the counters to increment.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`define wait_lock @(posedge LOCKED)
|
||||
|
||||
module b205_clk_gen_tb ();
|
||||
|
||||
// Clock to Q delay of 100ps
|
||||
localparam TCQ = 100;
|
||||
|
||||
|
||||
// timescale is 1ps/1ps
|
||||
localparam ONE_NS = 1000;
|
||||
localparam PHASE_ERR_MARGIN = 100; // 100ps
|
||||
// how many cycles to run
|
||||
localparam COUNT_PHASE = 1024;
|
||||
// we'll be using the period in many locations
|
||||
localparam time PER1 = 25.0*ONE_NS;
|
||||
localparam time PER1_1 = PER1/2;
|
||||
localparam time PER1_2 = PER1 - PER1/2;
|
||||
|
||||
// Declare the input clock signals
|
||||
reg CLK_IN1 = 1;
|
||||
|
||||
// The high bits of the sampling counters
|
||||
wire [3:1] COUNT;
|
||||
// Status and control signals
|
||||
reg RESET = 0;
|
||||
wire LOCKED;
|
||||
reg COUNTER_RESET = 0;
|
||||
wire [3:1] CLK_OUT;
|
||||
//Freq Check using the M & D values setting and actual Frequency generated
|
||||
|
||||
|
||||
// Input clock generation
|
||||
//------------------------------------
|
||||
always begin
|
||||
CLK_IN1 = #PER1_1 ~CLK_IN1;
|
||||
CLK_IN1 = #PER1_2 ~CLK_IN1;
|
||||
end
|
||||
|
||||
// Test sequence
|
||||
reg [15*8-1:0] test_phase = "";
|
||||
initial begin
|
||||
// Set up any display statements using time to be readable
|
||||
$timeformat(-12, 2, "ps", 10);
|
||||
COUNTER_RESET = 0;
|
||||
test_phase = "reset";
|
||||
RESET = 1;
|
||||
#(PER1*6);
|
||||
RESET = 0;
|
||||
test_phase = "wait lock";
|
||||
`wait_lock;
|
||||
#(PER1*6);
|
||||
COUNTER_RESET = 1;
|
||||
#(PER1*20)
|
||||
COUNTER_RESET = 0;
|
||||
|
||||
test_phase = "counting";
|
||||
#(PER1*COUNT_PHASE);
|
||||
|
||||
$display("SIMULATION PASSED");
|
||||
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Instantiation of the example design containing the clock
|
||||
// network and sampling counters
|
||||
//---------------------------------------------------------
|
||||
b205_clk_gen_exdes
|
||||
#(
|
||||
.TCQ (TCQ)
|
||||
) dut
|
||||
(// Clock in ports
|
||||
.CLK_IN1 (CLK_IN1),
|
||||
// Reset for logic in example design
|
||||
.COUNTER_RESET (COUNTER_RESET),
|
||||
.CLK_OUT (CLK_OUT),
|
||||
// High bits of the counters
|
||||
.COUNT (COUNT),
|
||||
// Status and control signals
|
||||
.RESET (RESET),
|
||||
.LOCKED (LOCKED));
|
||||
|
||||
// Freq Check
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,8 @@
|
||||
# file: simcmds.tcl
|
||||
|
||||
# create the simulation script
|
||||
vcd dumpfile isim.vcd
|
||||
vcd dumpvars -m /b205_clk_gen_tb -l 0
|
||||
wave add /
|
||||
run 50000ns
|
||||
quit
|
||||
@@ -0,0 +1,59 @@
|
||||
REM file: simulate_isim.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
vlogcomp -work work %XILINX%\verilog\src\glbl.v
|
||||
vlogcomp -work work ..\..\..\b205_clk_gen.v
|
||||
vlogcomp -work work ..\..\example_design\b205_clk_gen_exdes.v
|
||||
vlogcomp -work work ..\b205_clk_gen_tb.v
|
||||
|
||||
REM compile the project
|
||||
fuse work.b205_clk_gen_tb work.glbl -L unisims_ver -o b205_clk_gen_isim.exe
|
||||
|
||||
REM run the simulation script
|
||||
.\b205_clk_gen_isim.exe -gui -tclbatch simcmds.tcl
|
||||
@@ -0,0 +1,61 @@
|
||||
# file: simulate_isim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# lin64
|
||||
# create the project
|
||||
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
|
||||
vlogcomp -work work ../../../b205_clk_gen.v
|
||||
vlogcomp -work work ../../example_design/b205_clk_gen_exdes.v
|
||||
vlogcomp -work work ../b205_clk_gen_tb.v
|
||||
|
||||
# compile the project
|
||||
fuse work.b205_clk_gen_tb work.glbl -L unisims_ver -o b205_clk_gen_isim.exe
|
||||
|
||||
# run the simulation script
|
||||
./b205_clk_gen_isim.exe -gui -tclbatch simcmds.tcl
|
||||
@@ -0,0 +1,61 @@
|
||||
REM file: simulate_mti.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM set up the working directory
|
||||
vlib work
|
||||
|
||||
REM compile all of the files
|
||||
vlog -work work %XILINX%\verilog\src\glbl.v
|
||||
vlog -work work ..\..\..\b205_clk_gen.v
|
||||
vlog -work work ..\..\example_design\b205_clk_gen_exdes.v
|
||||
vlog -work work ..\b205_clk_gen_tb.v
|
||||
|
||||
REM run the simulation
|
||||
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b205_clk_gen_tb work.glbl
|
||||
|
||||
@@ -0,0 +1,65 @@
|
||||
# file: simulate_mti.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $env(XILINX)/verilog/src/glbl.v
|
||||
vlog -work work ../../../b205_clk_gen.v
|
||||
vlog -work work ../../example_design/b205_clk_gen_exdes.v
|
||||
vlog -work work ../b205_clk_gen_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -t ps -voptargs="+acc" -L unisims_ver work.b205_clk_gen_tb work.glbl
|
||||
do wave.do
|
||||
log b205_clk_gen_tb/dut/counter
|
||||
log -r /*
|
||||
run 50000ns
|
||||
@@ -0,0 +1,61 @@
|
||||
#/bin/sh
|
||||
# file: simulate_mti.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $XILINX/verilog/src/glbl.v
|
||||
vlog -work work ../../../b205_clk_gen.v
|
||||
vlog -work work ../../example_design/b205_clk_gen_exdes.v
|
||||
vlog -work work ../b205_clk_gen_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b205_clk_gen_tb work.glbl
|
||||
@@ -0,0 +1,62 @@
|
||||
#/bin/sh
|
||||
# file: simulate_ncsim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
mkdir work
|
||||
|
||||
# compile all of the files
|
||||
ncvlog -work work ${XILINX}/verilog/src/glbl.v
|
||||
ncvlog -work work ../../../b205_clk_gen.v
|
||||
ncvlog -work work ../../example_design/b205_clk_gen_exdes.v
|
||||
ncvlog -work work ../b205_clk_gen_tb.v
|
||||
|
||||
# elaborate and run the simulation
|
||||
ncelab -work work -access +wc work.b205_clk_gen_tb work.glbl
|
||||
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.b205_clk_gen_tb
|
||||
@@ -0,0 +1,72 @@
|
||||
#!/bin/sh
|
||||
# file: simulate_vcs.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# remove old files
|
||||
rm -rf simv* csrc DVEfiles AN.DB
|
||||
|
||||
# compile all of the files
|
||||
# Note that -sverilog is not strictly required- You can
|
||||
# remove the -sverilog if you change the type of the
|
||||
# localparam for the periods in the testbench file to
|
||||
# [63:0] from time
|
||||
vlogan -sverilog \
|
||||
${XILINX}/verilog/src/glbl.v \
|
||||
../../../b205_clk_gen.v \
|
||||
../../example_design/b205_clk_gen_exdes.v \
|
||||
../b205_clk_gen_tb.v
|
||||
|
||||
# prepare the simulation
|
||||
vcs +vcs+lic+wait -debug b205_clk_gen_tb glbl
|
||||
|
||||
# run the simulation
|
||||
./simv -ucli -i ucli_commands.key
|
||||
|
||||
# launch the viewer
|
||||
dve -vpd vcdplus.vpd -session vcs_session.tcl
|
||||
@@ -0,0 +1,5 @@
|
||||
call {$vcdpluson}
|
||||
call {$vcdplusmemon(b205_clk_gen_tb.dut.counter)}
|
||||
run
|
||||
call {$vcdplusclose}
|
||||
quit
|
||||
@@ -0,0 +1,18 @@
|
||||
gui_open_window Wave
|
||||
gui_sg_create b205_clk_gen_group
|
||||
gui_list_add_group -id Wave.1 {b205_clk_gen_group}
|
||||
gui_sg_addsignal -group b205_clk_gen_group {b205_clk_gen_tb.test_phase}
|
||||
gui_set_radix -radix {ascii} -signals {b205_clk_gen_tb.test_phase}
|
||||
gui_sg_addsignal -group b205_clk_gen_group {{Input_clocks}} -divider
|
||||
gui_sg_addsignal -group b205_clk_gen_group {b205_clk_gen_tb.CLK_IN1}
|
||||
gui_sg_addsignal -group b205_clk_gen_group {{Output_clocks}} -divider
|
||||
gui_sg_addsignal -group b205_clk_gen_group {b205_clk_gen_tb.dut.clk}
|
||||
gui_list_expand -id Wave.1 b205_clk_gen_tb.dut.clk
|
||||
gui_sg_addsignal -group b205_clk_gen_group {{Status_control}} -divider
|
||||
gui_sg_addsignal -group b205_clk_gen_group {b205_clk_gen_tb.RESET}
|
||||
gui_sg_addsignal -group b205_clk_gen_group {b205_clk_gen_tb.LOCKED}
|
||||
gui_sg_addsignal -group b205_clk_gen_group {{Counters}} -divider
|
||||
gui_sg_addsignal -group b205_clk_gen_group {b205_clk_gen_tb.COUNT}
|
||||
gui_sg_addsignal -group b205_clk_gen_group {b205_clk_gen_tb.dut.counter}
|
||||
gui_list_expand -id Wave.1 b205_clk_gen_tb.dut.counter
|
||||
gui_zoom -window Wave.1 -full
|
||||
@@ -0,0 +1,60 @@
|
||||
# file: wave.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
add wave -noupdate -format Literal -radix ascii /b205_clk_gen_tb/test_phase
|
||||
add wave -noupdate -divider {Input clocks}
|
||||
add wave -noupdate -format Logic /b205_clk_gen_tb/CLK_IN1
|
||||
add wave -noupdate -divider {Output clocks}
|
||||
add wave -noupdate -format Literal -expand /b205_clk_gen_tb/dut/clk
|
||||
add wave -noupdate -divider Status/control
|
||||
add wave -noupdate -format Logic /b205_clk_gen_tb/RESET
|
||||
add wave -noupdate -format Logic /b205_clk_gen_tb/LOCKED
|
||||
add wave -noupdate -divider Counters
|
||||
add wave -noupdate -format Literal -radix hexadecimal /b205_clk_gen_tb/COUNT
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /b205_clk_gen_tb/dut/counter
|
||||
@@ -0,0 +1,119 @@
|
||||
# file: wave.sv
|
||||
#
|
||||
# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# Get the windows set up
|
||||
#
|
||||
if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {
|
||||
window geometry "Design Browser 1" 1054x819+536+322
|
||||
}
|
||||
window target "Design Browser 1" on
|
||||
browser using {Design Browser 1}
|
||||
browser set \
|
||||
-scope nc::b205_clk_gen_tb
|
||||
browser yview see nc::b205_clk_gen_tb
|
||||
browser timecontrol set -lock 0
|
||||
|
||||
if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
|
||||
window geometry "Waveform 1" 1010x600+0+541
|
||||
}
|
||||
window target "Waveform 1" on
|
||||
waveform using {Waveform 1}
|
||||
waveform sidebar visibility partial
|
||||
waveform set \
|
||||
-primarycursor TimeA \
|
||||
-signalnames name \
|
||||
-signalwidth 175 \
|
||||
-units ns \
|
||||
-valuewidth 75
|
||||
cursor set -using TimeA -time 0
|
||||
waveform baseline set -time 0
|
||||
waveform xview limits 0 20000n
|
||||
|
||||
#
|
||||
# Define signal groups
|
||||
#
|
||||
catch {group new -name {Output clocks} -overlay 0}
|
||||
catch {group new -name {Status/control} -overlay 0}
|
||||
catch {group new -name {Counters} -overlay 0}
|
||||
|
||||
set id [waveform add -signals [list {nc::b205_clk_gen_tb.CLK_IN1}]]
|
||||
|
||||
group using {Output clocks}
|
||||
group set -overlay 0
|
||||
group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{b205_clk_gen_tb.dut.clk[1]} \
|
||||
{b205_clk_gen_tb.dut.clk[2]} \ {b205_clk_gen_tb.dut.clk[3]}
|
||||
group using {Counters}
|
||||
group set -overlay 0
|
||||
group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{b205_clk_gen_tb.dut.counter[1]} \
|
||||
{b205_clk_gen_tb.dut.counter[2]} \ {b205_clk_gen_tb.dut.counter[3]}
|
||||
group using {Status/control}
|
||||
group set -overlay 0
|
||||
group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{nc::b205_clk_gen_tb.RESET} {nc::b205_clk_gen_tb.LOCKED}
|
||||
|
||||
|
||||
set id [waveform add -signals [list {nc::b205_clk_gen_tb.COUNT} ]]
|
||||
|
||||
set id [waveform add -signals [list {nc::b205_clk_gen_tb.test_phase} ]]
|
||||
waveform format $id -radix %a
|
||||
|
||||
set groupId [waveform add -groups {{Input clocks}}]
|
||||
set groupId [waveform add -groups {{Output clocks}}]
|
||||
set groupId [waveform add -groups {{Status/control}}]
|
||||
set groupId [waveform add -groups {{Counters}}]
|
||||
@@ -0,0 +1,157 @@
|
||||
// file: b205_clk_gen_tb.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Clocking wizard demonstration testbench
|
||||
//----------------------------------------------------------------------------
|
||||
// This demonstration testbench instantiates the example design for the
|
||||
// clocking wizard. Input clocks are toggled, which cause the clocking
|
||||
// network to lock and the counters to increment.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`define wait_lock @(posedge LOCKED)
|
||||
|
||||
module b205_clk_gen_tb ();
|
||||
|
||||
// Clock to Q delay of 100ps
|
||||
localparam TCQ = 100;
|
||||
|
||||
|
||||
// timescale is 1ps/1ps
|
||||
localparam ONE_NS = 1000;
|
||||
localparam PHASE_ERR_MARGIN = 100; // 100ps
|
||||
// how many cycles to run
|
||||
localparam COUNT_PHASE = 1024;
|
||||
// we'll be using the period in many locations
|
||||
localparam time PER1 = 25.0*ONE_NS;
|
||||
localparam time PER1_1 = PER1/2;
|
||||
localparam time PER1_2 = PER1 - PER1/2;
|
||||
|
||||
// Declare the input clock signals
|
||||
reg CLK_IN1 = 1;
|
||||
|
||||
// The high bits of the sampling counters
|
||||
wire [3:1] COUNT;
|
||||
// Status and control signals
|
||||
reg RESET = 0;
|
||||
wire LOCKED;
|
||||
reg COUNTER_RESET = 0;
|
||||
wire [3:1] CLK_OUT;
|
||||
//Freq Check using the M & D values setting and actual Frequency generated
|
||||
|
||||
reg [13:0] timeout_counter = 14'b00000000000000;
|
||||
|
||||
// Input clock generation
|
||||
//------------------------------------
|
||||
always begin
|
||||
CLK_IN1 = #PER1_1 ~CLK_IN1;
|
||||
CLK_IN1 = #PER1_2 ~CLK_IN1;
|
||||
end
|
||||
|
||||
// Test sequence
|
||||
reg [15*8-1:0] test_phase = "";
|
||||
initial begin
|
||||
// Set up any display statements using time to be readable
|
||||
$timeformat(-12, 2, "ps", 10);
|
||||
$display ("Timing checks are not valid");
|
||||
COUNTER_RESET = 0;
|
||||
test_phase = "reset";
|
||||
RESET = 1;
|
||||
#(PER1*6);
|
||||
RESET = 0;
|
||||
test_phase = "wait lock";
|
||||
`wait_lock;
|
||||
#(PER1*6);
|
||||
COUNTER_RESET = 1;
|
||||
#(PER1*19.5)
|
||||
COUNTER_RESET = 0;
|
||||
#(PER1*1)
|
||||
$display ("Timing checks are valid");
|
||||
test_phase = "counting";
|
||||
#(PER1*COUNT_PHASE);
|
||||
|
||||
$display("SIMULATION PASSED");
|
||||
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge CLK_IN1) begin
|
||||
timeout_counter <= timeout_counter + 1'b1;
|
||||
if (timeout_counter == 14'b10000000000000) begin
|
||||
if (LOCKED != 1'b1) begin
|
||||
$display("ERROR : NO LOCK signal");
|
||||
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Instantiation of the example design containing the clock
|
||||
// network and sampling counters
|
||||
//---------------------------------------------------------
|
||||
b205_clk_gen_exdes
|
||||
dut
|
||||
(// Clock in ports
|
||||
.CLK_IN1 (CLK_IN1),
|
||||
// Reset for logic in example design
|
||||
.COUNTER_RESET (COUNTER_RESET),
|
||||
.CLK_OUT (CLK_OUT),
|
||||
// High bits of the counters
|
||||
.COUNT (COUNT),
|
||||
// Status and control signals
|
||||
.RESET (RESET),
|
||||
.LOCKED (LOCKED));
|
||||
|
||||
|
||||
// Freq Check
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,2 @@
|
||||
COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
|
||||
SCOPE = b205_clk_gen_tb.dut;
|
||||
@@ -0,0 +1,9 @@
|
||||
# file: simcmds.tcl
|
||||
|
||||
# create the simulation script
|
||||
vcd dumpfile isim.vcd
|
||||
vcd dumpvars -m /b205_clk_gen_tb -l 0
|
||||
wave add /
|
||||
run 50000ns
|
||||
quit
|
||||
|
||||
@@ -0,0 +1,62 @@
|
||||
# file: simulate_isim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# create the project
|
||||
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
|
||||
vlogcomp -work work ../../implement/results/routed.v
|
||||
vlogcomp -work work b205_clk_gen_tb.v
|
||||
|
||||
# compile the project
|
||||
fuse work.b205_clk_gen_tb work.glbl -L secureip -L simprims_ver -o b205_clk_gen_isim.exe
|
||||
|
||||
# run the simulation script
|
||||
./b205_clk_gen_isim.exe -tclbatch simcmds.tcl -sdfmax /b205_clk_gen_tb/dut=../../implement/results/routed.sdf
|
||||
|
||||
# run the simulation script
|
||||
#./b205_clk_gen_isim.exe -gui -tclbatch simcmds.tcl
|
||||
@@ -0,0 +1,59 @@
|
||||
REM file: simulate_mti.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
REM compile all of the files
|
||||
vlog -work work %XILINX%\verilog\src\glbl.v
|
||||
vlog -work work ..\..\implement\results\routed.v
|
||||
vlog -work work b205_clk_gen_tb.v
|
||||
|
||||
REM run the simulation
|
||||
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b205_clk_gen_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.b205_clk_gen_tb work.glbl
|
||||
@@ -0,0 +1,65 @@
|
||||
# file: simulate_mti.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $env(XILINX)/verilog/src/glbl.v
|
||||
vlog -work work ../../implement/results/routed.v
|
||||
vlog -work work b205_clk_gen_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b205_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b205_clk_gen_tb work.glbl
|
||||
#do wave.do
|
||||
#log -r /*
|
||||
run 50000ns
|
||||
|
||||
|
||||
@@ -0,0 +1,61 @@
|
||||
#/bin/sh
|
||||
# file: simulate_mti.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $XILINX/verilog/src/glbl.v
|
||||
vlog -work work ../../implement/results/routed.v
|
||||
vlog -work work b205_clk_gen_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b205_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b205_clk_gen_tb work.glbl
|
||||
@@ -0,0 +1,64 @@
|
||||
#!/bin/sh
|
||||
# file: simulate_ncsim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
mkdir work
|
||||
|
||||
# compile all of the files
|
||||
ncvlog -work work ${XILINX}/verilog/src/glbl.v
|
||||
ncvlog -work work ../../implement/results/routed.v
|
||||
ncvlog -work work b205_clk_gen_tb.v
|
||||
|
||||
# elaborate and run the simulation
|
||||
ncsdfc ../../implement/results/routed.sdf
|
||||
|
||||
ncelab -work work -access +wc -pulse_r 10 -nonotifier work.b205_clk_gen_tb work.glbl -sdf_cmd_file sdf_cmd_file
|
||||
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.b205_clk_gen_tb
|
||||
|
||||
@@ -0,0 +1,72 @@
|
||||
#!/bin/sh
|
||||
# file: simulate_vcs.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# remove old files
|
||||
rm -rf simv* csrc DVEfiles AN.DB
|
||||
|
||||
# compile all of the files
|
||||
# Note that -sverilog is not strictly required- You can
|
||||
# remove the -sverilog if you change the type of the
|
||||
# localparam for the periods in the testbench file to
|
||||
# [63:0] from time
|
||||
vlogan -sverilog \
|
||||
b205_clk_gen_tb.v \
|
||||
../../implement/results/routed.v
|
||||
|
||||
|
||||
# prepare the simulation
|
||||
vcs -sdf max:b205_clk_gen_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
|
||||
+libext+.v -debug b205_clk_gen_tb.v ../../implement/results/routed.v
|
||||
|
||||
# run the simulation
|
||||
./simv -ucli -i ucli_commands.key
|
||||
|
||||
# launch the viewer
|
||||
#dve -vpd vcdplus.vpd -session vcs_session.tcl
|
||||
@@ -0,0 +1,5 @@
|
||||
|
||||
call {$vcdpluson}
|
||||
run 50000ns
|
||||
call {$vcdplusclose}
|
||||
quit
|
||||
@@ -0,0 +1 @@
|
||||
gui_open_window Wave
|
||||
@@ -0,0 +1,72 @@
|
||||
# file: wave.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /b205_clk_gen_tb/CLK_IN1
|
||||
add wave -noupdate /b205_clk_gen_tb/COUNT
|
||||
add wave -noupdate /b205_clk_gen_tb/LOCKED
|
||||
add wave -noupdate /b205_clk_gen_tb/RESET
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
|
||||
configure wave -namecolwidth 238
|
||||
configure wave -valuecolwidth 107
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ps
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {74848022 ps}
|
||||
@@ -0,0 +1,54 @@
|
||||
# Output products list for <b205_clk_gen>
|
||||
_xmsgs/pn_parser.xmsgs
|
||||
b205_clk_gen/clk_wiz_v3_6_readme.txt
|
||||
b205_clk_gen/doc/clk_wiz_v3_6_readme.txt
|
||||
b205_clk_gen/doc/clk_wiz_v3_6_vinfo.html
|
||||
b205_clk_gen/doc/pg065_clk_wiz.pdf
|
||||
b205_clk_gen/example_design/b205_clk_gen_exdes.ucf
|
||||
b205_clk_gen/example_design/b205_clk_gen_exdes.v
|
||||
b205_clk_gen/example_design/b205_clk_gen_exdes.xdc
|
||||
b205_clk_gen/implement/implement.bat
|
||||
b205_clk_gen/implement/implement.sh
|
||||
b205_clk_gen/implement/planAhead_ise.bat
|
||||
b205_clk_gen/implement/planAhead_ise.sh
|
||||
b205_clk_gen/implement/planAhead_ise.tcl
|
||||
b205_clk_gen/implement/planAhead_rdn.bat
|
||||
b205_clk_gen/implement/planAhead_rdn.sh
|
||||
b205_clk_gen/implement/planAhead_rdn.tcl
|
||||
b205_clk_gen/implement/xst.prj
|
||||
b205_clk_gen/implement/xst.scr
|
||||
b205_clk_gen/simulation/b205_clk_gen_tb.v
|
||||
b205_clk_gen/simulation/functional/simcmds.tcl
|
||||
b205_clk_gen/simulation/functional/simulate_isim.bat
|
||||
b205_clk_gen/simulation/functional/simulate_isim.sh
|
||||
b205_clk_gen/simulation/functional/simulate_mti.bat
|
||||
b205_clk_gen/simulation/functional/simulate_mti.do
|
||||
b205_clk_gen/simulation/functional/simulate_mti.sh
|
||||
b205_clk_gen/simulation/functional/simulate_ncsim.sh
|
||||
b205_clk_gen/simulation/functional/simulate_vcs.sh
|
||||
b205_clk_gen/simulation/functional/ucli_commands.key
|
||||
b205_clk_gen/simulation/functional/vcs_session.tcl
|
||||
b205_clk_gen/simulation/functional/wave.do
|
||||
b205_clk_gen/simulation/functional/wave.sv
|
||||
b205_clk_gen/simulation/timing/b205_clk_gen_tb.v
|
||||
b205_clk_gen/simulation/timing/sdf_cmd_file
|
||||
b205_clk_gen/simulation/timing/simcmds.tcl
|
||||
b205_clk_gen/simulation/timing/simulate_isim.sh
|
||||
b205_clk_gen/simulation/timing/simulate_mti.bat
|
||||
b205_clk_gen/simulation/timing/simulate_mti.do
|
||||
b205_clk_gen/simulation/timing/simulate_mti.sh
|
||||
b205_clk_gen/simulation/timing/simulate_ncsim.sh
|
||||
b205_clk_gen/simulation/timing/simulate_vcs.sh
|
||||
b205_clk_gen/simulation/timing/ucli_commands.key
|
||||
b205_clk_gen/simulation/timing/vcs_session.tcl
|
||||
b205_clk_gen/simulation/timing/wave.do
|
||||
b205_clk_gen.asy
|
||||
b205_clk_gen.gise
|
||||
b205_clk_gen.ucf
|
||||
b205_clk_gen.v
|
||||
b205_clk_gen.veo
|
||||
b205_clk_gen.xco
|
||||
b205_clk_gen.xdc
|
||||
b205_clk_gen.xise
|
||||
b205_clk_gen_flist.txt
|
||||
b205_clk_gen_xmdf.tcl
|
||||
Executable
+140
@@ -0,0 +1,140 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide b205_clk_gen_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::b205_clk_gen_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::b205_clk_gen_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name b205_clk_gen
|
||||
}
|
||||
# ::b205_clk_gen_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::b205_clk_gen_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/clk_wiz_readme.txt
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/doc/clk_wiz_ds709.pdf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/doc/clk_wiz_gsg521.pdf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/implement/implement.bat
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/implement/implement.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/implement/xst.prj
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/implement/xst.scr
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/b205_clk_gen_tb.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/simcmds.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/simulate_isim.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/simulate_mti.do
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/simulate_ncsim.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/simulate_vcs.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/ucli_commands.key
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/vcs_session.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/wave.do
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/wave.sv
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen.ejp
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen.ucf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b205_clk_gen
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
@@ -0,0 +1,9 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 chipscope_icon
|
||||
RECTANGLE Normal 32 32 544 864
|
||||
LINE Wide 576 112 544 112
|
||||
PIN 576 112 RIGHT 36
|
||||
PINATTR PinName control0[35:0]
|
||||
PINATTR Polarity BOTH
|
||||
|
||||
@@ -0,0 +1,9 @@
|
||||
NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
|
||||
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
|
||||
#Update Constraints
|
||||
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
|
||||
NET "U0/iSHIFT_OUT" TIG ;
|
||||
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
|
||||
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
|
||||
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
|
||||
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
|
||||
@@ -0,0 +1,7 @@
|
||||
# icon XDC
|
||||
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
|
||||
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
|
||||
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
|
||||
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
|
||||
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,9 @@
|
||||
NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
|
||||
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
|
||||
#Update Constraints
|
||||
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
|
||||
NET "U0/iSHIFT_OUT" TIG ;
|
||||
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
|
||||
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
|
||||
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
|
||||
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
|
||||
@@ -0,0 +1,27 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2015 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 14.6
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : chipscope_icon.v
|
||||
// /___/ /\ Timestamp : Tue Apr 14 17:06:06 PDT 2015
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
// Design Name: Verilog Synthesis Wrapper
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// This wrapper is used to integrate with Project Navigator and PlanAhead
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module chipscope_icon(
|
||||
CONTROL0) /* synthesis syn_black_box syn_noprune=1 */;
|
||||
|
||||
|
||||
inout [35 : 0] CONTROL0;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,28 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2015 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 14.6
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : chipscope_icon.veo
|
||||
// /___/ /\ Timestamp : Tue Apr 14 17:06:06 PDT 2015
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
// Design Name: ISE Instantiation template
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
chipscope_icon YourInstanceName (
|
||||
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
@@ -0,0 +1,56 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.6
|
||||
# Date: Wed Apr 15 00:05:36 2015
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc6slx75
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -3
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET component_name=chipscope_icon
|
||||
CSET constraint_type=external
|
||||
CSET enable_jtag_bufg=true
|
||||
CSET example_design=false
|
||||
CSET number_control_ports=1
|
||||
CSET use_ext_bscan=false
|
||||
CSET use_softbscan=false
|
||||
CSET use_unused_bscan=false
|
||||
CSET user_scan_chain=USER1
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2013-06-08T17:28:33Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: b52cbe62
|
||||
@@ -0,0 +1,7 @@
|
||||
# icon XDC
|
||||
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
|
||||
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
|
||||
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
|
||||
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
|
||||
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
|
||||
@@ -0,0 +1,15 @@
|
||||
# Output products list for <chipscope_icon>
|
||||
chipscope_icon.asy
|
||||
chipscope_icon.constraints/chipscope_icon.ucf
|
||||
chipscope_icon.constraints/chipscope_icon.xdc
|
||||
chipscope_icon.gise
|
||||
chipscope_icon.ngc
|
||||
chipscope_icon.ucf
|
||||
chipscope_icon.v
|
||||
chipscope_icon.veo
|
||||
chipscope_icon.xco
|
||||
chipscope_icon.xdc
|
||||
chipscope_icon.xise
|
||||
chipscope_icon_flist.txt
|
||||
chipscope_icon_readme.txt
|
||||
chipscope_icon_xmdf.tcl
|
||||
@@ -0,0 +1,45 @@
|
||||
The following files were generated for 'chipscope_icon' in directory
|
||||
/home/mwest/git/fpgadev/usrp3/top/b205/coregen/
|
||||
|
||||
XCO file generator:
|
||||
Generate an XCO file for compatibility with legacy flows.
|
||||
|
||||
* chipscope_icon.xco
|
||||
|
||||
Creates an implementation netlist:
|
||||
Creates an implementation netlist for the IP.
|
||||
|
||||
* chipscope_icon.constraints/chipscope_icon.ucf
|
||||
* chipscope_icon.constraints/chipscope_icon.xdc
|
||||
* chipscope_icon.ngc
|
||||
* chipscope_icon.ucf
|
||||
* chipscope_icon.v
|
||||
* chipscope_icon.veo
|
||||
* chipscope_icon.xdc
|
||||
* chipscope_icon_xmdf.tcl
|
||||
|
||||
IP Symbol Generator:
|
||||
Generate an IP symbol based on the current project options'.
|
||||
|
||||
* chipscope_icon.asy
|
||||
|
||||
Generate ISE subproject:
|
||||
Create an ISE subproject for use when including this core in ISE designs
|
||||
|
||||
* chipscope_icon.gise
|
||||
* chipscope_icon.xise
|
||||
|
||||
Deliver Readme:
|
||||
Readme file for the IP.
|
||||
|
||||
* chipscope_icon_readme.txt
|
||||
|
||||
Generate FLIST file:
|
||||
Text file listing all of the output files produced when a customized core was
|
||||
generated in the CORE Generator.
|
||||
|
||||
* chipscope_icon_flist.txt
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
Executable
+88
@@ -0,0 +1,88 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide chipscope_icon_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::chipscope_icon_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::chipscope_icon_xmdf::xmdfInit { instance } {
|
||||
# Variable containing name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_icon
|
||||
}
|
||||
# ::chipscope_icon_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::chipscope_icon_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.ucf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ncf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.xdc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xcf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_icon
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
|
||||
|
||||
@@ -0,0 +1,17 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 chipscope_ila
|
||||
RECTANGLE Normal 32 32 288 704
|
||||
LINE Wide 0 80 32 80
|
||||
PIN 0 80 LEFT 36
|
||||
PINATTR PinName control[35:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 112 32 112
|
||||
PIN 0 112 LEFT 36
|
||||
PINATTR PinName clk
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 176 32 176
|
||||
PIN 0 176 LEFT 36
|
||||
PINATTR PinName trig0[127:0]
|
||||
PINATTR Polarity IN
|
||||
|
||||
@@ -0,0 +1,144 @@
|
||||
#ChipScope Core Generator Project File Version 3.0
|
||||
#Tue Jun 30 11:48:11 PDT 2015
|
||||
SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
|
||||
SignalExport.bus<0000>.name=TRIG0
|
||||
SignalExport.bus<0000>.offset=0.0
|
||||
SignalExport.bus<0000>.precision=0
|
||||
SignalExport.bus<0000>.radix=Bin
|
||||
SignalExport.bus<0000>.scaleFactor=1.0
|
||||
SignalExport.clockChannel=CLK
|
||||
SignalExport.dataEqualsTrigger=true
|
||||
SignalExport.triggerChannel<0000><0000>=TRIG0[0]
|
||||
SignalExport.triggerChannel<0000><0001>=TRIG0[1]
|
||||
SignalExport.triggerChannel<0000><0002>=TRIG0[2]
|
||||
SignalExport.triggerChannel<0000><0003>=TRIG0[3]
|
||||
SignalExport.triggerChannel<0000><0004>=TRIG0[4]
|
||||
SignalExport.triggerChannel<0000><0005>=TRIG0[5]
|
||||
SignalExport.triggerChannel<0000><0006>=TRIG0[6]
|
||||
SignalExport.triggerChannel<0000><0007>=TRIG0[7]
|
||||
SignalExport.triggerChannel<0000><0008>=TRIG0[8]
|
||||
SignalExport.triggerChannel<0000><0009>=TRIG0[9]
|
||||
SignalExport.triggerChannel<0000><0010>=TRIG0[10]
|
||||
SignalExport.triggerChannel<0000><0011>=TRIG0[11]
|
||||
SignalExport.triggerChannel<0000><0012>=TRIG0[12]
|
||||
SignalExport.triggerChannel<0000><0013>=TRIG0[13]
|
||||
SignalExport.triggerChannel<0000><0014>=TRIG0[14]
|
||||
SignalExport.triggerChannel<0000><0015>=TRIG0[15]
|
||||
SignalExport.triggerChannel<0000><0016>=TRIG0[16]
|
||||
SignalExport.triggerChannel<0000><0017>=TRIG0[17]
|
||||
SignalExport.triggerChannel<0000><0018>=TRIG0[18]
|
||||
SignalExport.triggerChannel<0000><0019>=TRIG0[19]
|
||||
SignalExport.triggerChannel<0000><0020>=TRIG0[20]
|
||||
SignalExport.triggerChannel<0000><0021>=TRIG0[21]
|
||||
SignalExport.triggerChannel<0000><0022>=TRIG0[22]
|
||||
SignalExport.triggerChannel<0000><0023>=TRIG0[23]
|
||||
SignalExport.triggerChannel<0000><0024>=TRIG0[24]
|
||||
SignalExport.triggerChannel<0000><0025>=TRIG0[25]
|
||||
SignalExport.triggerChannel<0000><0026>=TRIG0[26]
|
||||
SignalExport.triggerChannel<0000><0027>=TRIG0[27]
|
||||
SignalExport.triggerChannel<0000><0028>=TRIG0[28]
|
||||
SignalExport.triggerChannel<0000><0029>=TRIG0[29]
|
||||
SignalExport.triggerChannel<0000><0030>=TRIG0[30]
|
||||
SignalExport.triggerChannel<0000><0031>=TRIG0[31]
|
||||
SignalExport.triggerChannel<0000><0032>=TRIG0[32]
|
||||
SignalExport.triggerChannel<0000><0033>=TRIG0[33]
|
||||
SignalExport.triggerChannel<0000><0034>=TRIG0[34]
|
||||
SignalExport.triggerChannel<0000><0035>=TRIG0[35]
|
||||
SignalExport.triggerChannel<0000><0036>=TRIG0[36]
|
||||
SignalExport.triggerChannel<0000><0037>=TRIG0[37]
|
||||
SignalExport.triggerChannel<0000><0038>=TRIG0[38]
|
||||
SignalExport.triggerChannel<0000><0039>=TRIG0[39]
|
||||
SignalExport.triggerChannel<0000><0040>=TRIG0[40]
|
||||
SignalExport.triggerChannel<0000><0041>=TRIG0[41]
|
||||
SignalExport.triggerChannel<0000><0042>=TRIG0[42]
|
||||
SignalExport.triggerChannel<0000><0043>=TRIG0[43]
|
||||
SignalExport.triggerChannel<0000><0044>=TRIG0[44]
|
||||
SignalExport.triggerChannel<0000><0045>=TRIG0[45]
|
||||
SignalExport.triggerChannel<0000><0046>=TRIG0[46]
|
||||
SignalExport.triggerChannel<0000><0047>=TRIG0[47]
|
||||
SignalExport.triggerChannel<0000><0048>=TRIG0[48]
|
||||
SignalExport.triggerChannel<0000><0049>=TRIG0[49]
|
||||
SignalExport.triggerChannel<0000><0050>=TRIG0[50]
|
||||
SignalExport.triggerChannel<0000><0051>=TRIG0[51]
|
||||
SignalExport.triggerChannel<0000><0052>=TRIG0[52]
|
||||
SignalExport.triggerChannel<0000><0053>=TRIG0[53]
|
||||
SignalExport.triggerChannel<0000><0054>=TRIG0[54]
|
||||
SignalExport.triggerChannel<0000><0055>=TRIG0[55]
|
||||
SignalExport.triggerChannel<0000><0056>=TRIG0[56]
|
||||
SignalExport.triggerChannel<0000><0057>=TRIG0[57]
|
||||
SignalExport.triggerChannel<0000><0058>=TRIG0[58]
|
||||
SignalExport.triggerChannel<0000><0059>=TRIG0[59]
|
||||
SignalExport.triggerChannel<0000><0060>=TRIG0[60]
|
||||
SignalExport.triggerChannel<0000><0061>=TRIG0[61]
|
||||
SignalExport.triggerChannel<0000><0062>=TRIG0[62]
|
||||
SignalExport.triggerChannel<0000><0063>=TRIG0[63]
|
||||
SignalExport.triggerChannel<0000><0064>=TRIG0[64]
|
||||
SignalExport.triggerChannel<0000><0065>=TRIG0[65]
|
||||
SignalExport.triggerChannel<0000><0066>=TRIG0[66]
|
||||
SignalExport.triggerChannel<0000><0067>=TRIG0[67]
|
||||
SignalExport.triggerChannel<0000><0068>=TRIG0[68]
|
||||
SignalExport.triggerChannel<0000><0069>=TRIG0[69]
|
||||
SignalExport.triggerChannel<0000><0070>=TRIG0[70]
|
||||
SignalExport.triggerChannel<0000><0071>=TRIG0[71]
|
||||
SignalExport.triggerChannel<0000><0072>=TRIG0[72]
|
||||
SignalExport.triggerChannel<0000><0073>=TRIG0[73]
|
||||
SignalExport.triggerChannel<0000><0074>=TRIG0[74]
|
||||
SignalExport.triggerChannel<0000><0075>=TRIG0[75]
|
||||
SignalExport.triggerChannel<0000><0076>=TRIG0[76]
|
||||
SignalExport.triggerChannel<0000><0077>=TRIG0[77]
|
||||
SignalExport.triggerChannel<0000><0078>=TRIG0[78]
|
||||
SignalExport.triggerChannel<0000><0079>=TRIG0[79]
|
||||
SignalExport.triggerChannel<0000><0080>=TRIG0[80]
|
||||
SignalExport.triggerChannel<0000><0081>=TRIG0[81]
|
||||
SignalExport.triggerChannel<0000><0082>=TRIG0[82]
|
||||
SignalExport.triggerChannel<0000><0083>=TRIG0[83]
|
||||
SignalExport.triggerChannel<0000><0084>=TRIG0[84]
|
||||
SignalExport.triggerChannel<0000><0085>=TRIG0[85]
|
||||
SignalExport.triggerChannel<0000><0086>=TRIG0[86]
|
||||
SignalExport.triggerChannel<0000><0087>=TRIG0[87]
|
||||
SignalExport.triggerChannel<0000><0088>=TRIG0[88]
|
||||
SignalExport.triggerChannel<0000><0089>=TRIG0[89]
|
||||
SignalExport.triggerChannel<0000><0090>=TRIG0[90]
|
||||
SignalExport.triggerChannel<0000><0091>=TRIG0[91]
|
||||
SignalExport.triggerChannel<0000><0092>=TRIG0[92]
|
||||
SignalExport.triggerChannel<0000><0093>=TRIG0[93]
|
||||
SignalExport.triggerChannel<0000><0094>=TRIG0[94]
|
||||
SignalExport.triggerChannel<0000><0095>=TRIG0[95]
|
||||
SignalExport.triggerChannel<0000><0096>=TRIG0[96]
|
||||
SignalExport.triggerChannel<0000><0097>=TRIG0[97]
|
||||
SignalExport.triggerChannel<0000><0098>=TRIG0[98]
|
||||
SignalExport.triggerChannel<0000><0099>=TRIG0[99]
|
||||
SignalExport.triggerChannel<0000><0100>=TRIG0[100]
|
||||
SignalExport.triggerChannel<0000><0101>=TRIG0[101]
|
||||
SignalExport.triggerChannel<0000><0102>=TRIG0[102]
|
||||
SignalExport.triggerChannel<0000><0103>=TRIG0[103]
|
||||
SignalExport.triggerChannel<0000><0104>=TRIG0[104]
|
||||
SignalExport.triggerChannel<0000><0105>=TRIG0[105]
|
||||
SignalExport.triggerChannel<0000><0106>=TRIG0[106]
|
||||
SignalExport.triggerChannel<0000><0107>=TRIG0[107]
|
||||
SignalExport.triggerChannel<0000><0108>=TRIG0[108]
|
||||
SignalExport.triggerChannel<0000><0109>=TRIG0[109]
|
||||
SignalExport.triggerChannel<0000><0110>=TRIG0[110]
|
||||
SignalExport.triggerChannel<0000><0111>=TRIG0[111]
|
||||
SignalExport.triggerChannel<0000><0112>=TRIG0[112]
|
||||
SignalExport.triggerChannel<0000><0113>=TRIG0[113]
|
||||
SignalExport.triggerChannel<0000><0114>=TRIG0[114]
|
||||
SignalExport.triggerChannel<0000><0115>=TRIG0[115]
|
||||
SignalExport.triggerChannel<0000><0116>=TRIG0[116]
|
||||
SignalExport.triggerChannel<0000><0117>=TRIG0[117]
|
||||
SignalExport.triggerChannel<0000><0118>=TRIG0[118]
|
||||
SignalExport.triggerChannel<0000><0119>=TRIG0[119]
|
||||
SignalExport.triggerChannel<0000><0120>=TRIG0[120]
|
||||
SignalExport.triggerChannel<0000><0121>=TRIG0[121]
|
||||
SignalExport.triggerChannel<0000><0122>=TRIG0[122]
|
||||
SignalExport.triggerChannel<0000><0123>=TRIG0[123]
|
||||
SignalExport.triggerChannel<0000><0124>=TRIG0[124]
|
||||
SignalExport.triggerChannel<0000><0125>=TRIG0[125]
|
||||
SignalExport.triggerChannel<0000><0126>=TRIG0[126]
|
||||
SignalExport.triggerChannel<0000><0127>=TRIG0[127]
|
||||
SignalExport.triggerPort<0000>.name=TRIG0
|
||||
SignalExport.triggerPortCount=1
|
||||
SignalExport.triggerPortIsData<0000>=true
|
||||
SignalExport.triggerPortWidth<0000>=128
|
||||
SignalExport.type=ila
|
||||
|
||||
@@ -0,0 +1,15 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
NET "CLK" TNM_NET = D_CLK ;
|
||||
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
|
||||
TIMESPEC TS_D2_TO_T2_chipscope_ila = FROM D2_CLK TO "FFS" TIG;
|
||||
TIMESPEC TS_J2_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J3_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J4_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
|
||||
#
|
||||
# Input keep/save net constraints
|
||||
#
|
||||
NET "TRIG0<*" S;
|
||||
NET "TRIG0<*" KEEP;
|
||||
@@ -0,0 +1,6 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
|
||||
set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
|
||||
set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
|
||||
@@ -0,0 +1,15 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
NET "CLK" TNM_NET = D_CLK ;
|
||||
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
|
||||
TIMESPEC TS_D2_TO_T2 = FROM D2_CLK TO "FFS" TIG;
|
||||
TIMESPEC TS_J2_TO_D2 = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J3_TO_D2 = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J4_TO_D2 = FROM "FFS" TO D2_CLK TIG;
|
||||
|
||||
#
|
||||
# Input keep/save net constraints
|
||||
#
|
||||
NET "TRIG0<*" S;
|
||||
NET "TRIG0<*" KEEP;
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,15 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
NET "CLK" TNM_NET = D_CLK ;
|
||||
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
|
||||
TIMESPEC TS_D2_TO_T2_chipscope_ila = FROM D2_CLK TO "FFS" TIG;
|
||||
TIMESPEC TS_J2_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J3_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J4_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
|
||||
#
|
||||
# Input keep/save net constraints
|
||||
#
|
||||
NET "TRIG0<*" S;
|
||||
NET "TRIG0<*" KEEP;
|
||||
@@ -0,0 +1,31 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2015 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 14.7
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : chipscope_ila.v
|
||||
// /___/ /\ Timestamp : Tue Jun 30 11:48:11 PDT 2015
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
// Design Name: Verilog Synthesis Wrapper
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// This wrapper is used to integrate with Project Navigator and PlanAhead
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module chipscope_ila(
|
||||
CONTROL,
|
||||
CLK,
|
||||
TRIG0) /* synthesis syn_black_box syn_noprune=1 */;
|
||||
|
||||
|
||||
inout [35 : 0] CONTROL;
|
||||
input CLK;
|
||||
input [127 : 0] TRIG0;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,30 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2015 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 14.7
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : chipscope_ila.veo
|
||||
// /___/ /\ Timestamp : Tue Jun 30 11:48:11 PDT 2015
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
// Design Name: ISE Instantiation template
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
chipscope_ila YourInstanceName (
|
||||
.CONTROL(CONTROL), // INOUT BUS [35:0]
|
||||
.CLK(CLK), // IN
|
||||
.TRIG0(TRIG0) // IN BUS [127:0]
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
@@ -0,0 +1,141 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.7
|
||||
# Date: Tue Jun 30 18:46:21 2015
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc6slx75
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = csg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -3
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET check_bramcount=false
|
||||
CSET component_name=chipscope_ila
|
||||
CSET constraint_type=external
|
||||
CSET counter_width_1=Disabled
|
||||
CSET counter_width_10=Disabled
|
||||
CSET counter_width_11=Disabled
|
||||
CSET counter_width_12=Disabled
|
||||
CSET counter_width_13=Disabled
|
||||
CSET counter_width_14=Disabled
|
||||
CSET counter_width_15=Disabled
|
||||
CSET counter_width_16=Disabled
|
||||
CSET counter_width_2=Disabled
|
||||
CSET counter_width_3=Disabled
|
||||
CSET counter_width_4=Disabled
|
||||
CSET counter_width_5=Disabled
|
||||
CSET counter_width_6=Disabled
|
||||
CSET counter_width_7=Disabled
|
||||
CSET counter_width_8=Disabled
|
||||
CSET counter_width_9=Disabled
|
||||
CSET data_port_width=0
|
||||
CSET data_same_as_trigger=true
|
||||
CSET disable_save_keep=false
|
||||
CSET enable_storage_qualification=true
|
||||
CSET enable_trigger_output_port=false
|
||||
CSET example_design=false
|
||||
CSET exclude_from_data_storage_1=false
|
||||
CSET exclude_from_data_storage_10=false
|
||||
CSET exclude_from_data_storage_11=false
|
||||
CSET exclude_from_data_storage_12=false
|
||||
CSET exclude_from_data_storage_13=false
|
||||
CSET exclude_from_data_storage_14=false
|
||||
CSET exclude_from_data_storage_15=false
|
||||
CSET exclude_from_data_storage_16=false
|
||||
CSET exclude_from_data_storage_2=false
|
||||
CSET exclude_from_data_storage_3=false
|
||||
CSET exclude_from_data_storage_4=false
|
||||
CSET exclude_from_data_storage_5=false
|
||||
CSET exclude_from_data_storage_6=false
|
||||
CSET exclude_from_data_storage_7=false
|
||||
CSET exclude_from_data_storage_8=false
|
||||
CSET exclude_from_data_storage_9=false
|
||||
CSET match_type_1=basic_with_edges
|
||||
CSET match_type_10=basic_with_edges
|
||||
CSET match_type_11=basic_with_edges
|
||||
CSET match_type_12=basic_with_edges
|
||||
CSET match_type_13=basic_with_edges
|
||||
CSET match_type_14=basic_with_edges
|
||||
CSET match_type_15=basic_with_edges
|
||||
CSET match_type_16=basic_with_edges
|
||||
CSET match_type_2=basic_with_edges
|
||||
CSET match_type_3=basic_with_edges
|
||||
CSET match_type_4=basic_with_edges
|
||||
CSET match_type_5=basic_with_edges
|
||||
CSET match_type_6=basic_with_edges
|
||||
CSET match_type_7=basic_with_edges
|
||||
CSET match_type_8=basic_with_edges
|
||||
CSET match_type_9=basic_with_edges
|
||||
CSET match_units_1=1
|
||||
CSET match_units_10=1
|
||||
CSET match_units_11=1
|
||||
CSET match_units_12=1
|
||||
CSET match_units_13=1
|
||||
CSET match_units_14=1
|
||||
CSET match_units_15=1
|
||||
CSET match_units_16=1
|
||||
CSET match_units_2=1
|
||||
CSET match_units_3=1
|
||||
CSET match_units_4=1
|
||||
CSET match_units_5=1
|
||||
CSET match_units_6=1
|
||||
CSET match_units_7=1
|
||||
CSET match_units_8=1
|
||||
CSET match_units_9=1
|
||||
CSET max_sequence_levels=1
|
||||
CSET number_of_trigger_ports=1
|
||||
CSET sample_data_depth=1024
|
||||
CSET sample_on=Rising
|
||||
CSET trigger_port_width_1=128
|
||||
CSET trigger_port_width_10=8
|
||||
CSET trigger_port_width_11=8
|
||||
CSET trigger_port_width_12=8
|
||||
CSET trigger_port_width_13=8
|
||||
CSET trigger_port_width_14=8
|
||||
CSET trigger_port_width_15=8
|
||||
CSET trigger_port_width_16=8
|
||||
CSET trigger_port_width_2=8
|
||||
CSET trigger_port_width_3=8
|
||||
CSET trigger_port_width_4=8
|
||||
CSET trigger_port_width_5=8
|
||||
CSET trigger_port_width_6=8
|
||||
CSET trigger_port_width_7=8
|
||||
CSET trigger_port_width_8=8
|
||||
CSET trigger_port_width_9=8
|
||||
CSET use_rpms=false
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2013-10-13T14:13:15Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 76868b6e
|
||||
@@ -0,0 +1,6 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
|
||||
set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
|
||||
set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
|
||||
@@ -0,0 +1,18 @@
|
||||
# Output products list for <chipscope_ila>
|
||||
_xmsgs/pn_parser.xmsgs
|
||||
chipscope_ila.asy
|
||||
chipscope_ila.cdc
|
||||
chipscope_ila.constraints/chipscope_ila.ucf
|
||||
chipscope_ila.constraints/chipscope_ila.xdc
|
||||
chipscope_ila.gise
|
||||
chipscope_ila.ncf
|
||||
chipscope_ila.ngc
|
||||
chipscope_ila.ucf
|
||||
chipscope_ila.v
|
||||
chipscope_ila.veo
|
||||
chipscope_ila.xco
|
||||
chipscope_ila.xdc
|
||||
chipscope_ila.xise
|
||||
chipscope_ila_flist.txt
|
||||
chipscope_ila_readme.txt
|
||||
chipscope_ila_xmdf.tcl
|
||||
@@ -0,0 +1,48 @@
|
||||
The following files were generated for 'chipscope_ila' in directory
|
||||
/home/mwest/git/fpgadev/usrp3/top/b205/coregen/
|
||||
|
||||
XCO file generator:
|
||||
Generate an XCO file for compatibility with legacy flows.
|
||||
|
||||
* chipscope_ila.xco
|
||||
|
||||
Creates an implementation netlist:
|
||||
Creates an implementation netlist for the IP.
|
||||
|
||||
* chipscope_ila.cdc
|
||||
* chipscope_ila.constraints/chipscope_ila.ucf
|
||||
* chipscope_ila.constraints/chipscope_ila.xdc
|
||||
* chipscope_ila.ncf
|
||||
* chipscope_ila.ngc
|
||||
* chipscope_ila.ucf
|
||||
* chipscope_ila.v
|
||||
* chipscope_ila.veo
|
||||
* chipscope_ila.xdc
|
||||
* chipscope_ila_xmdf.tcl
|
||||
|
||||
IP Symbol Generator:
|
||||
Generate an IP symbol based on the current project options'.
|
||||
|
||||
* chipscope_ila.asy
|
||||
|
||||
Generate ISE subproject:
|
||||
Create an ISE subproject for use when including this core in ISE designs
|
||||
|
||||
* _xmsgs/pn_parser.xmsgs
|
||||
* chipscope_ila.gise
|
||||
* chipscope_ila.xise
|
||||
|
||||
Deliver Readme:
|
||||
Readme file for the IP.
|
||||
|
||||
* chipscope_ila_readme.txt
|
||||
|
||||
Generate FLIST file:
|
||||
Text file listing all of the output files produced when a customized core was
|
||||
generated in the CORE Generator.
|
||||
|
||||
* chipscope_ila_flist.txt
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
Executable
+87
@@ -0,0 +1,87 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide chipscope_ila_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::chipscope_ila_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::chipscope_ila_xmdf::xmdfInit { instance } {
|
||||
# Variable containing name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila
|
||||
}
|
||||
# ::chipscope_ila_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::chipscope_ila_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.cdc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.constraints/chipscope_ila.ucf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
|
||||
incr fcount
|
||||
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.ncf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.constraints/chipscope_ila.xdc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
|
||||
@@ -0,0 +1,9 @@
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET designentry = Verilog
|
||||
SET device = xc6slx150
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET package = csg484
|
||||
SET speedgrade = -3
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
@@ -0,0 +1,49 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 fifo_4k_2clk
|
||||
RECTANGLE Normal 32 32 800 4064
|
||||
LINE Normal 0 112 32 112
|
||||
PIN 0 112 LEFT 36
|
||||
PINATTR PinName rst
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 208 32 208
|
||||
PIN 0 208 LEFT 36
|
||||
PINATTR PinName wr_clk
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 240 32 240
|
||||
PIN 0 240 LEFT 36
|
||||
PINATTR PinName din[71:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 272 32 272
|
||||
PIN 0 272 LEFT 36
|
||||
PINATTR PinName wr_en
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 464 32 464
|
||||
PIN 0 464 LEFT 36
|
||||
PINATTR PinName full
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 0 624 32 624
|
||||
PIN 0 624 LEFT 36
|
||||
PINATTR PinName wr_data_count[9:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 832 240 800 240
|
||||
PIN 832 240 RIGHT 36
|
||||
PINATTR PinName rd_clk
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 832 272 800 272
|
||||
PIN 832 272 RIGHT 36
|
||||
PINATTR PinName dout[71:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 832 304 800 304
|
||||
PIN 832 304 RIGHT 36
|
||||
PINATTR PinName rd_en
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 832 496 800 496
|
||||
PIN 832 496 RIGHT 36
|
||||
PINATTR PinName empty
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 832 656 800 656
|
||||
PIN 832 656 RIGHT 36
|
||||
PINATTR PinName rd_data_count[9:0]
|
||||
PINATTR Polarity OUT
|
||||
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,491 @@
|
||||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used solely *
|
||||
* for design, simulation, implementation and creation of design files *
|
||||
* limited to Xilinx devices or technologies. Use with non-Xilinx *
|
||||
* devices or technologies is expressly prohibited and immediately *
|
||||
* terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
|
||||
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
|
||||
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
|
||||
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
|
||||
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
|
||||
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
|
||||
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
|
||||
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
|
||||
* PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support appliances, *
|
||||
* devices, or systems. Use in such applications are expressly *
|
||||
* prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2015 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
// You must compile the wrapper file fifo_4k_2clk.v when simulating
|
||||
// the core, fifo_4k_2clk. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
// The synthesis directives "translate_off/translate_on" specified below are
|
||||
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
|
||||
// tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module fifo_4k_2clk(
|
||||
rst,
|
||||
wr_clk,
|
||||
rd_clk,
|
||||
din,
|
||||
wr_en,
|
||||
rd_en,
|
||||
dout,
|
||||
full,
|
||||
empty,
|
||||
rd_data_count,
|
||||
wr_data_count
|
||||
);
|
||||
|
||||
input rst;
|
||||
input wr_clk;
|
||||
input rd_clk;
|
||||
input [71 : 0] din;
|
||||
input wr_en;
|
||||
input rd_en;
|
||||
output [71 : 0] dout;
|
||||
output full;
|
||||
output empty;
|
||||
output [9 : 0] rd_data_count;
|
||||
output [9 : 0] wr_data_count;
|
||||
|
||||
// synthesis translate_off
|
||||
|
||||
FIFO_GENERATOR_V9_3 #(
|
||||
.C_ADD_NGC_CONSTRAINT(0),
|
||||
.C_APPLICATION_TYPE_AXIS(0),
|
||||
.C_APPLICATION_TYPE_RACH(0),
|
||||
.C_APPLICATION_TYPE_RDCH(0),
|
||||
.C_APPLICATION_TYPE_WACH(0),
|
||||
.C_APPLICATION_TYPE_WDCH(0),
|
||||
.C_APPLICATION_TYPE_WRCH(0),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_AXI_DATA_WIDTH(64),
|
||||
.C_AXI_ID_WIDTH(4),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_TYPE(0),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXIS_TDATA_WIDTH(64),
|
||||
.C_AXIS_TDEST_WIDTH(4),
|
||||
.C_AXIS_TID_WIDTH(8),
|
||||
.C_AXIS_TKEEP_WIDTH(4),
|
||||
.C_AXIS_TSTRB_WIDTH(4),
|
||||
.C_AXIS_TUSER_WIDTH(4),
|
||||
.C_AXIS_TYPE(0),
|
||||
.C_COMMON_CLOCK(0),
|
||||
.C_COUNT_TYPE(0),
|
||||
.C_DATA_COUNT_WIDTH(9),
|
||||
.C_DEFAULT_VALUE("BlankString"),
|
||||
.C_DIN_WIDTH(72),
|
||||
.C_DIN_WIDTH_AXIS(1),
|
||||
.C_DIN_WIDTH_RACH(32),
|
||||
.C_DIN_WIDTH_RDCH(64),
|
||||
.C_DIN_WIDTH_WACH(32),
|
||||
.C_DIN_WIDTH_WDCH(64),
|
||||
.C_DIN_WIDTH_WRCH(2),
|
||||
.C_DOUT_RST_VAL("0"),
|
||||
.C_DOUT_WIDTH(72),
|
||||
.C_ENABLE_RLOCS(0),
|
||||
.C_ENABLE_RST_SYNC(1),
|
||||
.C_ERROR_INJECTION_TYPE(0),
|
||||
.C_ERROR_INJECTION_TYPE_AXIS(0),
|
||||
.C_ERROR_INJECTION_TYPE_RACH(0),
|
||||
.C_ERROR_INJECTION_TYPE_RDCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WACH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WDCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WRCH(0),
|
||||
.C_FAMILY("spartan6"),
|
||||
.C_FULL_FLAGS_RST_VAL(1),
|
||||
.C_HAS_ALMOST_EMPTY(0),
|
||||
.C_HAS_ALMOST_FULL(0),
|
||||
.C_HAS_AXI_ARUSER(0),
|
||||
.C_HAS_AXI_AWUSER(0),
|
||||
.C_HAS_AXI_BUSER(0),
|
||||
.C_HAS_AXI_RD_CHANNEL(0),
|
||||
.C_HAS_AXI_RUSER(0),
|
||||
.C_HAS_AXI_WR_CHANNEL(0),
|
||||
.C_HAS_AXI_WUSER(0),
|
||||
.C_HAS_AXIS_TDATA(0),
|
||||
.C_HAS_AXIS_TDEST(0),
|
||||
.C_HAS_AXIS_TID(0),
|
||||
.C_HAS_AXIS_TKEEP(0),
|
||||
.C_HAS_AXIS_TLAST(0),
|
||||
.C_HAS_AXIS_TREADY(1),
|
||||
.C_HAS_AXIS_TSTRB(0),
|
||||
.C_HAS_AXIS_TUSER(0),
|
||||
.C_HAS_BACKUP(0),
|
||||
.C_HAS_DATA_COUNT(0),
|
||||
.C_HAS_DATA_COUNTS_AXIS(0),
|
||||
.C_HAS_DATA_COUNTS_RACH(0),
|
||||
.C_HAS_DATA_COUNTS_RDCH(0),
|
||||
.C_HAS_DATA_COUNTS_WACH(0),
|
||||
.C_HAS_DATA_COUNTS_WDCH(0),
|
||||
.C_HAS_DATA_COUNTS_WRCH(0),
|
||||
.C_HAS_INT_CLK(0),
|
||||
.C_HAS_MASTER_CE(0),
|
||||
.C_HAS_MEMINIT_FILE(0),
|
||||
.C_HAS_OVERFLOW(0),
|
||||
.C_HAS_PROG_FLAGS_AXIS(0),
|
||||
.C_HAS_PROG_FLAGS_RACH(0),
|
||||
.C_HAS_PROG_FLAGS_RDCH(0),
|
||||
.C_HAS_PROG_FLAGS_WACH(0),
|
||||
.C_HAS_PROG_FLAGS_WDCH(0),
|
||||
.C_HAS_PROG_FLAGS_WRCH(0),
|
||||
.C_HAS_RD_DATA_COUNT(1),
|
||||
.C_HAS_RD_RST(0),
|
||||
.C_HAS_RST(1),
|
||||
.C_HAS_SLAVE_CE(0),
|
||||
.C_HAS_SRST(0),
|
||||
.C_HAS_UNDERFLOW(0),
|
||||
.C_HAS_VALID(0),
|
||||
.C_HAS_WR_ACK(0),
|
||||
.C_HAS_WR_DATA_COUNT(1),
|
||||
.C_HAS_WR_RST(0),
|
||||
.C_IMPLEMENTATION_TYPE(2),
|
||||
.C_IMPLEMENTATION_TYPE_AXIS(1),
|
||||
.C_IMPLEMENTATION_TYPE_RACH(1),
|
||||
.C_IMPLEMENTATION_TYPE_RDCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_WACH(1),
|
||||
.C_IMPLEMENTATION_TYPE_WDCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_WRCH(1),
|
||||
.C_INIT_WR_PNTR_VAL(0),
|
||||
.C_INTERFACE_TYPE(0),
|
||||
.C_MEMORY_TYPE(1),
|
||||
.C_MIF_FILE_NAME("BlankString"),
|
||||
.C_MSGON_VAL(1),
|
||||
.C_OPTIMIZATION_MODE(0),
|
||||
.C_OVERFLOW_LOW(0),
|
||||
.C_PRELOAD_LATENCY(0),
|
||||
.C_PRELOAD_REGS(1),
|
||||
.C_PRIM_FIFO_TYPE("512x72"),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
|
||||
.C_PROG_EMPTY_TYPE(0),
|
||||
.C_PROG_EMPTY_TYPE_AXIS(0),
|
||||
.C_PROG_EMPTY_TYPE_RACH(0),
|
||||
.C_PROG_EMPTY_TYPE_RDCH(0),
|
||||
.C_PROG_EMPTY_TYPE_WACH(0),
|
||||
.C_PROG_EMPTY_TYPE_WDCH(0),
|
||||
.C_PROG_EMPTY_TYPE_WRCH(0),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL(511),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
|
||||
.C_PROG_FULL_THRESH_NEGATE_VAL(510),
|
||||
.C_PROG_FULL_TYPE(0),
|
||||
.C_PROG_FULL_TYPE_AXIS(0),
|
||||
.C_PROG_FULL_TYPE_RACH(0),
|
||||
.C_PROG_FULL_TYPE_RDCH(0),
|
||||
.C_PROG_FULL_TYPE_WACH(0),
|
||||
.C_PROG_FULL_TYPE_WDCH(0),
|
||||
.C_PROG_FULL_TYPE_WRCH(0),
|
||||
.C_RACH_TYPE(0),
|
||||
.C_RD_DATA_COUNT_WIDTH(10),
|
||||
.C_RD_DEPTH(512),
|
||||
.C_RD_FREQ(1),
|
||||
.C_RD_PNTR_WIDTH(9),
|
||||
.C_RDCH_TYPE(0),
|
||||
.C_REG_SLICE_MODE_AXIS(0),
|
||||
.C_REG_SLICE_MODE_RACH(0),
|
||||
.C_REG_SLICE_MODE_RDCH(0),
|
||||
.C_REG_SLICE_MODE_WACH(0),
|
||||
.C_REG_SLICE_MODE_WDCH(0),
|
||||
.C_REG_SLICE_MODE_WRCH(0),
|
||||
.C_SYNCHRONIZER_STAGE(2),
|
||||
.C_UNDERFLOW_LOW(0),
|
||||
.C_USE_COMMON_OVERFLOW(0),
|
||||
.C_USE_COMMON_UNDERFLOW(0),
|
||||
.C_USE_DEFAULT_SETTINGS(0),
|
||||
.C_USE_DOUT_RST(1),
|
||||
.C_USE_ECC(0),
|
||||
.C_USE_ECC_AXIS(0),
|
||||
.C_USE_ECC_RACH(0),
|
||||
.C_USE_ECC_RDCH(0),
|
||||
.C_USE_ECC_WACH(0),
|
||||
.C_USE_ECC_WDCH(0),
|
||||
.C_USE_ECC_WRCH(0),
|
||||
.C_USE_EMBEDDED_REG(0),
|
||||
.C_USE_FIFO16_FLAGS(0),
|
||||
.C_USE_FWFT_DATA_COUNT(1),
|
||||
.C_VALID_LOW(0),
|
||||
.C_WACH_TYPE(0),
|
||||
.C_WDCH_TYPE(0),
|
||||
.C_WR_ACK_LOW(0),
|
||||
.C_WR_DATA_COUNT_WIDTH(10),
|
||||
.C_WR_DEPTH(512),
|
||||
.C_WR_DEPTH_AXIS(1024),
|
||||
.C_WR_DEPTH_RACH(16),
|
||||
.C_WR_DEPTH_RDCH(1024),
|
||||
.C_WR_DEPTH_WACH(16),
|
||||
.C_WR_DEPTH_WDCH(1024),
|
||||
.C_WR_DEPTH_WRCH(16),
|
||||
.C_WR_FREQ(1),
|
||||
.C_WR_PNTR_WIDTH(9),
|
||||
.C_WR_PNTR_WIDTH_AXIS(10),
|
||||
.C_WR_PNTR_WIDTH_RACH(4),
|
||||
.C_WR_PNTR_WIDTH_RDCH(10),
|
||||
.C_WR_PNTR_WIDTH_WACH(4),
|
||||
.C_WR_PNTR_WIDTH_WDCH(10),
|
||||
.C_WR_PNTR_WIDTH_WRCH(4),
|
||||
.C_WR_RESPONSE_LATENCY(1),
|
||||
.C_WRCH_TYPE(0)
|
||||
)
|
||||
inst (
|
||||
.RST(rst),
|
||||
.WR_CLK(wr_clk),
|
||||
.RD_CLK(rd_clk),
|
||||
.DIN(din),
|
||||
.WR_EN(wr_en),
|
||||
.RD_EN(rd_en),
|
||||
.DOUT(dout),
|
||||
.FULL(full),
|
||||
.EMPTY(empty),
|
||||
.RD_DATA_COUNT(rd_data_count),
|
||||
.WR_DATA_COUNT(wr_data_count),
|
||||
.BACKUP(),
|
||||
.BACKUP_MARKER(),
|
||||
.CLK(),
|
||||
.SRST(),
|
||||
.WR_RST(),
|
||||
.RD_RST(),
|
||||
.PROG_EMPTY_THRESH(),
|
||||
.PROG_EMPTY_THRESH_ASSERT(),
|
||||
.PROG_EMPTY_THRESH_NEGATE(),
|
||||
.PROG_FULL_THRESH(),
|
||||
.PROG_FULL_THRESH_ASSERT(),
|
||||
.PROG_FULL_THRESH_NEGATE(),
|
||||
.INT_CLK(),
|
||||
.INJECTDBITERR(),
|
||||
.INJECTSBITERR(),
|
||||
.ALMOST_FULL(),
|
||||
.WR_ACK(),
|
||||
.OVERFLOW(),
|
||||
.ALMOST_EMPTY(),
|
||||
.VALID(),
|
||||
.UNDERFLOW(),
|
||||
.DATA_COUNT(),
|
||||
.PROG_FULL(),
|
||||
.PROG_EMPTY(),
|
||||
.SBITERR(),
|
||||
.DBITERR(),
|
||||
.M_ACLK(),
|
||||
.S_ACLK(),
|
||||
.S_ARESETN(),
|
||||
.M_ACLK_EN(),
|
||||
.S_ACLK_EN(),
|
||||
.S_AXI_AWID(),
|
||||
.S_AXI_AWADDR(),
|
||||
.S_AXI_AWLEN(),
|
||||
.S_AXI_AWSIZE(),
|
||||
.S_AXI_AWBURST(),
|
||||
.S_AXI_AWLOCK(),
|
||||
.S_AXI_AWCACHE(),
|
||||
.S_AXI_AWPROT(),
|
||||
.S_AXI_AWQOS(),
|
||||
.S_AXI_AWREGION(),
|
||||
.S_AXI_AWUSER(),
|
||||
.S_AXI_AWVALID(),
|
||||
.S_AXI_AWREADY(),
|
||||
.S_AXI_WID(),
|
||||
.S_AXI_WDATA(),
|
||||
.S_AXI_WSTRB(),
|
||||
.S_AXI_WLAST(),
|
||||
.S_AXI_WUSER(),
|
||||
.S_AXI_WVALID(),
|
||||
.S_AXI_WREADY(),
|
||||
.S_AXI_BID(),
|
||||
.S_AXI_BRESP(),
|
||||
.S_AXI_BUSER(),
|
||||
.S_AXI_BVALID(),
|
||||
.S_AXI_BREADY(),
|
||||
.M_AXI_AWID(),
|
||||
.M_AXI_AWADDR(),
|
||||
.M_AXI_AWLEN(),
|
||||
.M_AXI_AWSIZE(),
|
||||
.M_AXI_AWBURST(),
|
||||
.M_AXI_AWLOCK(),
|
||||
.M_AXI_AWCACHE(),
|
||||
.M_AXI_AWPROT(),
|
||||
.M_AXI_AWQOS(),
|
||||
.M_AXI_AWREGION(),
|
||||
.M_AXI_AWUSER(),
|
||||
.M_AXI_AWVALID(),
|
||||
.M_AXI_AWREADY(),
|
||||
.M_AXI_WID(),
|
||||
.M_AXI_WDATA(),
|
||||
.M_AXI_WSTRB(),
|
||||
.M_AXI_WLAST(),
|
||||
.M_AXI_WUSER(),
|
||||
.M_AXI_WVALID(),
|
||||
.M_AXI_WREADY(),
|
||||
.M_AXI_BID(),
|
||||
.M_AXI_BRESP(),
|
||||
.M_AXI_BUSER(),
|
||||
.M_AXI_BVALID(),
|
||||
.M_AXI_BREADY(),
|
||||
.S_AXI_ARID(),
|
||||
.S_AXI_ARADDR(),
|
||||
.S_AXI_ARLEN(),
|
||||
.S_AXI_ARSIZE(),
|
||||
.S_AXI_ARBURST(),
|
||||
.S_AXI_ARLOCK(),
|
||||
.S_AXI_ARCACHE(),
|
||||
.S_AXI_ARPROT(),
|
||||
.S_AXI_ARQOS(),
|
||||
.S_AXI_ARREGION(),
|
||||
.S_AXI_ARUSER(),
|
||||
.S_AXI_ARVALID(),
|
||||
.S_AXI_ARREADY(),
|
||||
.S_AXI_RID(),
|
||||
.S_AXI_RDATA(),
|
||||
.S_AXI_RRESP(),
|
||||
.S_AXI_RLAST(),
|
||||
.S_AXI_RUSER(),
|
||||
.S_AXI_RVALID(),
|
||||
.S_AXI_RREADY(),
|
||||
.M_AXI_ARID(),
|
||||
.M_AXI_ARADDR(),
|
||||
.M_AXI_ARLEN(),
|
||||
.M_AXI_ARSIZE(),
|
||||
.M_AXI_ARBURST(),
|
||||
.M_AXI_ARLOCK(),
|
||||
.M_AXI_ARCACHE(),
|
||||
.M_AXI_ARPROT(),
|
||||
.M_AXI_ARQOS(),
|
||||
.M_AXI_ARREGION(),
|
||||
.M_AXI_ARUSER(),
|
||||
.M_AXI_ARVALID(),
|
||||
.M_AXI_ARREADY(),
|
||||
.M_AXI_RID(),
|
||||
.M_AXI_RDATA(),
|
||||
.M_AXI_RRESP(),
|
||||
.M_AXI_RLAST(),
|
||||
.M_AXI_RUSER(),
|
||||
.M_AXI_RVALID(),
|
||||
.M_AXI_RREADY(),
|
||||
.S_AXIS_TVALID(),
|
||||
.S_AXIS_TREADY(),
|
||||
.S_AXIS_TDATA(),
|
||||
.S_AXIS_TSTRB(),
|
||||
.S_AXIS_TKEEP(),
|
||||
.S_AXIS_TLAST(),
|
||||
.S_AXIS_TID(),
|
||||
.S_AXIS_TDEST(),
|
||||
.S_AXIS_TUSER(),
|
||||
.M_AXIS_TVALID(),
|
||||
.M_AXIS_TREADY(),
|
||||
.M_AXIS_TDATA(),
|
||||
.M_AXIS_TSTRB(),
|
||||
.M_AXIS_TKEEP(),
|
||||
.M_AXIS_TLAST(),
|
||||
.M_AXIS_TID(),
|
||||
.M_AXIS_TDEST(),
|
||||
.M_AXIS_TUSER(),
|
||||
.AXI_AW_INJECTSBITERR(),
|
||||
.AXI_AW_INJECTDBITERR(),
|
||||
.AXI_AW_PROG_FULL_THRESH(),
|
||||
.AXI_AW_PROG_EMPTY_THRESH(),
|
||||
.AXI_AW_DATA_COUNT(),
|
||||
.AXI_AW_WR_DATA_COUNT(),
|
||||
.AXI_AW_RD_DATA_COUNT(),
|
||||
.AXI_AW_SBITERR(),
|
||||
.AXI_AW_DBITERR(),
|
||||
.AXI_AW_OVERFLOW(),
|
||||
.AXI_AW_UNDERFLOW(),
|
||||
.AXI_AW_PROG_FULL(),
|
||||
.AXI_AW_PROG_EMPTY(),
|
||||
.AXI_W_INJECTSBITERR(),
|
||||
.AXI_W_INJECTDBITERR(),
|
||||
.AXI_W_PROG_FULL_THRESH(),
|
||||
.AXI_W_PROG_EMPTY_THRESH(),
|
||||
.AXI_W_DATA_COUNT(),
|
||||
.AXI_W_WR_DATA_COUNT(),
|
||||
.AXI_W_RD_DATA_COUNT(),
|
||||
.AXI_W_SBITERR(),
|
||||
.AXI_W_DBITERR(),
|
||||
.AXI_W_OVERFLOW(),
|
||||
.AXI_W_UNDERFLOW(),
|
||||
.AXI_B_INJECTSBITERR(),
|
||||
.AXI_W_PROG_FULL(),
|
||||
.AXI_W_PROG_EMPTY(),
|
||||
.AXI_B_INJECTDBITERR(),
|
||||
.AXI_B_PROG_FULL_THRESH(),
|
||||
.AXI_B_PROG_EMPTY_THRESH(),
|
||||
.AXI_B_DATA_COUNT(),
|
||||
.AXI_B_WR_DATA_COUNT(),
|
||||
.AXI_B_RD_DATA_COUNT(),
|
||||
.AXI_B_SBITERR(),
|
||||
.AXI_B_DBITERR(),
|
||||
.AXI_B_OVERFLOW(),
|
||||
.AXI_B_UNDERFLOW(),
|
||||
.AXI_AR_INJECTSBITERR(),
|
||||
.AXI_B_PROG_FULL(),
|
||||
.AXI_B_PROG_EMPTY(),
|
||||
.AXI_AR_INJECTDBITERR(),
|
||||
.AXI_AR_PROG_FULL_THRESH(),
|
||||
.AXI_AR_PROG_EMPTY_THRESH(),
|
||||
.AXI_AR_DATA_COUNT(),
|
||||
.AXI_AR_WR_DATA_COUNT(),
|
||||
.AXI_AR_RD_DATA_COUNT(),
|
||||
.AXI_AR_SBITERR(),
|
||||
.AXI_AR_DBITERR(),
|
||||
.AXI_AR_OVERFLOW(),
|
||||
.AXI_AR_UNDERFLOW(),
|
||||
.AXI_AR_PROG_FULL(),
|
||||
.AXI_AR_PROG_EMPTY(),
|
||||
.AXI_R_INJECTSBITERR(),
|
||||
.AXI_R_INJECTDBITERR(),
|
||||
.AXI_R_PROG_FULL_THRESH(),
|
||||
.AXI_R_PROG_EMPTY_THRESH(),
|
||||
.AXI_R_DATA_COUNT(),
|
||||
.AXI_R_WR_DATA_COUNT(),
|
||||
.AXI_R_RD_DATA_COUNT(),
|
||||
.AXI_R_SBITERR(),
|
||||
.AXI_R_DBITERR(),
|
||||
.AXI_R_OVERFLOW(),
|
||||
.AXI_R_UNDERFLOW(),
|
||||
.AXIS_INJECTSBITERR(),
|
||||
.AXI_R_PROG_FULL(),
|
||||
.AXI_R_PROG_EMPTY(),
|
||||
.AXIS_INJECTDBITERR(),
|
||||
.AXIS_PROG_FULL_THRESH(),
|
||||
.AXIS_PROG_EMPTY_THRESH(),
|
||||
.AXIS_DATA_COUNT(),
|
||||
.AXIS_WR_DATA_COUNT(),
|
||||
.AXIS_RD_DATA_COUNT(),
|
||||
.AXIS_SBITERR(),
|
||||
.AXIS_DBITERR(),
|
||||
.AXIS_OVERFLOW(),
|
||||
.AXIS_UNDERFLOW(),
|
||||
.AXIS_PROG_FULL(),
|
||||
.AXIS_PROG_EMPTY()
|
||||
);
|
||||
|
||||
// synthesis translate_on
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,79 @@
|
||||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used solely *
|
||||
* for design, simulation, implementation and creation of design files *
|
||||
* limited to Xilinx devices or technologies. Use with non-Xilinx *
|
||||
* devices or technologies is expressly prohibited and immediately *
|
||||
* terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
|
||||
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
|
||||
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
|
||||
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
|
||||
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
|
||||
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
|
||||
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
|
||||
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
|
||||
* PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support appliances, *
|
||||
* devices, or systems. Use in such applications are expressly *
|
||||
* prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2015 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 *
|
||||
* *
|
||||
* Rev 1. The FIFO Generator is a parameterizable first-in/first-out *
|
||||
* memory queue generator. Use it to generate resource and performance *
|
||||
* optimized FIFOs with common or independent read/write clock domains, *
|
||||
* and optional fixed or programmable full and empty flags and *
|
||||
* handshaking signals. Choose from a selection of memory resource *
|
||||
* types for implementation. Optional Hamming code based error *
|
||||
* detection and correction as well as error injection capability for *
|
||||
* system test help to insure data integrity. FIFO width and depth are *
|
||||
* parameterizable, and for native interface FIFOs, asymmetric read and *
|
||||
* write port widths are also supported. *
|
||||
*******************************************************************************/
|
||||
|
||||
// Interfaces:
|
||||
// AXI4Stream_MASTER_M_AXIS
|
||||
// AXI4Stream_SLAVE_S_AXIS
|
||||
// AXI4_MASTER_M_AXI
|
||||
// AXI4_SLAVE_S_AXI
|
||||
// AXI4Lite_MASTER_M_AXI
|
||||
// AXI4Lite_SLAVE_S_AXI
|
||||
// master_aclk
|
||||
// slave_aclk
|
||||
// slave_aresetn
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
fifo_4k_2clk your_instance_name (
|
||||
.rst(rst), // input rst
|
||||
.wr_clk(wr_clk), // input wr_clk
|
||||
.rd_clk(rd_clk), // input rd_clk
|
||||
.din(din), // input [71 : 0] din
|
||||
.wr_en(wr_en), // input wr_en
|
||||
.rd_en(rd_en), // input rd_en
|
||||
.dout(dout), // output [71 : 0] dout
|
||||
.full(full), // output full
|
||||
.empty(empty), // output empty
|
||||
.rd_data_count(rd_data_count), // output [9 : 0] rd_data_count
|
||||
.wr_data_count(wr_data_count) // output [9 : 0] wr_data_count
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file fifo_4k_2clk.v when simulating
|
||||
// the core, fifo_4k_2clk. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
@@ -0,0 +1,213 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.7
|
||||
# Date: Thu Mar 26 19:28:41 2015
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:fifo_generator:9.3
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc6slx75
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = csg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -3
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET add_ngc_constraint_axi=false
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET aruser_width=1
|
||||
CSET awuser_width=1
|
||||
CSET axi_address_width=32
|
||||
CSET axi_data_width=64
|
||||
CSET axi_type=AXI4_Stream
|
||||
CSET axis_type=FIFO
|
||||
CSET buser_width=1
|
||||
CSET clock_enable_type=Slave_Interface_Clock_Enable
|
||||
CSET clock_type_axi=Common_Clock
|
||||
CSET component_name=fifo_4k_2clk
|
||||
CSET data_count=false
|
||||
CSET data_count_width=9
|
||||
CSET disable_timing_violations=false
|
||||
CSET disable_timing_violations_axi=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=4
|
||||
CSET empty_threshold_assert_value_axis=1022
|
||||
CSET empty_threshold_assert_value_rach=1022
|
||||
CSET empty_threshold_assert_value_rdch=1022
|
||||
CSET empty_threshold_assert_value_wach=1022
|
||||
CSET empty_threshold_assert_value_wdch=1022
|
||||
CSET empty_threshold_assert_value_wrch=1022
|
||||
CSET empty_threshold_negate_value=5
|
||||
CSET enable_aruser=false
|
||||
CSET enable_awuser=false
|
||||
CSET enable_buser=false
|
||||
CSET enable_common_overflow=false
|
||||
CSET enable_common_underflow=false
|
||||
CSET enable_data_counts_axis=false
|
||||
CSET enable_data_counts_rach=false
|
||||
CSET enable_data_counts_rdch=false
|
||||
CSET enable_data_counts_wach=false
|
||||
CSET enable_data_counts_wdch=false
|
||||
CSET enable_data_counts_wrch=false
|
||||
CSET enable_ecc=false
|
||||
CSET enable_ecc_axis=false
|
||||
CSET enable_ecc_rach=false
|
||||
CSET enable_ecc_rdch=false
|
||||
CSET enable_ecc_wach=false
|
||||
CSET enable_ecc_wdch=false
|
||||
CSET enable_ecc_wrch=false
|
||||
CSET enable_read_channel=false
|
||||
CSET enable_read_pointer_increment_by2=false
|
||||
CSET enable_reset_synchronization=true
|
||||
CSET enable_ruser=false
|
||||
CSET enable_tdata=false
|
||||
CSET enable_tdest=false
|
||||
CSET enable_tid=false
|
||||
CSET enable_tkeep=false
|
||||
CSET enable_tlast=false
|
||||
CSET enable_tready=true
|
||||
CSET enable_tstrobe=false
|
||||
CSET enable_tuser=false
|
||||
CSET enable_write_channel=false
|
||||
CSET enable_wuser=false
|
||||
CSET fifo_application_type_axis=Data_FIFO
|
||||
CSET fifo_application_type_rach=Data_FIFO
|
||||
CSET fifo_application_type_rdch=Data_FIFO
|
||||
CSET fifo_application_type_wach=Data_FIFO
|
||||
CSET fifo_application_type_wdch=Data_FIFO
|
||||
CSET fifo_application_type_wrch=Data_FIFO
|
||||
CSET fifo_implementation=Independent_Clocks_Block_RAM
|
||||
CSET fifo_implementation_axis=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_rach=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_wach=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=511
|
||||
CSET full_threshold_assert_value_axis=1023
|
||||
CSET full_threshold_assert_value_rach=1023
|
||||
CSET full_threshold_assert_value_rdch=1023
|
||||
CSET full_threshold_assert_value_wach=1023
|
||||
CSET full_threshold_assert_value_wdch=1023
|
||||
CSET full_threshold_assert_value_wrch=1023
|
||||
CSET full_threshold_negate_value=510
|
||||
CSET id_width=4
|
||||
CSET inject_dbit_error=false
|
||||
CSET inject_dbit_error_axis=false
|
||||
CSET inject_dbit_error_rach=false
|
||||
CSET inject_dbit_error_rdch=false
|
||||
CSET inject_dbit_error_wach=false
|
||||
CSET inject_dbit_error_wdch=false
|
||||
CSET inject_dbit_error_wrch=false
|
||||
CSET inject_sbit_error=false
|
||||
CSET inject_sbit_error_axis=false
|
||||
CSET inject_sbit_error_rach=false
|
||||
CSET inject_sbit_error_rdch=false
|
||||
CSET inject_sbit_error_wach=false
|
||||
CSET inject_sbit_error_wdch=false
|
||||
CSET inject_sbit_error_wrch=false
|
||||
CSET input_data_width=72
|
||||
CSET input_depth=512
|
||||
CSET input_depth_axis=1024
|
||||
CSET input_depth_rach=16
|
||||
CSET input_depth_rdch=1024
|
||||
CSET input_depth_wach=16
|
||||
CSET input_depth_wdch=1024
|
||||
CSET input_depth_wrch=16
|
||||
CSET interface_type=Native
|
||||
CSET output_data_width=72
|
||||
CSET output_depth=512
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_flag_axi=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET overflow_sense_axi=Active_High
|
||||
CSET performance_options=First_Word_Fall_Through
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
|
||||
CSET rach_type=FIFO
|
||||
CSET rdch_type=FIFO
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=true
|
||||
CSET read_data_count_width=10
|
||||
CSET register_slice_mode_axis=Fully_Registered
|
||||
CSET register_slice_mode_rach=Fully_Registered
|
||||
CSET register_slice_mode_rdch=Fully_Registered
|
||||
CSET register_slice_mode_wach=Fully_Registered
|
||||
CSET register_slice_mode_wdch=Fully_Registered
|
||||
CSET register_slice_mode_wrch=Fully_Registered
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET ruser_width=1
|
||||
CSET synchronization_stages=2
|
||||
CSET synchronization_stages_axi=2
|
||||
CSET tdata_width=64
|
||||
CSET tdest_width=4
|
||||
CSET tid_width=8
|
||||
CSET tkeep_width=4
|
||||
CSET tstrb_width=4
|
||||
CSET tuser_width=4
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_flag_axi=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET underflow_sense_axi=Active_High
|
||||
CSET use_clock_enable=false
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=true
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET wach_type=FIFO
|
||||
CSET wdch_type=FIFO
|
||||
CSET wrch_type=FIFO
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=true
|
||||
CSET write_data_count_width=10
|
||||
CSET wuser_width=1
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-11-19T12:39:56Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: d3cdd696
|
||||
@@ -0,0 +1,236 @@
|
||||
CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
|
||||
|
||||
Release Date: December 18, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.4 software support
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.4 software support
|
||||
- IP level constraint for Built-in FIFO reset synchronizer
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v9.3 Rev 1 of this core at time of release:
|
||||
|
||||
1. Importing an XCO file alters the XCO configurations
|
||||
|
||||
Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
|
||||
into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
|
||||
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
|
||||
|
||||
CR 467240
|
||||
AR 31379
|
||||
|
||||
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
|
||||
|
||||
Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
|
||||
correct behavior of the FIFO status flags cannot be guaranteed after the first write.
|
||||
|
||||
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
|
||||
For more information and additional workaround see Answer Record 41099.
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v9.3 Rev 1 of this core at time of release:
|
||||
|
||||
1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
|
||||
ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
|
||||
|
||||
CR 665836
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes User Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
|
||||
10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
|
||||
07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
|
||||
04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
|
||||
01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
|
||||
10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support
|
||||
06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
|
||||
03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
|
||||
10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
|
||||
09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
|
||||
07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
|
||||
06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
|
||||
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
|
||||
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
|
||||
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
|
||||
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
|
||||
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
|
||||
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
|
||||
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
|
||||
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
|
||||
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
|
||||
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
|
||||
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
|
||||
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
|
||||
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
|
||||
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
|
||||
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
|
||||
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
@@ -0,0 +1,247 @@
|
||||
<HTML>
|
||||
<HEAD>
|
||||
<TITLE>fifo_generator_v9_3_vinfo</TITLE>
|
||||
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
|
||||
</HEAD>
|
||||
<BODY>
|
||||
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
|
||||
CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
|
||||
|
||||
Release Date: December 18, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
|
||||
|
||||
For system requirements:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
<A HREF="http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm">www.xilinx.com/products/ipcenter/FIFO_Generator.htm</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.4 software support
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.4 software support
|
||||
- IP level constraint for Built-in FIFO reset synchronizer
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v9.3 Rev 1 of this core at time of release:
|
||||
|
||||
1. Importing an XCO file alters the XCO configurations
|
||||
|
||||
Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
|
||||
into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
|
||||
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
|
||||
|
||||
CR 467240
|
||||
AR 31379
|
||||
|
||||
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
|
||||
|
||||
Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
|
||||
correct behavior of the FIFO status flags cannot be guaranteed after the first write.
|
||||
|
||||
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
|
||||
For more information and additional workaround see Answer Record 41099.
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v9.3 Rev 1 of this core at time of release:
|
||||
|
||||
1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
|
||||
ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
|
||||
|
||||
CR 665836
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes User Guide
|
||||
located at
|
||||
|
||||
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
|
||||
10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
|
||||
07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
|
||||
04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
|
||||
01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
|
||||
10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support
|
||||
06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
|
||||
03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
|
||||
10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
|
||||
09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
|
||||
07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
|
||||
06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
|
||||
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
|
||||
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
|
||||
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
|
||||
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
|
||||
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
|
||||
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
|
||||
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
|
||||
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
|
||||
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
|
||||
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
|
||||
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
|
||||
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
|
||||
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
|
||||
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
|
||||
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
|
||||
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
</FONT>
|
||||
</PRE>
|
||||
</BODY>
|
||||
</HTML>
|
||||
Binary file not shown.
@@ -0,0 +1,56 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Core Period Constraint. This constraint can be modified, and is
|
||||
# valid as long as it is met after place and route.
|
||||
NET "RD_CLK" TNM_NET = "RD_CLK";
|
||||
NET "WR_CLK" TNM_NET = "WR_CLK";
|
||||
TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" 50 MHZ;
|
||||
TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 50 MHZ;
|
||||
################################################################################
|
||||
@@ -0,0 +1,145 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core - core top file for implementation
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: fifo_4k_2clk_exdes.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the FIFO core wrapper with BUFG instances for clock connections.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
--------------------------------------------------------------------------------
|
||||
entity fifo_4k_2clk_exdes is
|
||||
PORT (
|
||||
WR_CLK : IN std_logic;
|
||||
RD_CLK : IN std_logic;
|
||||
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
|
||||
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
|
||||
RST : IN std_logic;
|
||||
WR_EN : IN std_logic;
|
||||
RD_EN : IN std_logic;
|
||||
DIN : IN std_logic_vector(72-1 DOWNTO 0);
|
||||
DOUT : OUT std_logic_vector(72-1 DOWNTO 0);
|
||||
FULL : OUT std_logic;
|
||||
EMPTY : OUT std_logic);
|
||||
|
||||
end fifo_4k_2clk_exdes;
|
||||
|
||||
|
||||
|
||||
architecture xilinx of fifo_4k_2clk_exdes is
|
||||
|
||||
signal wr_clk_i : std_logic;
|
||||
signal rd_clk_i : std_logic;
|
||||
|
||||
|
||||
|
||||
component fifo_4k_2clk is
|
||||
PORT (
|
||||
WR_CLK : IN std_logic;
|
||||
RD_CLK : IN std_logic;
|
||||
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
|
||||
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
|
||||
RST : IN std_logic;
|
||||
WR_EN : IN std_logic;
|
||||
RD_EN : IN std_logic;
|
||||
DIN : IN std_logic_vector(72-1 DOWNTO 0);
|
||||
DOUT : OUT std_logic_vector(72-1 DOWNTO 0);
|
||||
FULL : OUT std_logic;
|
||||
EMPTY : OUT std_logic);
|
||||
|
||||
end component;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
wr_clk_buf: bufg
|
||||
PORT map(
|
||||
i => WR_CLK,
|
||||
o => wr_clk_i
|
||||
);
|
||||
|
||||
rd_clk_buf: bufg
|
||||
PORT map(
|
||||
i => RD_CLK,
|
||||
o => rd_clk_i
|
||||
);
|
||||
|
||||
|
||||
exdes_inst : fifo_4k_2clk
|
||||
PORT MAP (
|
||||
WR_CLK => wr_clk_i,
|
||||
RD_CLK => rd_clk_i,
|
||||
WR_DATA_COUNT => wr_data_count,
|
||||
RD_DATA_COUNT => rd_data_count,
|
||||
RST => rst,
|
||||
WR_EN => wr_en,
|
||||
RD_EN => rd_en,
|
||||
DIN => din,
|
||||
DOUT => dout,
|
||||
FULL => full,
|
||||
EMPTY => empty);
|
||||
|
||||
end xilinx;
|
||||
@@ -0,0 +1,236 @@
|
||||
CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
|
||||
|
||||
Release Date: December 18, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.4 software support
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.4 software support
|
||||
- IP level constraint for Built-in FIFO reset synchronizer
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v9.3 Rev 1 of this core at time of release:
|
||||
|
||||
1. Importing an XCO file alters the XCO configurations
|
||||
|
||||
Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
|
||||
into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
|
||||
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
|
||||
|
||||
CR 467240
|
||||
AR 31379
|
||||
|
||||
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
|
||||
|
||||
Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
|
||||
correct behavior of the FIFO status flags cannot be guaranteed after the first write.
|
||||
|
||||
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
|
||||
For more information and additional workaround see Answer Record 41099.
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v9.3 Rev 1 of this core at time of release:
|
||||
|
||||
1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
|
||||
ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
|
||||
|
||||
CR 665836
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes User Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
|
||||
10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
|
||||
07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
|
||||
04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
|
||||
01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
|
||||
10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support
|
||||
06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
|
||||
03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
|
||||
10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
|
||||
09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
|
||||
07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
|
||||
06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
|
||||
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
|
||||
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
|
||||
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
|
||||
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
|
||||
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
|
||||
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
|
||||
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
|
||||
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
|
||||
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
|
||||
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
|
||||
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
|
||||
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
|
||||
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
|
||||
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
|
||||
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
|
||||
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
@@ -0,0 +1,88 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
rem Clean up the results directory
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
|
||||
rem Synthesize the VHDL Wrapper Files
|
||||
|
||||
#Synthesize the Wrapper Files
|
||||
|
||||
echo 'Synthesizing example design with XST';
|
||||
xst -ifn xst.scr
|
||||
copy fifo_4k_2clk_exdes.ngc .\results\
|
||||
|
||||
|
||||
rem Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
copy ..\..\fifo_4k_2clk.ngc results\
|
||||
|
||||
|
||||
rem Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
copy ..\example_design\fifo_4k_2clk_exdes.ucf results\
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
|
||||
ngdbuild -p xc6slx75-csg484-3 -sd ../../../ fifo_4k_2clk_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map fifo_4k_2clk_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level Verilog model'
|
||||
netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user