Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
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|
||||
@echo off
|
||||
|
||||
rem PlanAhead(TM)
|
||||
rem launch.bat: a PlanAhead-generated ExploreAhead Script
|
||||
rem Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
setlocal
|
||||
|
||||
set HD_LDIR=%~dp0
|
||||
|
||||
rem *** Create Queue Clues
|
||||
set HD_RUNDIR=%HD_LDIR%\../impl_1
|
||||
if exist "%HD_RUNDIR%" echo. > "%HD_RUNDIR%/.ISE.queue.rst"
|
||||
|
||||
|
||||
rem *** Launch Runs (one at a time)
|
||||
set HD_RUNBAT=%HD_LDIR%\../impl_1\runme.bat
|
||||
if exist "%HD_RUNBAT%" call "%HD_RUNBAT%" %*
|
||||
|
||||
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# PlanAhead(TM)
|
||||
# launch.sh: a PlanAhead-generated ExploreAhead Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LDIR=`dirname "$0"`
|
||||
|
||||
# *** Create Queue Clues
|
||||
HD_RUNDIR="$HD_LDIR/../impl_1"
|
||||
if [ -d "$HD_RUNDIR" ]
|
||||
then
|
||||
/bin/touch "$HD_RUNDIR/.ISE.queue.rst"
|
||||
fi
|
||||
|
||||
|
||||
# *** Launch Runs (one at a time)
|
||||
HD_RUNSH="$HD_LDIR/../impl_1/runme.sh"
|
||||
if [ -f "$HD_RUNSH" ]
|
||||
then
|
||||
"$HD_RUNSH"
|
||||
fi
|
||||
|
||||
|
||||
@@ -0,0 +1,317 @@
|
||||
## SPI Nets
|
||||
|
||||
NET "cat_ce" LOC = Y1;
|
||||
NET "cat_ce" IOSTANDARD = LVCMOS18;
|
||||
NET "cat_miso" LOC = V1;
|
||||
NET "cat_miso" IOSTANDARD = LVCMOS18;
|
||||
NET "cat_mosi" LOC = T4;
|
||||
NET "cat_mosi" IOSTANDARD = LVCMOS18;
|
||||
NET "cat_sclk" LOC = P7;
|
||||
NET "cat_sclk" IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "fx3_ce" LOC = H20;
|
||||
NET "fx3_miso" LOC = G20;
|
||||
NET "fx3_mosi" LOC = AA20;
|
||||
NET "fx3_sclk" LOC = Y21;
|
||||
|
||||
NET "pll_ce" LOC = W11;
|
||||
NET "pll_mosi" LOC = AB11;
|
||||
NET "pll_sclk" LOC = Y12;
|
||||
|
||||
NET "FPGA_RXD0" LOC = AB8;
|
||||
NET "FPGA_TXD0" LOC = AB7;
|
||||
|
||||
NET "SCL_FPGA" LOC = P21;
|
||||
NET "SDA_FPGA" LOC = W22;
|
||||
|
||||
## Catalina Controls
|
||||
|
||||
NET "codec_enable" LOC = J6;
|
||||
NET "codec_enable" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_en_agc" LOC = P6;
|
||||
NET "codec_en_agc" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_reset" LOC = Y2;
|
||||
NET "codec_reset" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_sync" LOC = M3;
|
||||
NET "codec_sync" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_txrx" LOC = M7;
|
||||
NET "codec_txrx" IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "codec_ctrl_in[0]" LOC = E3;
|
||||
NET "codec_ctrl_in[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in[1]" LOC = F2;
|
||||
NET "codec_ctrl_in[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in[2]" LOC = F1;
|
||||
NET "codec_ctrl_in[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in[3]" LOC = E1;
|
||||
NET "codec_ctrl_in[3]" IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "codec_ctrl_out[0]" LOC = D1;
|
||||
NET "codec_ctrl_out[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[1]" LOC = C1;
|
||||
NET "codec_ctrl_out[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[2]" LOC = H3;
|
||||
NET "codec_ctrl_out[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[3]" LOC = F3;
|
||||
NET "codec_ctrl_out[3]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[4]" LOC = P1;
|
||||
NET "codec_ctrl_out[4]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[5]" LOC = J1;
|
||||
NET "codec_ctrl_out[5]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[6]" LOC = B1;
|
||||
NET "codec_ctrl_out[6]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[7]" LOC = H2;
|
||||
NET "codec_ctrl_out[7]" IOSTANDARD = LVCMOS18;
|
||||
|
||||
## Catalina Data RX
|
||||
|
||||
NET "rx_codec_d[0]" LOC = T2;
|
||||
NET "rx_codec_d[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[0]" DRIVE = 4;
|
||||
NET "rx_codec_d[1]" LOC = R1;
|
||||
NET "rx_codec_d[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[1]" DRIVE = 4;
|
||||
NET "rx_codec_d[2]" LOC = V2;
|
||||
NET "rx_codec_d[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[2]" DRIVE = 4;
|
||||
NET "rx_codec_d[3]" LOC = N1;
|
||||
NET "rx_codec_d[3]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[3]" DRIVE = 4;
|
||||
NET "rx_codec_d[4]" LOC = V3;
|
||||
NET "rx_codec_d[4]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[4]" DRIVE = 4;
|
||||
NET "rx_codec_d[5]" LOC = T1;
|
||||
NET "rx_codec_d[5]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[5]" DRIVE = 4;
|
||||
NET "rx_codec_d[6]" LOC = W1;
|
||||
NET "rx_codec_d[6]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[6]" DRIVE = 4;
|
||||
NET "rx_codec_d[7]" LOC = U1;
|
||||
NET "rx_codec_d[7]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[7]" DRIVE = 4;
|
||||
NET "rx_codec_d[8]" LOC = W3;
|
||||
NET "rx_codec_d[8]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[8]" DRIVE = 4;
|
||||
NET "rx_codec_d[9]" LOC = U3;
|
||||
NET "rx_codec_d[9]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[9]" DRIVE = 4;
|
||||
NET "rx_codec_d[10]" LOC = P2;
|
||||
NET "rx_codec_d[10]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[10]" DRIVE = 4;
|
||||
NET "rx_codec_d[11]" LOC = R3;
|
||||
NET "rx_codec_d[11]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[11]" DRIVE = 4;
|
||||
|
||||
## Catalina Data TX
|
||||
|
||||
NET "tx_codec_d[0]" LOC = M1;
|
||||
NET "tx_codec_d[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[0]" DRIVE = 4;
|
||||
NET "tx_codec_d[1]" LOC = K1;
|
||||
NET "tx_codec_d[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[1]" DRIVE = 4;
|
||||
NET "tx_codec_d[2]" LOC = L3;
|
||||
NET "tx_codec_d[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[2]" DRIVE = 4;
|
||||
NET "tx_codec_d[3]" LOC = K2;
|
||||
NET "tx_codec_d[3]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[3]" DRIVE = 4;
|
||||
NET "tx_codec_d[4]" LOC = M4;
|
||||
NET "tx_codec_d[4]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[4]" DRIVE = 4;
|
||||
NET "tx_codec_d[5]" LOC = J4;
|
||||
NET "tx_codec_d[5]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[5]" DRIVE = 4;
|
||||
NET "tx_codec_d[6]" LOC = L4;
|
||||
NET "tx_codec_d[6]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[6]" DRIVE = 4;
|
||||
NET "tx_codec_d[7]" LOC = H1;
|
||||
NET "tx_codec_d[7]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[7]" DRIVE = 4;
|
||||
NET "tx_codec_d[8]" LOC = M2;
|
||||
NET "tx_codec_d[8]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[8]" DRIVE = 4;
|
||||
NET "tx_codec_d[9]" LOC = G1;
|
||||
NET "tx_codec_d[9]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[9]" DRIVE = 4;
|
||||
NET "tx_codec_d[10]" LOC = N3;
|
||||
NET "tx_codec_d[10]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[10]" DRIVE = 4;
|
||||
NET "tx_codec_d[11]" LOC = G3;
|
||||
NET "tx_codec_d[11]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[11]" DRIVE = 4;
|
||||
|
||||
## Catalina Clocks
|
||||
|
||||
NET "cat_clkout_fpga" LOC = J3;
|
||||
NET "cat_clkout_fpga" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_data_clk_p" LOC = K3;
|
||||
NET "codec_data_clk_p" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_fb_clk_p" LOC = P3;
|
||||
NET "codec_fb_clk_p" IOSTANDARD = LVCMOS18;
|
||||
# | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_main_clk_p" LOC = K5;
|
||||
# | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_main_clk_n" LOC = K4;
|
||||
|
||||
NET "rx_frame_p" LOC = U4;
|
||||
NET "rx_frame_p" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_frame_p" LOC = T3;
|
||||
NET "tx_frame_p" IOSTANDARD = LVCMOS18;
|
||||
|
||||
## Debug Bus
|
||||
|
||||
NET "debug[0]" LOC = C14;
|
||||
NET "debug[1]" LOC = F15;
|
||||
NET "debug[2]" LOC = A18;
|
||||
NET "debug[3]" LOC = A17;
|
||||
NET "debug[4]" LOC = E14;
|
||||
NET "debug[5]" LOC = G13;
|
||||
NET "debug[6]" LOC = D13;
|
||||
NET "debug[7]" LOC = F13;
|
||||
NET "debug[8]" LOC = D8;
|
||||
NET "debug[9]" LOC = A6;
|
||||
NET "debug[10]" LOC = D7;
|
||||
NET "debug[11]" LOC = A5;
|
||||
NET "debug[12]" LOC = B6;
|
||||
NET "debug[13]" LOC = A3;
|
||||
NET "debug[14]" LOC = A7;
|
||||
NET "debug[15]" LOC = A8;
|
||||
NET "debug[16]" LOC = B18;
|
||||
NET "debug[17]" LOC = C17;
|
||||
NET "debug[18]" LOC = H13;
|
||||
NET "debug[19]" LOC = D12;
|
||||
NET "debug[20]" LOC = H14;
|
||||
NET "debug[21]" LOC = C10;
|
||||
NET "debug[22]" LOC = D10;
|
||||
NET "debug[23]" LOC = C8;
|
||||
NET "debug[24]" LOC = D9;
|
||||
NET "debug[25]" LOC = C5;
|
||||
NET "debug[26]" LOC = A9;
|
||||
NET "debug[27]" LOC = B8;
|
||||
NET "debug[28]" LOC = A4;
|
||||
NET "debug[29]" LOC = C7;
|
||||
NET "debug[30]" LOC = C6;
|
||||
NET "debug[31]" LOC = D6;
|
||||
|
||||
NET "debug_clk[0]" LOC = A12;
|
||||
NET "debug_clk[1]" LOC = C12;
|
||||
|
||||
## GPIF
|
||||
|
||||
NET "IFCLK" LOC = H21;
|
||||
NET "FX3_EXTINT" LOC = U20;
|
||||
|
||||
NET "GPIF_CTL0" LOC = V20;
|
||||
NET "GPIF_CTL1" LOC = T22;
|
||||
NET "GPIF_CTL2" LOC = R22;
|
||||
NET "GPIF_CTL3" LOC = U22;
|
||||
NET "GPIF_CTL4" LOC = P19;
|
||||
NET "GPIF_CTL5" LOC = N22;
|
||||
NET "GPIF_CTL6" LOC = T21;
|
||||
NET "GPIF_CTL7" LOC = V21;
|
||||
NET "GPIF_CTL8" LOC = K18;
|
||||
NET "GPIF_CTL9" LOC = R20;
|
||||
##GPIF_CTL10 is "FPGA_CFG_DONE", defined later.
|
||||
NET "GPIF_CTL11" LOC = P22;
|
||||
NET "GPIF_CTL12" LOC = M20;
|
||||
|
||||
NET "GPIF_D[0]" LOC = T17;
|
||||
NET "GPIF_D[1]" LOC = U14;
|
||||
NET "GPIF_D[2]" LOC = U13;
|
||||
NET "GPIF_D[3]" LOC = AA6;
|
||||
NET "GPIF_D[4]" LOC = AB6;
|
||||
NET "GPIF_D[5]" LOC = Y3;
|
||||
NET "GPIF_D[6]" LOC = AB3;
|
||||
NET "GPIF_D[7]" LOC = AA4;
|
||||
NET "GPIF_D[8]" LOC = AA2;
|
||||
NET "GPIF_D[9]" LOC = AB2;
|
||||
NET "GPIF_D[10]" LOC = AB19;
|
||||
NET "GPIF_D[11]" LOC = AA18;
|
||||
NET "GPIF_D[12]" LOC = AB18;
|
||||
NET "GPIF_D[13]" LOC = Y13;
|
||||
NET "GPIF_D[14]" LOC = AA12;
|
||||
NET "GPIF_D[15]" LOC = AB12;
|
||||
NET "GPIF_D[16]" LOC = N20;
|
||||
NET "GPIF_D[17]" LOC = L20;
|
||||
NET "GPIF_D[18]" LOC = N19;
|
||||
NET "GPIF_D[19]" LOC = M22;
|
||||
NET "GPIF_D[20]" LOC = L19;
|
||||
NET "GPIF_D[21]" LOC = M21;
|
||||
NET "GPIF_D[22]" LOC = M19;
|
||||
NET "GPIF_D[23]" LOC = K22;
|
||||
NET "GPIF_D[24]" LOC = J20;
|
||||
NET "GPIF_D[25]" LOC = L22;
|
||||
NET "GPIF_D[26]" LOC = K19;
|
||||
NET "GPIF_D[27]" LOC = H22;
|
||||
NET "GPIF_D[28]" LOC = J22;
|
||||
NET "GPIF_D[29]" LOC = K20;
|
||||
NET "GPIF_D[30]" LOC = G22;
|
||||
NET "GPIF_D[31]" LOC = F22;
|
||||
|
||||
## GPS
|
||||
|
||||
NET "gps_lock" LOC = Y17;
|
||||
NET "gps_out_enable" LOC = V22;
|
||||
NET "gps_ref_enable" LOC = AB13;
|
||||
NET "gps_rxd" LOC = AB14;
|
||||
NET "gps_txd" LOC = W12;
|
||||
NET "gps_txd_nmea" LOC = AA14;
|
||||
|
||||
## LEDS
|
||||
|
||||
NET "LED_RX1" LOC = C22;
|
||||
NET "LED_RX2" LOC = L15;
|
||||
NET "LED_TXRX1_TX" LOC = C20;
|
||||
NET "LED_TXRX2_RX" LOC = D21;
|
||||
NET "LED_TXRX1_RX" LOC = K16;
|
||||
NET "LED_TXRX2_TX" LOC = D22;
|
||||
|
||||
## Misc Hardware Control
|
||||
|
||||
NET "ext_ref_enable" LOC = Y15;
|
||||
NET "pll_lock" LOC = AB10;
|
||||
NET "AUX_PWR_ON" LOC = AA21;
|
||||
#NET "RFUSE" LOC = "P15" ;
|
||||
|
||||
## PPS
|
||||
|
||||
NET "pps_fpga_out_enable" LOC = AB15;
|
||||
NET "PPS_IN_EXT" LOC = AB16;
|
||||
NET "PPS_IN_INT" LOC = AB21;
|
||||
NET "pps_out" LOC = AB17;
|
||||
|
||||
## RF Hardware Control
|
||||
|
||||
NET "SFDX1_RX" LOC = W4;
|
||||
NET "SFDX1_TX" LOC = T18;
|
||||
NET "SFDX2_RX" LOC = F18;
|
||||
NET "SFDX2_TX" LOC = H17;
|
||||
NET "SRX1_RX" LOC = Y7;
|
||||
NET "SRX1_TX" LOC = AA8;
|
||||
NET "SRX2_RX" LOC = J17;
|
||||
NET "SRX2_TX" LOC = F19;
|
||||
NET "tx_bandsel_a" LOC = N16;
|
||||
NET "tx_bandsel_b" LOC = M16;
|
||||
NET "tx_enable1" LOC = Y4;
|
||||
NET "tx_enable2" LOC = R19;
|
||||
NET "rx_bandsel_a" LOC = T20;
|
||||
NET "rx_bandsel_b" LOC = U19;
|
||||
NET "rx_bandsel_c" LOC = P20;
|
||||
|
||||
## FPGA Config Pins
|
||||
|
||||
#NET "FPGA_CFG_INIT_B" LOC = "T6" ;
|
||||
#NET "FPGA_CFG_DONE" LOC = "Y22" ;
|
||||
#NET "FPGA_CFG_M0" LOC = "AA22" ;
|
||||
#NET "FPGA_CFG_M1" LOC = "U15" ;
|
||||
#NET "FPGA_CFG_PROG_B" LOC = "AA1" ;
|
||||
|
||||
## Special Pins
|
||||
|
||||
#NET "VFS" LOC = "P16" ;
|
||||
#NET "TMS" LOC = "C18" ;
|
||||
#NET "TDO" LOC = "A19" ;
|
||||
#NET "TDI" LOC = "E18" ;
|
||||
#NET "TCK" LOC = "G15" ;
|
||||
#NET "GND" LOC = "N15" ;
|
||||
@@ -0,0 +1,85 @@
|
||||
|
||||
# codec_main_clk is 40 MHz main tcxo clock
|
||||
NET "codec_main_clk*" TNM_NET = "codec_main_clk";
|
||||
TIMESPEC TS_codec_main_clk = PERIOD "codec_main_clk" 25000 ps HIGH 50 %;
|
||||
|
||||
|
||||
# IFCLK is 100 MHz GPIF clock
|
||||
NET "IFCLK" TNM_NET = "IFCLK";
|
||||
TIMESPEC TS_IFCLK = PERIOD "IFCLK" 10000 ps HIGH 50 %;
|
||||
|
||||
|
||||
# codec_data_clk is the data clock from catalina, sample rate dependent
|
||||
# this clock equals sample rate in CMOS DDR 1R1T mode
|
||||
# this clock is double the sample rate in CMOS DDR 2R2T mode
|
||||
# Max clock rate is 61.44 MHz
|
||||
NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p";
|
||||
TIMESPEC TS_codec_data_clk_p = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %;
|
||||
|
||||
|
||||
#always use IOB for GPIF pins for awesome timing
|
||||
INST "GPIF_D_9_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_8_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_7_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_6_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_5_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_4_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_3_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_31_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_30_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_2_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_29_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_28_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_27_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_26_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_25_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_24_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_23_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_22_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_21_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_20_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_1_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL0_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL11_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL12_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL1_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL2_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL3_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL4_IBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL5_IBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL7_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL9_IBUF" IOB =TRUE;
|
||||
INST "GPIF_D_0_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_10_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_11_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_12_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_13_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_14_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_15_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_16_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_17_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_18_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_19_IOBUF" IOB =TRUE;
|
||||
|
||||
# TODO not working... constraints ignored
|
||||
|
||||
#constrain FX3 IO
|
||||
INST "GPIF_D[*]" TNM = "gpif_net_out";
|
||||
INST "GPIF_D[*]" TNM = "gpif_net_in";
|
||||
INST "GPIF_CTL0" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL1" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL2" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL3" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL4" TNM = "gpif_net_in";
|
||||
INST "GPIF_CTL5" TNM = "gpif_net_in";
|
||||
INST "GPIF_CTL6" TNM = gpif_net_in;
|
||||
INST "GPIF_CTL7" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL8" TNM = gpif_net_in;
|
||||
INST "GPIF_CTL11" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL12" TNM = "gpif_net_out";
|
||||
|
||||
#NET "gpif_clk" TNM_NET = "TNM_gpif_clk";
|
||||
#OFFSET = OUT 5 ns AFTER "gpif_clk";
|
||||
#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %;
|
||||
#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING;
|
||||
#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING;
|
||||
@@ -0,0 +1,196 @@
|
||||
//
|
||||
// PlanAhead(TM)
|
||||
// ISEWrap.js: ExploreAhead Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2010 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
return ISEFileSys.OpenTextFile( ISEFullPath, 8, true );
|
||||
}
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# PlanAhead(TM)
|
||||
# ISEWrap.sh: ExploreAhead Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2010 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,341 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE twReport [
|
||||
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
|
||||
twDebug*, twFoot?, twClientInfo?)>
|
||||
<!ATTLIST twReport version CDATA "10,4">
|
||||
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
|
||||
<!ELEMENT twExecVer (#PCDATA)>
|
||||
<!ELEMENT twCopyright (#PCDATA)>
|
||||
<!ELEMENT twCmdLine (#PCDATA)>
|
||||
<!ELEMENT twDesign (#PCDATA)>
|
||||
<!ELEMENT twPCF (#PCDATA)>
|
||||
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
|
||||
<!ELEMENT twDevName (#PCDATA)>
|
||||
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
|
||||
<!ELEMENT twSpeedGrade (#PCDATA)>
|
||||
<!ELEMENT twSpeedVer (#PCDATA)>
|
||||
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
|
||||
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
|
||||
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
|
||||
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
|
||||
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
|
||||
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twItemLimit (#PCDATA)>
|
||||
<!ELEMENT twUnconst EMPTY>
|
||||
<!ELEMENT twUnconstLimit (#PCDATA)>
|
||||
<!ELEMENT twEnvVar EMPTY>
|
||||
<!ATTLIST twEnvVar name CDATA #REQUIRED>
|
||||
<!ATTLIST twEnvVar description CDATA #REQUIRED>
|
||||
<!ELEMENT twWarn (#PCDATA)>
|
||||
<!ELEMENT twInfo (#PCDATA)>
|
||||
<!ELEMENT twDebug (#PCDATA)>
|
||||
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
|
||||
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
|
||||
<!ELEMENT twProc (#PCDATA)>
|
||||
<!ELEMENT twTemp (#PCDATA)>
|
||||
<!ELEMENT twVolt (#PCDATA)>
|
||||
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
|
||||
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
|
||||
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twCycles (twSigConn+)>
|
||||
<!ATTLIST twCycles twNum CDATA #REQUIRED>
|
||||
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
|
||||
<!ELEMENT twSig (#PCDATA)>
|
||||
<!ELEMENT twDriver (#PCDATA)>
|
||||
<!ELEMENT twLoad (#PCDATA)>
|
||||
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
|
||||
<!ATTLIST twConst twConstType (NET |
|
||||
NETDELAY |
|
||||
NETSKEW |
|
||||
PATH |
|
||||
DEFPERIOD |
|
||||
UNCONSTPATH |
|
||||
DEFPATH |
|
||||
PATH2SETUP |
|
||||
UNCONSTPATH2SETUP |
|
||||
PATHCLASS |
|
||||
PATHDELAY |
|
||||
PERIOD |
|
||||
FREQUENCY |
|
||||
PATHBLOCK |
|
||||
OFFSET |
|
||||
OFFSETIN |
|
||||
OFFSETINCLOCK |
|
||||
UNCONSTOFFSETINCLOCK |
|
||||
OFFSETINDELAY |
|
||||
OFFSETINMOD |
|
||||
OFFSETOUT |
|
||||
OFFSETOUTCLOCK |
|
||||
UNCONSTOFFSETOUTCLOCK |
|
||||
OFFSETOUTDELAY |
|
||||
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
|
||||
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
|
||||
twEndPtCnt?,
|
||||
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
|
||||
<!ELEMENT twConstName (#PCDATA)>
|
||||
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
|
||||
<!ATTLIST twConstHead uID CDATA #IMPLIED>
|
||||
<!ELEMENT twItemCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCntEndPt (#PCDATA)>
|
||||
<!ELEMENT twErrCntSetup (#PCDATA)>
|
||||
<!ELEMENT twErrCntHold (#PCDATA)>
|
||||
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twEndPtCnt (#PCDATA)>
|
||||
<!ELEMENT twPathErrCnt (#PCDATA)>
|
||||
<!ELEMENT twMinPer (#PCDATA) >
|
||||
<!ELEMENT twFootnote EMPTY>
|
||||
<!ATTLIST twFootnote number CDATA #REQUIRED>
|
||||
<!ELEMENT twMaxDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFreq (#PCDATA)>
|
||||
<!ELEMENT twMinOff (#PCDATA)>
|
||||
<!ELEMENT twMaxOff (#PCDATA)>
|
||||
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
|
||||
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
|
||||
<!ELEMENT twTIGName (#PCDATA)>
|
||||
<!ELEMENT twInstantiated (#PCDATA)>
|
||||
<!ELEMENT twBlocked (#PCDATA)>
|
||||
<!ELEMENT twRacePathRpt (twRacePath+)>
|
||||
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
|
||||
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
|
||||
twSimpleMinPath CDATA #IMPLIED>
|
||||
<!ELEMENT twTotDel (#PCDATA)>
|
||||
<!ELEMENT twSrc (#PCDATA)>
|
||||
<!ATTLIST twSrc BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDest (#PCDATA)>
|
||||
<!ATTLIST twDest BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDel (#PCDATA)>
|
||||
<!ELEMENT twSUTime (#PCDATA)>
|
||||
<!ELEMENT twTotPathDel (#PCDATA)>
|
||||
<!ELEMENT twClkSkew (#PCDATA)>
|
||||
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
|
||||
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
|
||||
<!ELEMENT twSlack (#PCDATA)>
|
||||
<!ELEMENT twDelConst (#PCDATA)>
|
||||
<!ELEMENT tw2Phase EMPTY>
|
||||
<!ELEMENT twClkUncert (#PCDATA)>
|
||||
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
|
||||
fDCMJit CDATA #IMPLIED
|
||||
fPhaseErr CDATA #IMPLIED
|
||||
sEqu CDATA #IMPLIED>
|
||||
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
|
||||
<!ELEMENT twPathRptBanner (#PCDATA)>
|
||||
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twOff (#PCDATA)>
|
||||
<!ELEMENT twGuaranteed EMPTY>
|
||||
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
|
||||
<!ELEMENT twClkDel (#PCDATA)>
|
||||
<!ELEMENT twClkSrc (#PCDATA)>
|
||||
<!ELEMENT twClkDest (#PCDATA)>
|
||||
<!ELEMENT twGuarInSetup (#PCDATA)>
|
||||
<!ELEMENT twOffSrc (#PCDATA)>
|
||||
<!ELEMENT twOffDest (#PCDATA)>
|
||||
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ELEMENT twDataDel (#PCDATA)>
|
||||
<!ELEMENT twDataSrc (#PCDATA)>
|
||||
<!ELEMENT twDataDest (#PCDATA)>
|
||||
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
|
||||
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twLogLvls (#PCDATA)>
|
||||
<!ELEMENT twSrcSite (#PCDATA)>
|
||||
<!ELEMENT twSrcClk (#PCDATA)>
|
||||
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
|
||||
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twDelInfo (#PCDATA)>
|
||||
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twSite (#PCDATA)>
|
||||
<!ELEMENT twDelType (#PCDATA)>
|
||||
<!ELEMENT twFanCnt (#PCDATA)>
|
||||
<!ELEMENT twComp (#PCDATA)>
|
||||
<!ELEMENT twNet (#PCDATA)>
|
||||
<!ELEMENT twBEL (#PCDATA)>
|
||||
<!ELEMENT twLogDel (#PCDATA)>
|
||||
<!ELEMENT twRouteDel (#PCDATA)>
|
||||
<!ELEMENT twDestClk (#PCDATA)>
|
||||
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPctLog (#PCDATA)>
|
||||
<!ELEMENT twPctRoute (#PCDATA)>
|
||||
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
|
||||
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
|
||||
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
|
||||
<!ELEMENT twTimeConst (#PCDATA)>
|
||||
<!ELEMENT twAbsSlack (#PCDATA)>
|
||||
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
|
||||
<!ELEMENT twSkew (#PCDATA)>
|
||||
<!ELEMENT twDetNet (twNetDel*)>
|
||||
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
|
||||
<!ELEMENT twNetDelInfo (#PCDATA)>
|
||||
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twDetSkewNet (twNetSkew*)>
|
||||
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
|
||||
<!ELEMENT twClkSkewLimit EMPTY>
|
||||
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
|
||||
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollupTable (twConstRollup*)>
|
||||
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollup EMPTY>
|
||||
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
|
||||
<!ELEMENT twConstList (twConstListItem)*>
|
||||
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
|
||||
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
|
||||
<!ELEMENT twNotMet EMPTY>
|
||||
<!ELEMENT twReqVal (#PCDATA)>
|
||||
<!ELEMENT twActVal (#PCDATA)>
|
||||
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
|
||||
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
|
||||
<!ELEMENT twConstStats (twConstName)>
|
||||
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
|
||||
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
|
||||
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
|
||||
<!ELEMENT twConstData EMPTY>
|
||||
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
|
||||
best CDATA #IMPLIED requested CDATA #IMPLIED
|
||||
errors CDATA #IMPLIED
|
||||
score CDATA #IMPLIED>
|
||||
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
|
||||
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
|
||||
<!ELEMENT twTimeGrpName (#PCDATA)>
|
||||
<!ELEMENT twCompList (twCompName+)>
|
||||
<!ELEMENT twCompName (#PCDATA)>
|
||||
<!ELEMENT twSigList (twSigName+)>
|
||||
<!ELEMENT twSigName (#PCDATA)>
|
||||
<!ELEMENT twBELList (twBELName+)>
|
||||
<!ELEMENT twBELName (#PCDATA)>
|
||||
<!ELEMENT twBlockList (twBlockName+)>
|
||||
<!ELEMENT twBlockName (#PCDATA)>
|
||||
<!ELEMENT twMacList (twMacName+)>
|
||||
<!ELEMENT twMacName (#PCDATA)>
|
||||
<!ELEMENT twPinList (twPinName+)>
|
||||
<!ELEMENT twPinName (#PCDATA)>
|
||||
<!ELEMENT twUnmetConstCnt (#PCDATA)>
|
||||
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
|
||||
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
|
||||
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
|
||||
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
|
||||
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
|
||||
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
|
||||
<!ELEMENT twSU2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twH2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
|
||||
<!ELEMENT twClk2Pad (twDest, twTime)>
|
||||
<!ELEMENT twTime (#PCDATA)>
|
||||
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
|
||||
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2Out EMPTY>
|
||||
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
|
||||
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
|
||||
<!ELEMENT twRiseRise (#PCDATA)>
|
||||
<!ELEMENT twFallRise (#PCDATA)>
|
||||
<!ELEMENT twRiseFall (#PCDATA)>
|
||||
<!ELEMENT twFallFall (#PCDATA)>
|
||||
<!ELEMENT twPad2PadList (twPad2Pad+)>
|
||||
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
|
||||
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
|
||||
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
|
||||
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
|
||||
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
|
||||
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffOutTblRow EMPTY>
|
||||
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
|
||||
<!ELEMENT twNonDedClk (#PCDATA)>
|
||||
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
|
||||
<!ELEMENT twScore (#PCDATA)>
|
||||
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
|
||||
<!ELEMENT twPathCnt (#PCDATA)>
|
||||
<!ELEMENT twNetCnt (#PCDATA)>
|
||||
<!ELEMENT twConnCnt (#PCDATA)>
|
||||
<!ELEMENT twPct (#PCDATA)>
|
||||
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
|
||||
<!ELEMENT twMaxCombDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFromToDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetSkew (#PCDATA)>
|
||||
<!ELEMENT twMaxInAfterClk (#PCDATA)>
|
||||
<!ELEMENT twMinInBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMinOutAfterClk (#PCDATA)>
|
||||
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
|
||||
<!ELEMENT twTimestamp (#PCDATA)>
|
||||
<!ELEMENT twFootnoteExplanation EMPTY>
|
||||
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
|
||||
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
|
||||
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
|
||||
<!ELEMENT twClientName (#PCDATA)>
|
||||
<!ELEMENT twAttrList (twAttrListItem)*>
|
||||
<!ELEMENT twAttrListItem (twName, twValue*)>
|
||||
<!ELEMENT twName (#PCDATA)>
|
||||
<!ELEMENT twValue (#PCDATA)>
|
||||
]>
|
||||
<twReport><twHead anchorID="1"><twExecVer>Release 14.1 Trace (lin64)</twExecVer><twCopyright>Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>/opt/Xilinx/14.1/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -e 10 -s 3
|
||||
-n 3 -fastpaths -xml b200.twx b200.ncd -o b200.twr b200.pcf
|
||||
|
||||
</twCmdLine><twDesign>b200.ncd</twDesign><twDesignPath>b200.ncd</twDesignPath><twPCF>b200.pcf</twPCF><twPcfPath>b200.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="fgg484"><twDevName>xc6slx75</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRODUCTION 1.21 2012-04-23</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twErr" twReportMinPaths="true" dlyHyperLnks="t" ><twItemLimit>10</twItemLimit><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twErrRpt><twConst anchorID="5" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="" ScopeName="">TS_codec_main_clk = PERIOD TIMEGRP "codec_main_clk" 25 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>16.000</twMinPer></twConstHead><twPinLimitRpt anchorID="6"><twPinLimitBanner>Component Switching Limit Checks: TS_codec_main_clk = PERIOD TIMEGRP "codec_main_clk" 25 ns HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConst anchorID="7" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="" ScopeName="">TS_IFCLK = PERIOD TIMEGRP "IFCLK" 10 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt></twConstHead><twPinLimitRpt anchorID="8"><twPinLimitBanner>Component Switching Limit Checks: TS_IFCLK = PERIOD TIMEGRP "IFCLK" 10 ns HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConst anchorID="9" twConstType="PERIOD" ><twConstHead uID="3"><twConstName UCFConstName="" ScopeName="">TS_codec_data_clk_p = PERIOD TIMEGRP "codec_data_clk_p" 16.276 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.639</twMinPer></twConstHead><twPinLimitRpt anchorID="10"><twPinLimitBanner>Component Switching Limit Checks: TS_codec_data_clk_p = PERIOD TIMEGRP "codec_data_clk_p" 16.276 ns HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConst anchorID="11" twConstType="PERIOD" ><twConstHead uID="4"><twConstName UCFConstName="" ScopeName="">TS_gen_clks_clkfx = PERIOD TIMEGRP "gen_clks_clkfx" TS_codec_main_clk / 2.5 HIGH 50%;</twConstName><twItemCnt>48903</twItemCnt><twErrCntSetup>2</twErrCntSetup><twErrCntEndPt>2</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>9931</twEndPtCnt><twPathErrCnt>2</twPathErrCnt><twMinPer>12.189</twMinPer></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point slave_fifo32/EP_READY1 (OLOGIC_X4Y173.D1), 1 path
|
||||
</twPathRptBanner><twPathRpt anchorID="12"><twConstPath anchorID="13" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-2.189</twSlack><twSrc BELType="FF">slave_fifo32/EP_READY</twSrc><twDest BELType="FF">slave_fifo32/EP_READY1</twDest><twTotPathDel>12.263</twTotPathDel><twClkSkew dest = "1.637" src = "1.328">-0.309</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.400" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.235</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>slave_fifo32/EP_READY</twSrc><twDest BELType='FF'>slave_fifo32/EP_READY1</twDest><twLogLvls>0</twLogLvls><twSrcSite>ILOGIC_X17Y55.CLK0</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">gpif_clk</twSrcClk><twPathDel><twSite>ILOGIC_X17Y55.Q4</twSite><twDelType>Tickq</twDelType><twDelInfo twEdge="twRising">0.992</twDelInfo><twComp>slave_fifo32/EP_READY</twComp><twBEL>slave_fifo32/EP_READY</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X4Y173.D1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">10.468</twDelInfo><twComp>slave_fifo32/EP_READY</twComp></twPathDel><twPathDel><twSite>OLOGIC_X4Y173.CLK0</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.803</twDelInfo><twComp>slave_fifo32/EP_READY1</twComp><twBEL>slave_fifo32/EP_READY1</twBEL></twPathDel><twLogDel>1.795</twLogDel><twRouteDel>10.468</twRouteDel><twTotDel>12.263</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">gpif_clk</twDestClk><twPctLog>14.6</twPctLog><twPctRoute>85.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point slave_fifo32/EP_WMARK1 (OLOGIC_X2Y175.D1), 1 path
|
||||
</twPathRptBanner><twPathRpt anchorID="14"><twConstPath anchorID="15" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-1.341</twSlack><twSrc BELType="FF">slave_fifo32/EP_WMARK</twSrc><twDest BELType="FF">slave_fifo32/EP_WMARK1</twDest><twTotPathDel>11.029</twTotPathDel><twClkSkew dest = "1.642" src = "1.719">0.077</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.400" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.235</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>slave_fifo32/EP_WMARK</twSrc><twDest BELType='FF'>slave_fifo32/EP_WMARK1</twDest><twLogLvls>0</twLogLvls><twSrcSite>ILOGIC_X17Y78.CLK0</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">gpif_clk</twSrcClk><twPathDel><twSite>ILOGIC_X17Y78.Q4</twSite><twDelType>Tickq</twDelType><twDelInfo twEdge="twRising">0.992</twDelInfo><twComp>slave_fifo32/EP_WMARK</twComp><twBEL>slave_fifo32/EP_WMARK</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X2Y175.D1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">9.234</twDelInfo><twComp>slave_fifo32/EP_WMARK</twComp></twPathDel><twPathDel><twSite>OLOGIC_X2Y175.CLK0</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.803</twDelInfo><twComp>slave_fifo32/EP_WMARK1</twComp><twBEL>slave_fifo32/EP_WMARK1</twBEL></twPathDel><twLogDel>1.795</twLogDel><twRouteDel>9.234</twRouteDel><twTotDel>11.029</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">gpif_clk</twDestClk><twPctLog>16.3</twPctLog><twPctRoute>83.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="16"><twPinLimitBanner>Component Switching Limit Checks: TS_gen_clks_clkfx = PERIOD TIMEGRP "gen_clks_clkfx" TS_codec_main_clk / 2.5
|
||||
HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConstRollupTable uID="1" anchorID="17"><twConstRollup name="TS_codec_main_clk" fullName="TS_codec_main_clk = PERIOD TIMEGRP "codec_main_clk" 25 ns HIGH 50%;" type="origin" depth="0" requirement="25.000" prefType="period" actual="16.000" actualRollup="30.473" errors="0" errorRollup="2" items="0" itemsRollup="48903"/><twConstRollup name="TS_gen_clks_clkfx" fullName="TS_gen_clks_clkfx = PERIOD TIMEGRP "gen_clks_clkfx" TS_codec_main_clk / 2.5 HIGH 50%;" type="child" depth="1" requirement="10.000" prefType="period" actual="12.189" actualRollup="N/A" errors="2" errorRollup="0" items="48903" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="18">1</twUnmetConstCnt><twDataSheet anchorID="19" twNameLen="16"><twClk2SUList anchorID="20" twDestWidth="16"><twDest>codec_main_clk_n</twDest><twClk2SU><twSrc>codec_main_clk_n</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU><twClk2SU><twSrc>codec_main_clk_p</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="21" twDestWidth="16"><twDest>codec_main_clk_p</twDest><twClk2SU><twSrc>codec_main_clk_n</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU><twClk2SU><twSrc>codec_main_clk_p</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twErrRpt></twBody><twSum anchorID="22"><twErrCnt>2</twErrCnt><twScore>3530</twScore><twSetupScore>3530</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>48903</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>12388</twConnCnt></twConstCov><twStats anchorID="23"><twMinPer>16.000</twMinPer><twMaxFreq>62.500</twMaxFreq></twStats></twSum><twFoot><twTimestamp>Tue Jan 29 17:12:06 2013 </twTimestamp></twFoot><twClientInfo anchorID="24"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
|
||||
|
||||
Peak Memory Usage: 536 MB
|
||||
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
|
||||
@@ -0,0 +1,415 @@
|
||||
|
||||
####################################################################################
|
||||
# Generated by PlanAhead 14.4 built on 'Tue Dec 18 05:17:28 MST 2012' by 'xbuild'
|
||||
####################################################################################
|
||||
|
||||
|
||||
####################################################################################
|
||||
# Constraints from file : 'b200.ucf'
|
||||
####################################################################################
|
||||
|
||||
## SPI Nets
|
||||
|
||||
NET "cat_ce" LOC = Y1;
|
||||
NET "cat_ce" IOSTANDARD = LVCMOS18;
|
||||
NET "cat_miso" LOC = V1;
|
||||
NET "cat_miso" IOSTANDARD = LVCMOS18;
|
||||
NET "cat_mosi" LOC = T4;
|
||||
NET "cat_mosi" IOSTANDARD = LVCMOS18;
|
||||
NET "cat_sclk" LOC = P7;
|
||||
NET "cat_sclk" IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "fx3_ce" LOC = H20;
|
||||
NET "fx3_miso" LOC = G20;
|
||||
NET "fx3_mosi" LOC = AA20;
|
||||
NET "fx3_sclk" LOC = Y21;
|
||||
|
||||
NET "pll_ce" LOC = W11;
|
||||
NET "pll_mosi" LOC = AB11;
|
||||
NET "pll_sclk" LOC = Y12;
|
||||
|
||||
NET "FPGA_RXD0" LOC = AB8;
|
||||
NET "FPGA_TXD0" LOC = AB7;
|
||||
|
||||
NET "SCL_FPGA" LOC = P21;
|
||||
NET "SDA_FPGA" LOC = W22;
|
||||
|
||||
## Catalina Controls
|
||||
|
||||
NET "codec_enable" LOC = J6;
|
||||
NET "codec_enable" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_en_agc" LOC = P6;
|
||||
NET "codec_en_agc" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_reset" LOC = Y2;
|
||||
NET "codec_reset" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_sync" LOC = M3;
|
||||
NET "codec_sync" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_txrx" LOC = M7;
|
||||
NET "codec_txrx" IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "codec_ctrl_in[0]" LOC = E3;
|
||||
NET "codec_ctrl_in[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in[1]" LOC = F2;
|
||||
NET "codec_ctrl_in[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in[2]" LOC = F1;
|
||||
NET "codec_ctrl_in[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in[3]" LOC = E1;
|
||||
NET "codec_ctrl_in[3]" IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "codec_ctrl_out[0]" LOC = D1;
|
||||
NET "codec_ctrl_out[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[1]" LOC = C1;
|
||||
NET "codec_ctrl_out[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[2]" LOC = H3;
|
||||
NET "codec_ctrl_out[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[3]" LOC = F3;
|
||||
NET "codec_ctrl_out[3]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[4]" LOC = P1;
|
||||
NET "codec_ctrl_out[4]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[5]" LOC = J1;
|
||||
NET "codec_ctrl_out[5]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[6]" LOC = B1;
|
||||
NET "codec_ctrl_out[6]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[7]" LOC = H2;
|
||||
NET "codec_ctrl_out[7]" IOSTANDARD = LVCMOS18;
|
||||
|
||||
## Catalina Data RX
|
||||
|
||||
NET "rx_codec_d[0]" LOC = T2;
|
||||
NET "rx_codec_d[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[0]" DRIVE = 4;
|
||||
NET "rx_codec_d[1]" LOC = R1;
|
||||
NET "rx_codec_d[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[1]" DRIVE = 4;
|
||||
NET "rx_codec_d[2]" LOC = V2;
|
||||
NET "rx_codec_d[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[2]" DRIVE = 4;
|
||||
NET "rx_codec_d[3]" LOC = N1;
|
||||
NET "rx_codec_d[3]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[3]" DRIVE = 4;
|
||||
NET "rx_codec_d[4]" LOC = V3;
|
||||
NET "rx_codec_d[4]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[4]" DRIVE = 4;
|
||||
NET "rx_codec_d[5]" LOC = T1;
|
||||
NET "rx_codec_d[5]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[5]" DRIVE = 4;
|
||||
NET "rx_codec_d[6]" LOC = W1;
|
||||
NET "rx_codec_d[6]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[6]" DRIVE = 4;
|
||||
NET "rx_codec_d[7]" LOC = U1;
|
||||
NET "rx_codec_d[7]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[7]" DRIVE = 4;
|
||||
NET "rx_codec_d[8]" LOC = W3;
|
||||
NET "rx_codec_d[8]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[8]" DRIVE = 4;
|
||||
NET "rx_codec_d[9]" LOC = U3;
|
||||
NET "rx_codec_d[9]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[9]" DRIVE = 4;
|
||||
NET "rx_codec_d[10]" LOC = P2;
|
||||
NET "rx_codec_d[10]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[10]" DRIVE = 4;
|
||||
NET "rx_codec_d[11]" LOC = R3;
|
||||
NET "rx_codec_d[11]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[11]" DRIVE = 4;
|
||||
|
||||
## Catalina Data TX
|
||||
|
||||
NET "tx_codec_d[0]" LOC = M1;
|
||||
NET "tx_codec_d[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[0]" DRIVE = 4;
|
||||
NET "tx_codec_d[1]" LOC = K1;
|
||||
NET "tx_codec_d[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[1]" DRIVE = 4;
|
||||
NET "tx_codec_d[2]" LOC = L3;
|
||||
NET "tx_codec_d[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[2]" DRIVE = 4;
|
||||
NET "tx_codec_d[3]" LOC = K2;
|
||||
NET "tx_codec_d[3]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[3]" DRIVE = 4;
|
||||
NET "tx_codec_d[4]" LOC = M4;
|
||||
NET "tx_codec_d[4]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[4]" DRIVE = 4;
|
||||
NET "tx_codec_d[5]" LOC = J4;
|
||||
NET "tx_codec_d[5]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[5]" DRIVE = 4;
|
||||
NET "tx_codec_d[6]" LOC = L4;
|
||||
NET "tx_codec_d[6]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[6]" DRIVE = 4;
|
||||
NET "tx_codec_d[7]" LOC = H1;
|
||||
NET "tx_codec_d[7]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[7]" DRIVE = 4;
|
||||
NET "tx_codec_d[8]" LOC = M2;
|
||||
NET "tx_codec_d[8]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[8]" DRIVE = 4;
|
||||
NET "tx_codec_d[9]" LOC = G1;
|
||||
NET "tx_codec_d[9]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[9]" DRIVE = 4;
|
||||
NET "tx_codec_d[10]" LOC = N3;
|
||||
NET "tx_codec_d[10]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[10]" DRIVE = 4;
|
||||
NET "tx_codec_d[11]" LOC = G3;
|
||||
NET "tx_codec_d[11]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[11]" DRIVE = 4;
|
||||
|
||||
## Catalina Clocks
|
||||
|
||||
NET "cat_clkout_fpga" LOC = J3;
|
||||
NET "cat_clkout_fpga" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_data_clk_p" LOC = K3;
|
||||
NET "codec_data_clk_p" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_fb_clk_p" LOC = P3;
|
||||
NET "codec_fb_clk_p" IOSTANDARD = LVCMOS18;
|
||||
# | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_main_clk_p" LOC = K5;
|
||||
# | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_main_clk_n" LOC = K4;
|
||||
|
||||
NET "rx_frame_p" LOC = U4;
|
||||
NET "rx_frame_p" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_frame_p" LOC = T3;
|
||||
NET "tx_frame_p" IOSTANDARD = LVCMOS18;
|
||||
|
||||
## Debug Bus
|
||||
|
||||
NET "debug[0]" LOC = C14;
|
||||
NET "debug[1]" LOC = F15;
|
||||
NET "debug[2]" LOC = A18;
|
||||
NET "debug[3]" LOC = A17;
|
||||
NET "debug[4]" LOC = E14;
|
||||
NET "debug[5]" LOC = G13;
|
||||
NET "debug[6]" LOC = D13;
|
||||
NET "debug[7]" LOC = F13;
|
||||
NET "debug[8]" LOC = D8;
|
||||
NET "debug[9]" LOC = A6;
|
||||
NET "debug[10]" LOC = D7;
|
||||
NET "debug[11]" LOC = A5;
|
||||
NET "debug[12]" LOC = B6;
|
||||
NET "debug[13]" LOC = A3;
|
||||
NET "debug[14]" LOC = A7;
|
||||
NET "debug[15]" LOC = A8;
|
||||
NET "debug[16]" LOC = B18;
|
||||
NET "debug[17]" LOC = C17;
|
||||
NET "debug[18]" LOC = H13;
|
||||
NET "debug[19]" LOC = D12;
|
||||
NET "debug[20]" LOC = H14;
|
||||
NET "debug[21]" LOC = C10;
|
||||
NET "debug[22]" LOC = D10;
|
||||
NET "debug[23]" LOC = C8;
|
||||
NET "debug[24]" LOC = D9;
|
||||
NET "debug[25]" LOC = C5;
|
||||
NET "debug[26]" LOC = A9;
|
||||
NET "debug[27]" LOC = B8;
|
||||
NET "debug[28]" LOC = A4;
|
||||
NET "debug[29]" LOC = C7;
|
||||
NET "debug[30]" LOC = C6;
|
||||
NET "debug[31]" LOC = D6;
|
||||
|
||||
NET "debug_clk[0]" LOC = A12;
|
||||
NET "debug_clk[1]" LOC = C12;
|
||||
|
||||
## GPIF
|
||||
|
||||
NET "IFCLK" LOC = H21;
|
||||
NET "FX3_EXTINT" LOC = U20;
|
||||
|
||||
NET "GPIF_CTL0" LOC = V20;
|
||||
NET "GPIF_CTL1" LOC = T22;
|
||||
NET "GPIF_CTL2" LOC = R22;
|
||||
NET "GPIF_CTL3" LOC = U22;
|
||||
NET "GPIF_CTL4" LOC = P19;
|
||||
NET "GPIF_CTL5" LOC = N22;
|
||||
NET "GPIF_CTL6" LOC = T21;
|
||||
NET "GPIF_CTL7" LOC = V21;
|
||||
NET "GPIF_CTL8" LOC = K18;
|
||||
NET "GPIF_CTL9" LOC = R20;
|
||||
##GPIF_CTL10 is "FPGA_CFG_DONE", defined later.
|
||||
NET "GPIF_CTL11" LOC = P22;
|
||||
NET "GPIF_CTL12" LOC = M20;
|
||||
|
||||
NET "GPIF_D[0]" LOC = T17;
|
||||
NET "GPIF_D[1]" LOC = U14;
|
||||
NET "GPIF_D[2]" LOC = U13;
|
||||
NET "GPIF_D[3]" LOC = AA6;
|
||||
NET "GPIF_D[4]" LOC = AB6;
|
||||
NET "GPIF_D[5]" LOC = Y3;
|
||||
NET "GPIF_D[6]" LOC = AB3;
|
||||
NET "GPIF_D[7]" LOC = AA4;
|
||||
NET "GPIF_D[8]" LOC = AA2;
|
||||
NET "GPIF_D[9]" LOC = AB2;
|
||||
NET "GPIF_D[10]" LOC = AB19;
|
||||
NET "GPIF_D[11]" LOC = AA18;
|
||||
NET "GPIF_D[12]" LOC = AB18;
|
||||
NET "GPIF_D[13]" LOC = Y13;
|
||||
NET "GPIF_D[14]" LOC = AA12;
|
||||
NET "GPIF_D[15]" LOC = AB12;
|
||||
NET "GPIF_D[16]" LOC = N20;
|
||||
NET "GPIF_D[17]" LOC = L20;
|
||||
NET "GPIF_D[18]" LOC = N19;
|
||||
NET "GPIF_D[19]" LOC = M22;
|
||||
NET "GPIF_D[20]" LOC = L19;
|
||||
NET "GPIF_D[21]" LOC = M21;
|
||||
NET "GPIF_D[22]" LOC = M19;
|
||||
NET "GPIF_D[23]" LOC = K22;
|
||||
NET "GPIF_D[24]" LOC = J20;
|
||||
NET "GPIF_D[25]" LOC = L22;
|
||||
NET "GPIF_D[26]" LOC = K19;
|
||||
NET "GPIF_D[27]" LOC = H22;
|
||||
NET "GPIF_D[28]" LOC = J22;
|
||||
NET "GPIF_D[29]" LOC = K20;
|
||||
NET "GPIF_D[30]" LOC = G22;
|
||||
NET "GPIF_D[31]" LOC = F22;
|
||||
|
||||
## GPS
|
||||
|
||||
NET "gps_lock" LOC = Y17;
|
||||
NET "gps_out_enable" LOC = V22;
|
||||
NET "gps_ref_enable" LOC = AB13;
|
||||
NET "gps_rxd" LOC = AB14;
|
||||
NET "gps_txd" LOC = W12;
|
||||
NET "gps_txd_nmea" LOC = AA14;
|
||||
|
||||
## LEDS
|
||||
|
||||
NET "LED_RX1" LOC = C22;
|
||||
NET "LED_RX2" LOC = L15;
|
||||
NET "LED_TXRX1_TX" LOC = C20;
|
||||
NET "LED_TXRX2_RX" LOC = D21;
|
||||
NET "LED_TXRX1_RX" LOC = K16;
|
||||
NET "LED_TXRX2_TX" LOC = D22;
|
||||
|
||||
## Misc Hardware Control
|
||||
|
||||
NET "ext_ref_enable" LOC = Y15;
|
||||
NET "pll_lock" LOC = AB10;
|
||||
NET "AUX_PWR_ON" LOC = AA21;
|
||||
#NET "RFUSE" LOC = "P15" ;
|
||||
|
||||
## PPS
|
||||
|
||||
NET "pps_fpga_out_enable" LOC = AB15;
|
||||
NET "PPS_IN_EXT" LOC = AB16;
|
||||
NET "PPS_IN_INT" LOC = AB21;
|
||||
NET "pps_out" LOC = AB17;
|
||||
|
||||
## RF Hardware Control
|
||||
|
||||
NET "SFDX1_RX" LOC = W4;
|
||||
NET "SFDX1_TX" LOC = T18;
|
||||
NET "SFDX2_RX" LOC = F18;
|
||||
NET "SFDX2_TX" LOC = H17;
|
||||
NET "SRX1_RX" LOC = Y7;
|
||||
NET "SRX1_TX" LOC = AA8;
|
||||
NET "SRX2_RX" LOC = J17;
|
||||
NET "SRX2_TX" LOC = F19;
|
||||
NET "tx_bandsel_a" LOC = N16;
|
||||
NET "tx_bandsel_b" LOC = M16;
|
||||
NET "tx_enable1" LOC = Y4;
|
||||
NET "tx_enable2" LOC = R19;
|
||||
NET "rx_bandsel_a" LOC = T20;
|
||||
NET "rx_bandsel_b" LOC = U19;
|
||||
NET "rx_bandsel_c" LOC = P20;
|
||||
|
||||
## FPGA Config Pins
|
||||
|
||||
#NET "FPGA_CFG_INIT_B" LOC = "T6" ;
|
||||
#NET "FPGA_CFG_DONE" LOC = "Y22" ;
|
||||
#NET "FPGA_CFG_M0" LOC = "AA22" ;
|
||||
#NET "FPGA_CFG_M1" LOC = "U15" ;
|
||||
#NET "FPGA_CFG_PROG_B" LOC = "AA1" ;
|
||||
|
||||
## Special Pins
|
||||
|
||||
#NET "VFS" LOC = "P16" ;
|
||||
#NET "TMS" LOC = "C18" ;
|
||||
#NET "TDO" LOC = "A19" ;
|
||||
#NET "TDI" LOC = "E18" ;
|
||||
#NET "TCK" LOC = "G15" ;
|
||||
#NET "GND" LOC = "N15" ;
|
||||
|
||||
####################################################################################
|
||||
# Constraints from file : 'timing.ucf'
|
||||
####################################################################################
|
||||
|
||||
|
||||
# codec_main_clk is 40 MHz main tcxo clock
|
||||
NET "codec_main_clk*" TNM_NET = "codec_main_clk";
|
||||
TIMESPEC TS_codec_main_clk = PERIOD "codec_main_clk" 25000 ps HIGH 50 %;
|
||||
|
||||
|
||||
# IFCLK is 100 MHz GPIF clock
|
||||
NET "IFCLK" TNM_NET = "IFCLK";
|
||||
TIMESPEC TS_IFCLK = PERIOD "IFCLK" 10000 ps HIGH 50 %;
|
||||
|
||||
|
||||
# codec_data_clk is the data clock from catalina, sample rate dependent
|
||||
# this clock equals sample rate in CMOS DDR 1R1T mode
|
||||
# this clock is double the sample rate in CMOS DDR 2R2T mode
|
||||
# Max clock rate is 61.44 MHz
|
||||
NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p";
|
||||
TIMESPEC TS_codec_data_clk_p = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %;
|
||||
|
||||
|
||||
#always use IOB for GPIF pins for awesome timing
|
||||
INST "GPIF_D_9_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_8_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_7_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_6_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_5_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_4_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_3_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_31_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_30_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_2_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_29_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_28_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_27_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_26_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_25_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_24_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_23_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_22_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_21_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_20_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_1_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL0_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL11_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL12_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL1_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL2_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL3_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL4_IBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL5_IBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL7_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL9_IBUF" IOB =TRUE;
|
||||
INST "GPIF_D_0_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_10_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_11_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_12_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_13_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_14_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_15_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_16_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_17_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_18_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_19_IOBUF" IOB =TRUE;
|
||||
|
||||
# TODO not working... constraints ignored
|
||||
|
||||
#constrain FX3 IO
|
||||
INST "GPIF_D[*]" TNM = "gpif_net_out";
|
||||
INST "GPIF_D[*]" TNM = "gpif_net_in";
|
||||
INST "GPIF_CTL0" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL1" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL2" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL3" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL4" TNM = "gpif_net_in";
|
||||
INST "GPIF_CTL5" TNM = "gpif_net_in";
|
||||
INST "GPIF_CTL7" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL11" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL12" TNM = "gpif_net_out";
|
||||
|
||||
#NET "gpif_clk" TNM_NET = "TNM_gpif_clk";
|
||||
#OFFSET = OUT 5 ns AFTER "gpif_clk";
|
||||
#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %;
|
||||
#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING;
|
||||
#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING;
|
||||
Binary file not shown.
@@ -0,0 +1,13 @@
|
||||
#
|
||||
# PlanAhead(TM)
|
||||
# htr.txt: a PlanAhead-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for PlanAhead to track run status.
|
||||
# Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
ngdbuild -intstyle ise -p xc6slx75fgg484-3 -dd _ngo -uc "b200.ucf" "b200.edf"
|
||||
map -intstyle pa -w "b200.ngd"
|
||||
par -intstyle pa "b200.ncd" -w "b200_routed.ncd"
|
||||
trce -intstyle ise -o "b200.twr" -v 30 -l 30 "b200_routed.ncd" "b200.pcf"
|
||||
xdl -secure -ncd2xdl -nopips "b200_routed.ncd" "b200_routed.xdl"
|
||||
@@ -0,0 +1,48 @@
|
||||
//
|
||||
// PlanAhead(TM)
|
||||
// rundef.js: a PlanAhead-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64;/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64;/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin;";
|
||||
} else {
|
||||
PathVal = "/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64;/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64;/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "ngdbuild",
|
||||
"-intstyle ise -p xc6slx75fgg484-3 -dd _ngo -uc \"b200.ucf\" \"b200.edf\"" );
|
||||
ISEStep( "map",
|
||||
"-intstyle pa -w \"b200.ngd\"" );
|
||||
ISEStep( "par",
|
||||
"-intstyle pa \"b200.ncd\" -w \"b200_routed.ncd\"" );
|
||||
ISEStep( "trce",
|
||||
"-intstyle ise -o \"b200.twr\" -v 30 -l 30 \"b200_routed.ncd\" \"b200.pcf\"" );
|
||||
ISEStep( "xdl",
|
||||
"-secure -ncd2xdl -nopips \"b200_routed.ncd\" \"b200_routed.xdl\"" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
@echo off
|
||||
|
||||
rem PlanAhead (TM)
|
||||
rem runme.bat: a PlanAhead-generated Script
|
||||
rem Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
@@ -0,0 +1,4 @@
|
||||
*** PLEASE NOTE: this run was imported on Tue Jan 29 17:25:57 2013
|
||||
from ISE results generated outside of PlanAhead.
|
||||
Original messages and reports have not been imported
|
||||
but you can launch bitgen on this run if desired...
|
||||
+43
@@ -0,0 +1,43 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# PlanAhead(TM)
|
||||
# runme.sh: a PlanAhead-generated Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64:/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin
|
||||
else
|
||||
PATH=/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64:/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64
|
||||
else
|
||||
LD_LIBRARY_PATH=/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD=`dirname "$0"`
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep ngdbuild -intstyle ise -p xc6slx75fgg484-3 -dd _ngo -uc "b200.ucf" "b200.edf"
|
||||
EAStep map -intstyle pa -w "b200.ngd"
|
||||
EAStep par -intstyle pa "b200.ncd" -w "b200_routed.ncd"
|
||||
EAStep trce -intstyle ise -o "b200.twr" -v 30 -l 30 "b200_routed.ncd" "b200.pcf"
|
||||
EAStep xdl -secure -ncd2xdl -nopips "b200_routed.ncd" "b200_routed.xdl"
|
||||
@@ -0,0 +1,241 @@
|
||||
## SPI Nets
|
||||
|
||||
NET "cat_ce" LOC = "Y1" | IOSTANDARD = LVCMOS18;
|
||||
NET "cat_miso" LOC = "V1" | IOSTANDARD = LVCMOS18;
|
||||
NET "cat_mosi" LOC = "T4" | IOSTANDARD = LVCMOS18;
|
||||
NET "cat_sclk" LOC = "P7" | IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "fx3_ce" LOC = "H20" ;
|
||||
NET "fx3_miso" LOC = "G20" ;
|
||||
NET "fx3_mosi" LOC = "AA20" ;
|
||||
NET "fx3_sclk" LOC = "Y21" ;
|
||||
|
||||
NET "pll_ce" LOC = "W11" ;
|
||||
NET "pll_mosi" LOC = "AB11" ;
|
||||
NET "pll_sclk" LOC = "Y12" ;
|
||||
|
||||
NET "FPGA_RXD0" LOC = "AB8" ;
|
||||
NET "FPGA_TXD0" LOC = "AB7" ;
|
||||
|
||||
NET "SCL_FPGA" LOC = "P21" ;
|
||||
NET "SDA_FPGA" LOC = "W22" ;
|
||||
|
||||
## Catalina Controls
|
||||
|
||||
NET "codec_enable" LOC = "J6" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_en_agc" LOC = "P6" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_reset" LOC = "Y2" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_sync" LOC = "M3" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_txrx" LOC = "M7" | IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "codec_ctrl_in<0>" LOC = "E3" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in<1>" LOC = "F2" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in<2>" LOC = "F1" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in<3>" LOC = "E1" | IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "codec_ctrl_out<0>" LOC = "D1" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out<1>" LOC = "C1" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out<2>" LOC = "H3" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out<3>" LOC = "F3" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out<4>" LOC = "P1" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out<5>" LOC = "J1" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out<6>" LOC = "B1" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out<7>" LOC = "H2" | IOSTANDARD = LVCMOS18;
|
||||
|
||||
## Catalina Data RX
|
||||
|
||||
NET "rx_codec_d<0>" LOC = "T2" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<1>" LOC = "R1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<2>" LOC = "V2" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<3>" LOC = "N1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<4>" LOC = "V3" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<5>" LOC = "T1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<6>" LOC = "W1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<7>" LOC = "U1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<8>" LOC = "W3" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<9>" LOC = "U3" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<10>" LOC = "P2" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<11>" LOC = "R3" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
|
||||
## Catalina Data TX
|
||||
|
||||
NET "tx_codec_d<0>" LOC = "M1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<1>" LOC = "K1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<2>" LOC = "L3" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<3>" LOC = "K2" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<4>" LOC = "M4" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<5>" LOC = "J4" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<6>" LOC = "L4" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<7>" LOC = "H1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<8>" LOC = "M2" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<9>" LOC = "G1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<10>" LOC = "N3" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<11>" LOC = "G3" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
|
||||
## Catalina Clocks
|
||||
|
||||
NET "cat_clkout_fpga" LOC = "J3" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_data_clk_p" LOC = "K3" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_fb_clk_p" LOC = "P3" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_main_clk_p" LOC = "K5" ;# | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_main_clk_n" LOC = "K4" ;# | IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "rx_frame_p" LOC = "U4" | IOSTANDARD = LVCMOS18;
|
||||
NET "tx_frame_p" LOC = "T3" | IOSTANDARD = LVCMOS18;
|
||||
|
||||
## Debug Bus
|
||||
|
||||
NET "debug<0>" LOC = "C14" ;
|
||||
NET "debug<1>" LOC = "F15" ;
|
||||
NET "debug<2>" LOC = "A18" ;
|
||||
NET "debug<3>" LOC = "A17" ;
|
||||
NET "debug<4>" LOC = "E14" ;
|
||||
NET "debug<5>" LOC = "G13" ;
|
||||
NET "debug<6>" LOC = "D13" ;
|
||||
NET "debug<7>" LOC = "F13" ;
|
||||
NET "debug<8>" LOC = "D8" ;
|
||||
NET "debug<9>" LOC = "A6" ;
|
||||
NET "debug<10>" LOC = "D7" ;
|
||||
NET "debug<11>" LOC = "A5" ;
|
||||
NET "debug<12>" LOC = "B6" ;
|
||||
NET "debug<13>" LOC = "A3" ;
|
||||
NET "debug<14>" LOC = "A7" ;
|
||||
NET "debug<15>" LOC = "A8" ;
|
||||
NET "debug<16>" LOC = "B18" ;
|
||||
NET "debug<17>" LOC = "C17" ;
|
||||
NET "debug<18>" LOC = "H13" ;
|
||||
NET "debug<19>" LOC = "D12" ;
|
||||
NET "debug<20>" LOC = "H14" ;
|
||||
NET "debug<21>" LOC = "C10" ;
|
||||
NET "debug<22>" LOC = "D10" ;
|
||||
NET "debug<23>" LOC = "C8" ;
|
||||
NET "debug<24>" LOC = "D9" ;
|
||||
NET "debug<25>" LOC = "C5" ;
|
||||
NET "debug<26>" LOC = "A9" ;
|
||||
NET "debug<27>" LOC = "B8" ;
|
||||
NET "debug<28>" LOC = "A4" ;
|
||||
NET "debug<29>" LOC = "C7" ;
|
||||
NET "debug<30>" LOC = "C6" ;
|
||||
NET "debug<31>" LOC = "D6" ;
|
||||
|
||||
NET "debug_clk<0>" LOC = "A12" ;
|
||||
NET "debug_clk<1>" LOC = "C12" ;
|
||||
|
||||
## GPIF
|
||||
|
||||
NET "IFCLK" LOC = "H21" ;
|
||||
NET "FX3_EXTINT" LOC = "U20" ;
|
||||
|
||||
NET "GPIF_CTL0" LOC = "V20" ;
|
||||
NET "GPIF_CTL1" LOC = "T22" ;
|
||||
NET "GPIF_CTL2" LOC = "R22" ;
|
||||
NET "GPIF_CTL3" LOC = "U22" ;
|
||||
NET "GPIF_CTL4" LOC = "P19" ;
|
||||
NET "GPIF_CTL5" LOC = "N22" ;
|
||||
NET "GPIF_CTL6" LOC = "T21" ;
|
||||
NET "GPIF_CTL7" LOC = "V21" ;
|
||||
NET "GPIF_CTL8" LOC = "K18" ;
|
||||
NET "GPIF_CTL9" LOC = "R20" ;
|
||||
##GPIF_CTL10 is "FPGA_CFG_DONE", defined later.
|
||||
NET "GPIF_CTL11" LOC = "P22" ;
|
||||
NET "GPIF_CTL12" LOC = "M20" ;
|
||||
|
||||
NET "GPIF_D<0>" LOC = "T17" ;
|
||||
NET "GPIF_D<1>" LOC = "U14" ;
|
||||
NET "GPIF_D<2>" LOC = "U13" ;
|
||||
NET "GPIF_D<3>" LOC = "AA6" ;
|
||||
NET "GPIF_D<4>" LOC = "AB6" ;
|
||||
NET "GPIF_D<5>" LOC = "Y3" ;
|
||||
NET "GPIF_D<6>" LOC = "AB3" ;
|
||||
NET "GPIF_D<7>" LOC = "AA4" ;
|
||||
NET "GPIF_D<8>" LOC = "AA2" ;
|
||||
NET "GPIF_D<9>" LOC = "AB2" ;
|
||||
NET "GPIF_D<10>" LOC = "AB19" ;
|
||||
NET "GPIF_D<11>" LOC = "AA18" ;
|
||||
NET "GPIF_D<12>" LOC = "AB18" ;
|
||||
NET "GPIF_D<13>" LOC = "Y13" ;
|
||||
NET "GPIF_D<14>" LOC = "AA12" ;
|
||||
NET "GPIF_D<15>" LOC = "AB12" ;
|
||||
NET "GPIF_D<16>" LOC = "N20" ;
|
||||
NET "GPIF_D<17>" LOC = "L20" ;
|
||||
NET "GPIF_D<18>" LOC = "N19" ;
|
||||
NET "GPIF_D<19>" LOC = "M22" ;
|
||||
NET "GPIF_D<20>" LOC = "L19" ;
|
||||
NET "GPIF_D<21>" LOC = "M21" ;
|
||||
NET "GPIF_D<22>" LOC = "M19" ;
|
||||
NET "GPIF_D<23>" LOC = "K22" ;
|
||||
NET "GPIF_D<24>" LOC = "J20" ;
|
||||
NET "GPIF_D<25>" LOC = "L22" ;
|
||||
NET "GPIF_D<26>" LOC = "K19" ;
|
||||
NET "GPIF_D<27>" LOC = "H22" ;
|
||||
NET "GPIF_D<28>" LOC = "J22" ;
|
||||
NET "GPIF_D<29>" LOC = "K20" ;
|
||||
NET "GPIF_D<30>" LOC = "G22" ;
|
||||
NET "GPIF_D<31>" LOC = "F22" ;
|
||||
|
||||
## GPS
|
||||
|
||||
NET "gps_lock" LOC = "Y17" ;
|
||||
NET "gps_out_enable" LOC = "V22" ;
|
||||
NET "gps_ref_enable" LOC = "AB13" ;
|
||||
NET "gps_rxd" LOC = "AB14" ;
|
||||
NET "gps_txd" LOC = "W12" ;
|
||||
NET "gps_txd_nmea" LOC = "AA14" ;
|
||||
|
||||
## LEDS
|
||||
|
||||
NET "LED_RX1" LOC = "C22" ;
|
||||
NET "LED_RX2" LOC = "L15" ;
|
||||
NET "LED_TXRX1_TX" LOC = "C20" ;
|
||||
NET "LED_TXRX2_RX" LOC = "D21" ;
|
||||
NET "LED_TXRX1_RX" LOC = "K16" ;
|
||||
NET "LED_TXRX2_TX" LOC = "D22" ;
|
||||
|
||||
## Misc Hardware Control
|
||||
|
||||
NET "ext_ref_enable" LOC = "Y15" ;
|
||||
NET "pll_lock" LOC = "AB10" ;
|
||||
NET "AUX_PWR_ON" LOC = "AA21" ;
|
||||
#NET "RFUSE" LOC = "P15" ;
|
||||
|
||||
## PPS
|
||||
|
||||
NET "pps_fpga_out_enable" LOC = "AB15" ;
|
||||
NET "PPS_IN_EXT" LOC = "AB16" ;
|
||||
NET "PPS_IN_INT" LOC = "AB21" ;
|
||||
NET "pps_out" LOC = "AB17" ;
|
||||
|
||||
## RF Hardware Control
|
||||
|
||||
NET "SFDX1_RX" LOC = "W4" ;
|
||||
NET "SFDX1_TX" LOC = "T18" ;
|
||||
NET "SFDX2_RX" LOC = "F18" ;
|
||||
NET "SFDX2_TX" LOC = "H17" ;
|
||||
NET "SRX1_RX" LOC = "Y7" ;
|
||||
NET "SRX1_TX" LOC = "AA8" ;
|
||||
NET "SRX2_RX" LOC = "J17" ;
|
||||
NET "SRX2_TX" LOC = "F19" ;
|
||||
NET "tx_bandsel_a" LOC = "N16" ;
|
||||
NET "tx_bandsel_b" LOC = "M16" ;
|
||||
NET "tx_enable1" LOC = "Y4" ;
|
||||
NET "tx_enable2" LOC = "R19" ;
|
||||
NET "rx_bandsel_a" LOC = "T20" ;
|
||||
NET "rx_bandsel_b" LOC = "U19" ;
|
||||
NET "rx_bandsel_c" LOC = "P20" ;
|
||||
|
||||
## FPGA Config Pins
|
||||
|
||||
#NET "FPGA_CFG_INIT_B" LOC = "T6" ;
|
||||
#NET "FPGA_CFG_DONE" LOC = "Y22" ;
|
||||
#NET "FPGA_CFG_M0" LOC = "AA22" ;
|
||||
#NET "FPGA_CFG_M1" LOC = "U15" ;
|
||||
#NET "FPGA_CFG_PROG_B" LOC = "AA1" ;
|
||||
|
||||
## Special Pins
|
||||
|
||||
#NET "VFS" LOC = "P16" ;
|
||||
#NET "TMS" LOC = "C18" ;
|
||||
#NET "TDO" LOC = "A19" ;
|
||||
#NET "TDI" LOC = "E18" ;
|
||||
#NET "TCK" LOC = "G15" ;
|
||||
#NET "GND" LOC = "N15" ;
|
||||
@@ -0,0 +1,44 @@
|
||||
|
||||
# codec_main_clk is 40 MHz main tcxo clock
|
||||
NET "codec_main_clk*" TNM_NET = "codec_main_clk";
|
||||
TIMESPEC "TS_codec_main_clk" = PERIOD "codec_main_clk" 25000 ps HIGH 50 %;
|
||||
|
||||
|
||||
# IFCLK is 100 MHz GPIF clock
|
||||
NET "IFCLK" TNM_NET = "IFCLK";
|
||||
TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 10000 ps HIGH 50 %;
|
||||
|
||||
|
||||
# codec_data_clk is the data clock from catalina, sample rate dependent
|
||||
# this clock equals sample rate in CMOS DDR 1R1T mode
|
||||
# this clock is double the sample rate in CMOS DDR 2R2T mode
|
||||
# Max clock rate is 61.44 MHz
|
||||
NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p";
|
||||
TIMESPEC "TS_codec_data_clk_p" = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %;
|
||||
|
||||
|
||||
#always use IOB for GPIF pins for awesome timing
|
||||
INST "GPIF_*" IOB = TRUE;
|
||||
|
||||
# TODO not working... constraints ignored
|
||||
|
||||
#constrain FX3 IO
|
||||
INST "GPIF_D<*>" TNM = gpif_net_out;
|
||||
INST "GPIF_D<*>" TNM = gpif_net_in;
|
||||
INST "GPIF_CTL0" TNM = gpif_net_out;
|
||||
INST "GPIF_CTL1" TNM = gpif_net_out;
|
||||
INST "GPIF_CTL2" TNM = gpif_net_out;
|
||||
INST "GPIF_CTL3" TNM = gpif_net_out;
|
||||
INST "GPIF_CTL4" TNM = gpif_net_in;
|
||||
INST "GPIF_CTL5" TNM = gpif_net_in;
|
||||
INST "GPIF_CTL6" TNM = gpif_net_in;
|
||||
INST "GPIF_CTL7" TNM = gpif_net_out;
|
||||
INST "GPIF_CTL8" TNM = gpif_net_in;
|
||||
INST "GPIF_CTL11" TNM = gpif_net_out;
|
||||
INST "GPIF_CTL12" TNM = gpif_net_out;
|
||||
|
||||
#NET "gpif_clk" TNM_NET = "TNM_gpif_clk";
|
||||
#OFFSET = OUT 5 ns AFTER "gpif_clk";
|
||||
#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %;
|
||||
#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING;
|
||||
#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING;
|
||||
File diff suppressed because one or more lines are too long
Reference in New Issue
Block a user