Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,5 @@
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/tmp
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/_xmsgs
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/*.log
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/*.gise
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/*.xise
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@@ -0,0 +1,9 @@
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Version 4
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SymbolType BLOCK
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TEXT 32 32 LEFT 4 b200_chipscope_icon
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RECTANGLE Normal 32 32 544 864
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LINE Wide 576 112 544 112
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PIN 576 112 RIGHT 36
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PINATTR PinName control0[35:0]
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PINATTR Polarity BOTH
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@@ -0,0 +1,9 @@
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NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
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TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
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#Update Constraints
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NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
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NET "U0/iSHIFT_OUT" TIG ;
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TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
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TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
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TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
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TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
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@@ -0,0 +1,7 @@
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# icon XDC
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create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
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create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
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set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
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set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
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set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
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set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
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File diff suppressed because one or more lines are too long
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NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
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TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
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#Update Constraints
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NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
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NET "U0/iSHIFT_OUT" TIG ;
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TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
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TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
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TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
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TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
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@@ -0,0 +1,27 @@
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///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2013 Xilinx, Inc.
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// All Rights Reserved
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 14.4
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// \ \ Application: Xilinx CORE Generator
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// / / Filename : b200_chipscope_icon.v
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// /___/ /\ Timestamp : Tue Feb 19 14:28:40 PST 2013
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// \ \ / \
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// \___\/\___\
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//
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// Design Name: Verilog Synthesis Wrapper
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///////////////////////////////////////////////////////////////////////////////
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// This wrapper is used to integrate with Project Navigator and PlanAhead
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`timescale 1ns/1ps
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module b200_chipscope_icon(
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CONTROL0) /* synthesis syn_black_box syn_noprune=1 */;
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inout [35 : 0] CONTROL0;
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endmodule
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@@ -0,0 +1,28 @@
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///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2013 Xilinx, Inc.
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// All Rights Reserved
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 14.4
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// \ \ Application: Xilinx CORE Generator
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// / / Filename : b200_chipscope_icon.veo
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// /___/ /\ Timestamp : Tue Feb 19 14:28:40 PST 2013
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// \ \ / \
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// \___\/\___\
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//
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// Design Name: ISE Instantiation template
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///////////////////////////////////////////////////////////////////////////////
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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b200_chipscope_icon YourInstanceName (
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.CONTROL0(CONTROL0) // INOUT BUS [35:0]
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);
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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@@ -0,0 +1,56 @@
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##############################################################
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#
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# Xilinx Core Generator version 14.4
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# Date: Tue Feb 19 22:27:58 2013
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = Verilog
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SET device = xc6slx75
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SET devicefamily = spartan6
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SET flowvendor = Foundation_ISE
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = fgg484
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -3
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SET verilogsim = true
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SET vhdlsim = false
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# END Project Options
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# BEGIN Select
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SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
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# END Select
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# BEGIN Parameters
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CSET component_name=b200_chipscope_icon
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CSET constraint_type=external
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CSET enable_jtag_bufg=true
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CSET example_design=false
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CSET number_control_ports=1
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CSET use_ext_bscan=false
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CSET use_softbscan=false
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CSET use_unused_bscan=false
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CSET user_scan_chain=USER1
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2012-12-18T02:47:25Z
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# END Extra information
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GENERATE
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# CRC: 729764e8
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# icon XDC
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create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
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create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
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set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
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set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
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set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
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set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
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@@ -0,0 +1,15 @@
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# Output products list for <b200_chipscope_icon>
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b200_chipscope_icon.asy
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b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
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b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
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b200_chipscope_icon.gise
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b200_chipscope_icon.ngc
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b200_chipscope_icon.ucf
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b200_chipscope_icon.v
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b200_chipscope_icon.veo
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b200_chipscope_icon.xco
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b200_chipscope_icon.xdc
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b200_chipscope_icon.xise
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b200_chipscope_icon_flist.txt
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b200_chipscope_icon_readme.txt
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b200_chipscope_icon_xmdf.tcl
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@@ -0,0 +1,45 @@
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The following files were generated for 'b200_chipscope_icon' in directory
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/home/bhilburn/xilinx/
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XCO file generator:
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Generate an XCO file for compatibility with legacy flows.
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* b200_chipscope_icon.xco
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Creates an implementation netlist:
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Creates an implementation netlist for the IP.
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* b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
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* b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
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* b200_chipscope_icon.ngc
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* b200_chipscope_icon.ucf
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* b200_chipscope_icon.v
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* b200_chipscope_icon.veo
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* b200_chipscope_icon.xdc
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* b200_chipscope_icon_xmdf.tcl
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IP Symbol Generator:
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Generate an IP symbol based on the current project options'.
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* b200_chipscope_icon.asy
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Generate ISE subproject:
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Create an ISE subproject for use when including this core in ISE designs
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* b200_chipscope_icon.gise
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* b200_chipscope_icon.xise
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Deliver Readme:
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Readme file for the IP.
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* b200_chipscope_icon_readme.txt
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Generate FLIST file:
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Text file listing all of the output files produced when a customized core was
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generated in the CORE Generator.
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* b200_chipscope_icon_flist.txt
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Please see the Xilinx CORE Generator online help for further details on
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generated files and how to use them.
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+88
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# The package naming convention is <core_name>_xmdf
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package provide b200_chipscope_icon_xmdf 1.0
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# This includes some utilities that support common XMDF operations
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package require utilities_xmdf
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# Define a namespace for this package. The name of the name space
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# is <core_name>_xmdf
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namespace eval ::b200_chipscope_icon_xmdf {
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# Use this to define any statics
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}
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# Function called by client to rebuild the params and port arrays
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# Optional when the use context does not require the param or ports
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# arrays to be available.
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proc ::b200_chipscope_icon_xmdf::xmdfInit { instance } {
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# Variable containing name of library into which module is compiled
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# Recommendation: <module_name>
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# Required
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utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_chipscope_icon
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}
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# ::b200_chipscope_icon_xmdf::xmdfInit
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# Function called by client to fill in all the xmdf* data variables
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# based on the current settings of the parameters
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proc ::b200_chipscope_icon_xmdf::xmdfApplyParams { instance } {
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set fcount 0
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# Array containing libraries that are assumed to exist
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# Examples include unisim and xilinxcorelib
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# Optional
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# In this example, we assume that the unisim library will
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# be available to the simulation and synthesis tool
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utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
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utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
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incr fcount
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utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.asy
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utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
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incr fcount
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utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
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utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
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incr fcount
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utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.ncf
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utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
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incr fcount
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utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
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utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
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incr fcount
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utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.xcf
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utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
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incr fcount
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utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.ngc
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utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
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incr fcount
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utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.v
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utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
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incr fcount
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utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.veo
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utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
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incr fcount
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utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.xco
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utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
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incr fcount
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utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon_xmdf.tcl
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utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
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incr fcount
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utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_chipscope_icon
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incr fcount
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}
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# ::gen_comp_name_xmdf::xmdfApplyParams
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@@ -0,0 +1,21 @@
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Version 4
|
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SymbolType BLOCK
|
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TEXT 32 32 LEFT 4 b200_chipscope_ila
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RECTANGLE Normal 32 32 288 704
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LINE Wide 0 80 32 80
|
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PIN 0 80 LEFT 36
|
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PINATTR PinName control[35:0]
|
||||
PINATTR Polarity IN
|
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LINE Normal 0 112 32 112
|
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PIN 0 112 LEFT 36
|
||||
PINATTR PinName clk
|
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PINATTR Polarity IN
|
||||
LINE Wide 0 144 32 144
|
||||
PIN 0 144 LEFT 36
|
||||
PINATTR PinName data[63:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 176 32 176
|
||||
PIN 0 176 LEFT 36
|
||||
PINATTR PinName trig0[7:0]
|
||||
PINATTR Polarity IN
|
||||
|
||||
@@ -0,0 +1,83 @@
|
||||
#ChipScope Core Generator Project File Version 3.0
|
||||
#Tue Feb 19 16:52:47 PST 2013
|
||||
SignalExport.clockChannel=CLK
|
||||
SignalExport.dataChannel<0000>=DATA[0]
|
||||
SignalExport.dataChannel<0001>=DATA[1]
|
||||
SignalExport.dataChannel<0002>=DATA[2]
|
||||
SignalExport.dataChannel<0003>=DATA[3]
|
||||
SignalExport.dataChannel<0004>=DATA[4]
|
||||
SignalExport.dataChannel<0005>=DATA[5]
|
||||
SignalExport.dataChannel<0006>=DATA[6]
|
||||
SignalExport.dataChannel<0007>=DATA[7]
|
||||
SignalExport.dataChannel<0008>=DATA[8]
|
||||
SignalExport.dataChannel<0009>=DATA[9]
|
||||
SignalExport.dataChannel<0010>=DATA[10]
|
||||
SignalExport.dataChannel<0011>=DATA[11]
|
||||
SignalExport.dataChannel<0012>=DATA[12]
|
||||
SignalExport.dataChannel<0013>=DATA[13]
|
||||
SignalExport.dataChannel<0014>=DATA[14]
|
||||
SignalExport.dataChannel<0015>=DATA[15]
|
||||
SignalExport.dataChannel<0016>=DATA[16]
|
||||
SignalExport.dataChannel<0017>=DATA[17]
|
||||
SignalExport.dataChannel<0018>=DATA[18]
|
||||
SignalExport.dataChannel<0019>=DATA[19]
|
||||
SignalExport.dataChannel<0020>=DATA[20]
|
||||
SignalExport.dataChannel<0021>=DATA[21]
|
||||
SignalExport.dataChannel<0022>=DATA[22]
|
||||
SignalExport.dataChannel<0023>=DATA[23]
|
||||
SignalExport.dataChannel<0024>=DATA[24]
|
||||
SignalExport.dataChannel<0025>=DATA[25]
|
||||
SignalExport.dataChannel<0026>=DATA[26]
|
||||
SignalExport.dataChannel<0027>=DATA[27]
|
||||
SignalExport.dataChannel<0028>=DATA[28]
|
||||
SignalExport.dataChannel<0029>=DATA[29]
|
||||
SignalExport.dataChannel<0030>=DATA[30]
|
||||
SignalExport.dataChannel<0031>=DATA[31]
|
||||
SignalExport.dataChannel<0032>=DATA[32]
|
||||
SignalExport.dataChannel<0033>=DATA[33]
|
||||
SignalExport.dataChannel<0034>=DATA[34]
|
||||
SignalExport.dataChannel<0035>=DATA[35]
|
||||
SignalExport.dataChannel<0036>=DATA[36]
|
||||
SignalExport.dataChannel<0037>=DATA[37]
|
||||
SignalExport.dataChannel<0038>=DATA[38]
|
||||
SignalExport.dataChannel<0039>=DATA[39]
|
||||
SignalExport.dataChannel<0040>=DATA[40]
|
||||
SignalExport.dataChannel<0041>=DATA[41]
|
||||
SignalExport.dataChannel<0042>=DATA[42]
|
||||
SignalExport.dataChannel<0043>=DATA[43]
|
||||
SignalExport.dataChannel<0044>=DATA[44]
|
||||
SignalExport.dataChannel<0045>=DATA[45]
|
||||
SignalExport.dataChannel<0046>=DATA[46]
|
||||
SignalExport.dataChannel<0047>=DATA[47]
|
||||
SignalExport.dataChannel<0048>=DATA[48]
|
||||
SignalExport.dataChannel<0049>=DATA[49]
|
||||
SignalExport.dataChannel<0050>=DATA[50]
|
||||
SignalExport.dataChannel<0051>=DATA[51]
|
||||
SignalExport.dataChannel<0052>=DATA[52]
|
||||
SignalExport.dataChannel<0053>=DATA[53]
|
||||
SignalExport.dataChannel<0054>=DATA[54]
|
||||
SignalExport.dataChannel<0055>=DATA[55]
|
||||
SignalExport.dataChannel<0056>=DATA[56]
|
||||
SignalExport.dataChannel<0057>=DATA[57]
|
||||
SignalExport.dataChannel<0058>=DATA[58]
|
||||
SignalExport.dataChannel<0059>=DATA[59]
|
||||
SignalExport.dataChannel<0060>=DATA[60]
|
||||
SignalExport.dataChannel<0061>=DATA[61]
|
||||
SignalExport.dataChannel<0062>=DATA[62]
|
||||
SignalExport.dataChannel<0063>=DATA[63]
|
||||
SignalExport.dataEqualsTrigger=false
|
||||
SignalExport.dataPortWidth=64
|
||||
SignalExport.triggerChannel<0000><0000>=TRIG0[0]
|
||||
SignalExport.triggerChannel<0000><0001>=TRIG0[1]
|
||||
SignalExport.triggerChannel<0000><0002>=TRIG0[2]
|
||||
SignalExport.triggerChannel<0000><0003>=TRIG0[3]
|
||||
SignalExport.triggerChannel<0000><0004>=TRIG0[4]
|
||||
SignalExport.triggerChannel<0000><0005>=TRIG0[5]
|
||||
SignalExport.triggerChannel<0000><0006>=TRIG0[6]
|
||||
SignalExport.triggerChannel<0000><0007>=TRIG0[7]
|
||||
SignalExport.triggerPort<0000>.name=TRIG0
|
||||
SignalExport.triggerPortCount=1
|
||||
SignalExport.triggerPortIsData<0000>=false
|
||||
SignalExport.triggerPortWidth<0000>=8
|
||||
SignalExport.type=ila
|
||||
|
||||
@@ -0,0 +1,17 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
NET "CLK" TNM_NET = D_CLK ;
|
||||
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
|
||||
TIMESPEC TS_D2_TO_T2_b200_chipscope_ila = FROM D2_CLK TO "FFS" TIG;
|
||||
TIMESPEC TS_J2_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J3_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J4_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
|
||||
#
|
||||
# Input keep/save net constraints
|
||||
#
|
||||
NET "TRIG0<*" S;
|
||||
NET "TRIG0<*" KEEP;
|
||||
NET "DATA<*" S;
|
||||
NET "DATA<*" KEEP;
|
||||
@@ -0,0 +1,6 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
|
||||
set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
|
||||
set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,17 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
NET "CLK" TNM_NET = D_CLK ;
|
||||
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
|
||||
TIMESPEC TS_D2_TO_T2_b200_chipscope_ila = FROM D2_CLK TO "FFS" TIG;
|
||||
TIMESPEC TS_J2_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J3_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J4_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
|
||||
#
|
||||
# Input keep/save net constraints
|
||||
#
|
||||
NET "TRIG0<*" S;
|
||||
NET "TRIG0<*" KEEP;
|
||||
NET "DATA<*" S;
|
||||
NET "DATA<*" KEEP;
|
||||
@@ -0,0 +1,33 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2013 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 14.4
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : b200_chipscope_ila.v
|
||||
// /___/ /\ Timestamp : Tue Feb 19 16:52:47 PST 2013
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
// Design Name: Verilog Synthesis Wrapper
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// This wrapper is used to integrate with Project Navigator and PlanAhead
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module b200_chipscope_ila(
|
||||
CONTROL,
|
||||
CLK,
|
||||
DATA,
|
||||
TRIG0) /* synthesis syn_black_box syn_noprune=1 */;
|
||||
|
||||
|
||||
inout [35 : 0] CONTROL;
|
||||
input CLK;
|
||||
input [63 : 0] DATA;
|
||||
input [7 : 0] TRIG0;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,31 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2013 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 14.4
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : b200_chipscope_ila.veo
|
||||
// /___/ /\ Timestamp : Tue Feb 19 16:52:47 PST 2013
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
// Design Name: ISE Instantiation template
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
b200_chipscope_ila YourInstanceName (
|
||||
.CONTROL(CONTROL), // INOUT BUS [35:0]
|
||||
.CLK(CLK), // IN
|
||||
.DATA(DATA), // IN BUS [63:0]
|
||||
.TRIG0(TRIG0) // IN BUS [7:0]
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
@@ -0,0 +1,141 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Wed Feb 20 00:50:54 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc6slx75
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -3
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET check_bramcount=false
|
||||
CSET component_name=b200_chipscope_ila
|
||||
CSET constraint_type=external
|
||||
CSET counter_width_1=Disabled
|
||||
CSET counter_width_10=Disabled
|
||||
CSET counter_width_11=Disabled
|
||||
CSET counter_width_12=Disabled
|
||||
CSET counter_width_13=Disabled
|
||||
CSET counter_width_14=Disabled
|
||||
CSET counter_width_15=Disabled
|
||||
CSET counter_width_16=Disabled
|
||||
CSET counter_width_2=Disabled
|
||||
CSET counter_width_3=Disabled
|
||||
CSET counter_width_4=Disabled
|
||||
CSET counter_width_5=Disabled
|
||||
CSET counter_width_6=Disabled
|
||||
CSET counter_width_7=Disabled
|
||||
CSET counter_width_8=Disabled
|
||||
CSET counter_width_9=Disabled
|
||||
CSET data_port_width=64
|
||||
CSET data_same_as_trigger=false
|
||||
CSET disable_save_keep=false
|
||||
CSET enable_storage_qualification=true
|
||||
CSET enable_trigger_output_port=false
|
||||
CSET example_design=false
|
||||
CSET exclude_from_data_storage_1=true
|
||||
CSET exclude_from_data_storage_10=true
|
||||
CSET exclude_from_data_storage_11=true
|
||||
CSET exclude_from_data_storage_12=true
|
||||
CSET exclude_from_data_storage_13=true
|
||||
CSET exclude_from_data_storage_14=true
|
||||
CSET exclude_from_data_storage_15=true
|
||||
CSET exclude_from_data_storage_16=true
|
||||
CSET exclude_from_data_storage_2=true
|
||||
CSET exclude_from_data_storage_3=true
|
||||
CSET exclude_from_data_storage_4=true
|
||||
CSET exclude_from_data_storage_5=true
|
||||
CSET exclude_from_data_storage_6=true
|
||||
CSET exclude_from_data_storage_7=true
|
||||
CSET exclude_from_data_storage_8=true
|
||||
CSET exclude_from_data_storage_9=true
|
||||
CSET match_type_1=basic_with_edges
|
||||
CSET match_type_10=basic_with_edges
|
||||
CSET match_type_11=basic_with_edges
|
||||
CSET match_type_12=basic_with_edges
|
||||
CSET match_type_13=basic_with_edges
|
||||
CSET match_type_14=basic_with_edges
|
||||
CSET match_type_15=basic_with_edges
|
||||
CSET match_type_16=basic_with_edges
|
||||
CSET match_type_2=basic_with_edges
|
||||
CSET match_type_3=basic_with_edges
|
||||
CSET match_type_4=basic_with_edges
|
||||
CSET match_type_5=basic_with_edges
|
||||
CSET match_type_6=basic_with_edges
|
||||
CSET match_type_7=basic_with_edges
|
||||
CSET match_type_8=basic_with_edges
|
||||
CSET match_type_9=basic_with_edges
|
||||
CSET match_units_1=1
|
||||
CSET match_units_10=1
|
||||
CSET match_units_11=1
|
||||
CSET match_units_12=1
|
||||
CSET match_units_13=1
|
||||
CSET match_units_14=1
|
||||
CSET match_units_15=1
|
||||
CSET match_units_16=1
|
||||
CSET match_units_2=1
|
||||
CSET match_units_3=1
|
||||
CSET match_units_4=1
|
||||
CSET match_units_5=1
|
||||
CSET match_units_6=1
|
||||
CSET match_units_7=1
|
||||
CSET match_units_8=1
|
||||
CSET match_units_9=1
|
||||
CSET max_sequence_levels=1
|
||||
CSET number_of_trigger_ports=1
|
||||
CSET sample_data_depth=8192
|
||||
CSET sample_on=Rising
|
||||
CSET trigger_port_width_1=8
|
||||
CSET trigger_port_width_10=8
|
||||
CSET trigger_port_width_11=8
|
||||
CSET trigger_port_width_12=8
|
||||
CSET trigger_port_width_13=8
|
||||
CSET trigger_port_width_14=8
|
||||
CSET trigger_port_width_15=8
|
||||
CSET trigger_port_width_16=8
|
||||
CSET trigger_port_width_2=8
|
||||
CSET trigger_port_width_3=8
|
||||
CSET trigger_port_width_4=8
|
||||
CSET trigger_port_width_5=8
|
||||
CSET trigger_port_width_6=8
|
||||
CSET trigger_port_width_7=8
|
||||
CSET trigger_port_width_8=8
|
||||
CSET trigger_port_width_9=8
|
||||
CSET use_rpms=false
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-12-18T02:47:40Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 92d75d38
|
||||
@@ -0,0 +1,6 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
|
||||
set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
|
||||
set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
|
||||
@@ -0,0 +1,18 @@
|
||||
# Output products list for <b200_chipscope_ila>
|
||||
_xmsgs/pn_parser.xmsgs
|
||||
b200_chipscope_ila.asy
|
||||
b200_chipscope_ila.cdc
|
||||
b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
|
||||
b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
|
||||
b200_chipscope_ila.gise
|
||||
b200_chipscope_ila.ncf
|
||||
b200_chipscope_ila.ngc
|
||||
b200_chipscope_ila.ucf
|
||||
b200_chipscope_ila.v
|
||||
b200_chipscope_ila.veo
|
||||
b200_chipscope_ila.xco
|
||||
b200_chipscope_ila.xdc
|
||||
b200_chipscope_ila.xise
|
||||
b200_chipscope_ila_flist.txt
|
||||
b200_chipscope_ila_readme.txt
|
||||
b200_chipscope_ila_xmdf.tcl
|
||||
@@ -0,0 +1,48 @@
|
||||
The following files were generated for 'b200_chipscope_ila' in directory
|
||||
/home/bhilburn/code/ettus/b200_dev/fpgapriv.git/usrp3/top/b200/coregen/
|
||||
|
||||
XCO file generator:
|
||||
Generate an XCO file for compatibility with legacy flows.
|
||||
|
||||
* b200_chipscope_ila.xco
|
||||
|
||||
Creates an implementation netlist:
|
||||
Creates an implementation netlist for the IP.
|
||||
|
||||
* b200_chipscope_ila.cdc
|
||||
* b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
|
||||
* b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
|
||||
* b200_chipscope_ila.ncf
|
||||
* b200_chipscope_ila.ngc
|
||||
* b200_chipscope_ila.ucf
|
||||
* b200_chipscope_ila.v
|
||||
* b200_chipscope_ila.veo
|
||||
* b200_chipscope_ila.xdc
|
||||
* b200_chipscope_ila_xmdf.tcl
|
||||
|
||||
IP Symbol Generator:
|
||||
Generate an IP symbol based on the current project options'.
|
||||
|
||||
* b200_chipscope_ila.asy
|
||||
|
||||
Generate ISE subproject:
|
||||
Create an ISE subproject for use when including this core in ISE designs
|
||||
|
||||
* _xmsgs/pn_parser.xmsgs
|
||||
* b200_chipscope_ila.gise
|
||||
* b200_chipscope_ila.xise
|
||||
|
||||
Deliver Readme:
|
||||
Readme file for the IP.
|
||||
|
||||
* b200_chipscope_ila_readme.txt
|
||||
|
||||
Generate FLIST file:
|
||||
Text file listing all of the output files produced when a customized core was
|
||||
generated in the CORE Generator.
|
||||
|
||||
* b200_chipscope_ila_flist.txt
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
Executable
+87
@@ -0,0 +1,87 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide b200_chipscope_ila_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::b200_chipscope_ila_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::b200_chipscope_ila_xmdf::xmdfInit { instance } {
|
||||
# Variable containing name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_chipscope_ila
|
||||
}
|
||||
# ::b200_chipscope_ila_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::b200_chipscope_ila_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.cdc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
|
||||
incr fcount
|
||||
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.ncf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_chipscope_ila
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 b200_clk_gen
|
||||
RECTANGLE Normal 32 32 576 1088
|
||||
LINE Normal 0 112 32 112
|
||||
PIN 0 112 LEFT 36
|
||||
PINATTR PinName clk_in1_p
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 144 32 144
|
||||
PIN 0 144 LEFT 36
|
||||
PINATTR PinName clk_in1_n
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 432 32 432
|
||||
PIN 0 432 LEFT 36
|
||||
PINATTR PinName reset
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 608 80 576 80
|
||||
PIN 608 80 RIGHT 36
|
||||
PINATTR PinName clk_out1
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 608 176 576 176
|
||||
PIN 608 176 RIGHT 36
|
||||
PINATTR PinName clk_out2
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 608 272 576 272
|
||||
PIN 608 272 RIGHT 36
|
||||
PINATTR PinName clk_out3
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 608 976 576 976
|
||||
PIN 608 976 RIGHT 36
|
||||
PINATTR PinName locked
|
||||
PINATTR Polarity OUT
|
||||
|
||||
Executable
+72
@@ -0,0 +1,72 @@
|
||||
# file: b200_clk_gen.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
# Differential clock only needs one constraint
|
||||
NET "CLK_IN1_P" TNM_NET = "CLK_IN1_P";
|
||||
TIMESPEC "TS_CLK_IN1_P" = PERIOD "CLK_IN1_P" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps;
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
# automatically propogated by the tools
|
||||
# However, if you'd like to use them for module level testing, you
|
||||
# can copy them into your module level timing checks
|
||||
#-----------------------------------------------------------------
|
||||
# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
|
||||
# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 40.000 MHz;
|
||||
|
||||
# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
|
||||
# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz;
|
||||
# NET "clk_int[3]" TNM_NET = "CLK_OUT3";
|
||||
# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz;
|
||||
|
||||
# FALSE PATH constraints
|
||||
PIN "RESET" TIG;
|
||||
|
||||
Executable
+163
@@ -0,0 +1,163 @@
|
||||
// file: b200_clk_gen.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1____40.000______0.000______50.0______200.000____150.000
|
||||
// CLK_OUT2___100.000______0.000______50.0______400.000____150.000
|
||||
// CLK_OUT3___100.000______0.000______50.0______400.000____150.000
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary__________40.000____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "b200_clk_gen,clk_wiz_v3_6,{component_name=b200_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
|
||||
module b200_clk_gen
|
||||
(// Clock in ports
|
||||
input CLK_IN1_40_P,
|
||||
input CLK_IN1_40_N,
|
||||
// Clock out ports
|
||||
output CLK_OUT1_40_int,
|
||||
output CLK_OUT2_100_gpif,
|
||||
output CLK_OUT3_100_bus,
|
||||
// Status and control signals
|
||||
input RESET,
|
||||
output LOCKED
|
||||
);
|
||||
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
IBUFGDS clkin1_buf
|
||||
(.O (clkin1),
|
||||
.I (CLK_IN1_40_P),
|
||||
.IB (CLK_IN1_40_N));
|
||||
|
||||
|
||||
// Clocking primitive
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the DCM primitive
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire [7:0] status_int;
|
||||
wire clkfb;
|
||||
wire clk0;
|
||||
wire clkfx;
|
||||
|
||||
DCM_SP
|
||||
#(.CLKDV_DIVIDE (2.000),
|
||||
.CLKFX_DIVIDE (2),
|
||||
.CLKFX_MULTIPLY (5),
|
||||
.CLKIN_DIVIDE_BY_2 ("FALSE"),
|
||||
.CLKIN_PERIOD (25.0),
|
||||
.CLKOUT_PHASE_SHIFT ("NONE"),
|
||||
.CLK_FEEDBACK ("1X"),
|
||||
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
|
||||
.PHASE_SHIFT (0),
|
||||
.STARTUP_WAIT ("FALSE"))
|
||||
dcm_sp_inst
|
||||
// Input clock
|
||||
(.CLKIN (clkin1),
|
||||
.CLKFB (clkfb),
|
||||
// Output clocks
|
||||
.CLK0 (clk0),
|
||||
.CLK90 (),
|
||||
.CLK180 (),
|
||||
.CLK270 (),
|
||||
.CLK2X (),
|
||||
.CLK2X180 (),
|
||||
.CLKFX (clkfx),
|
||||
.CLKFX180 (),
|
||||
.CLKDV (),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.STATUS (status_int),
|
||||
|
||||
.RST (RESET),
|
||||
// Unused pin- tie low
|
||||
.DSSEN (1'b0));
|
||||
|
||||
assign LOCKED = locked_int;
|
||||
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
assign clkfb = CLK_OUT1_40_int;
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (CLK_OUT1_40_int),
|
||||
.I (clk0));
|
||||
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (CLK_OUT2_100_gpif),
|
||||
.I (clkfx));
|
||||
|
||||
BUFG clkout3_buf
|
||||
(.O (CLK_OUT3_100_bus),
|
||||
.I (clkfx));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
Executable
+83
@@ -0,0 +1,83 @@
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1____40.000______0.000______50.0______200.000____150.000
|
||||
// CLK_OUT2___100.000______0.000______50.0______400.000____150.000
|
||||
// CLK_OUT3___100.000______0.000______50.0______400.000____150.000
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary__________40.000____________0.010
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
b200_clk_gen instance_name
|
||||
(// Clock in ports
|
||||
.CLK_IN1_40_P(CLK_IN1_40_P), // IN
|
||||
.CLK_IN1_40_N(CLK_IN1_40_N), // IN
|
||||
// Clock out ports
|
||||
.CLK_OUT1_40_int(CLK_OUT1_40_int), // OUT
|
||||
.CLK_OUT2_100_gpif(CLK_OUT2_100_gpif), // OUT
|
||||
.CLK_OUT3_100_bus(CLK_OUT3_100_bus), // OUT
|
||||
// Status and control signals
|
||||
.RESET(RESET),// IN
|
||||
.LOCKED(LOCKED)); // OUT
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
@@ -0,0 +1,269 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Fri Jan 25 20:00:48 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:clk_wiz:3.6
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc6slx75
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = csg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET calc_done=DONE
|
||||
CSET clk_in_sel_port=CLK_IN_SEL
|
||||
CSET clk_out1_port=CLK_OUT1_40_int
|
||||
CSET clk_out1_use_fine_ps_gui=false
|
||||
CSET clk_out2_port=CLK_OUT2_100_gpif
|
||||
CSET clk_out2_use_fine_ps_gui=false
|
||||
CSET clk_out3_port=CLK_OUT3_100_bus
|
||||
CSET clk_out3_use_fine_ps_gui=false
|
||||
CSET clk_out4_port=CLK_OUT4
|
||||
CSET clk_out4_use_fine_ps_gui=false
|
||||
CSET clk_out5_port=CLK_OUT5
|
||||
CSET clk_out5_use_fine_ps_gui=false
|
||||
CSET clk_out6_port=CLK_OUT6
|
||||
CSET clk_out6_use_fine_ps_gui=false
|
||||
CSET clk_out7_port=CLK_OUT7
|
||||
CSET clk_out7_use_fine_ps_gui=false
|
||||
CSET clk_valid_port=CLK_VALID
|
||||
CSET clkfb_in_n_port=CLKFB_IN_N
|
||||
CSET clkfb_in_p_port=CLKFB_IN_P
|
||||
CSET clkfb_in_port=CLKFB_IN
|
||||
CSET clkfb_in_signaling=SINGLE
|
||||
CSET clkfb_out_n_port=CLKFB_OUT_N
|
||||
CSET clkfb_out_p_port=CLKFB_OUT_P
|
||||
CSET clkfb_out_port=CLKFB_OUT
|
||||
CSET clkfb_stopped_port=CLKFB_STOPPED
|
||||
CSET clkin1_jitter_ps=250.0
|
||||
CSET clkin1_ui_jitter=0.010
|
||||
CSET clkin2_jitter_ps=100.0
|
||||
CSET clkin2_ui_jitter=0.010
|
||||
CSET clkout1_drives=BUFG
|
||||
CSET clkout1_requested_duty_cycle=50.000
|
||||
CSET clkout1_requested_out_freq=40.000
|
||||
CSET clkout1_requested_phase=0.000
|
||||
CSET clkout2_drives=BUFG
|
||||
CSET clkout2_requested_duty_cycle=50.000
|
||||
CSET clkout2_requested_out_freq=100.000
|
||||
CSET clkout2_requested_phase=0.000
|
||||
CSET clkout2_used=true
|
||||
CSET clkout3_drives=BUFG
|
||||
CSET clkout3_requested_duty_cycle=50.000
|
||||
CSET clkout3_requested_out_freq=100.000
|
||||
CSET clkout3_requested_phase=0.000
|
||||
CSET clkout3_used=true
|
||||
CSET clkout4_drives=BUFG
|
||||
CSET clkout4_requested_duty_cycle=50.000
|
||||
CSET clkout4_requested_out_freq=100.000
|
||||
CSET clkout4_requested_phase=0.000
|
||||
CSET clkout4_used=false
|
||||
CSET clkout5_drives=BUFG
|
||||
CSET clkout5_requested_duty_cycle=50.000
|
||||
CSET clkout5_requested_out_freq=100.000
|
||||
CSET clkout5_requested_phase=0.000
|
||||
CSET clkout5_used=false
|
||||
CSET clkout6_drives=BUFG
|
||||
CSET clkout6_requested_duty_cycle=50.000
|
||||
CSET clkout6_requested_out_freq=100.000
|
||||
CSET clkout6_requested_phase=0.000
|
||||
CSET clkout6_used=false
|
||||
CSET clkout7_drives=BUFG
|
||||
CSET clkout7_requested_duty_cycle=50.000
|
||||
CSET clkout7_requested_out_freq=100.000
|
||||
CSET clkout7_requested_phase=0.000
|
||||
CSET clkout7_used=false
|
||||
CSET clock_mgr_type=AUTO
|
||||
CSET component_name=b200_clk_gen
|
||||
CSET daddr_port=DADDR
|
||||
CSET dclk_port=DCLK
|
||||
CSET dcm_clk_feedback=1X
|
||||
CSET dcm_clk_out1_port=CLK0
|
||||
CSET dcm_clk_out2_port=CLKFX
|
||||
CSET dcm_clk_out3_port=CLKFX
|
||||
CSET dcm_clk_out4_port=CLK0
|
||||
CSET dcm_clk_out5_port=CLK0
|
||||
CSET dcm_clk_out6_port=CLK0
|
||||
CSET dcm_clkdv_divide=2.0
|
||||
CSET dcm_clkfx_divide=2
|
||||
CSET dcm_clkfx_multiply=5
|
||||
CSET dcm_clkgen_clk_out1_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out2_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out3_port=CLKFX
|
||||
CSET dcm_clkgen_clkfx_divide=1
|
||||
CSET dcm_clkgen_clkfx_md_max=0.000
|
||||
CSET dcm_clkgen_clkfx_multiply=4
|
||||
CSET dcm_clkgen_clkfxdv_divide=2
|
||||
CSET dcm_clkgen_clkin_period=10.000
|
||||
CSET dcm_clkgen_notes=None
|
||||
CSET dcm_clkgen_spread_spectrum=NONE
|
||||
CSET dcm_clkgen_startup_wait=false
|
||||
CSET dcm_clkin_divide_by_2=false
|
||||
CSET dcm_clkin_period=25.000
|
||||
CSET dcm_clkout_phase_shift=NONE
|
||||
CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
|
||||
CSET dcm_notes=None
|
||||
CSET dcm_phase_shift=0
|
||||
CSET dcm_pll_cascade=NONE
|
||||
CSET dcm_startup_wait=false
|
||||
CSET den_port=DEN
|
||||
CSET din_port=DIN
|
||||
CSET dout_port=DOUT
|
||||
CSET drdy_port=DRDY
|
||||
CSET dwe_port=DWE
|
||||
CSET feedback_source=FDBK_AUTO
|
||||
CSET in_freq_units=Units_MHz
|
||||
CSET in_jitter_units=Units_UI
|
||||
CSET input_clk_stopped_port=INPUT_CLK_STOPPED
|
||||
CSET jitter_options=UI
|
||||
CSET jitter_sel=No_Jitter
|
||||
CSET locked_port=LOCKED
|
||||
CSET mmcm_bandwidth=OPTIMIZED
|
||||
CSET mmcm_clkfbout_mult_f=4.000
|
||||
CSET mmcm_clkfbout_phase=0.000
|
||||
CSET mmcm_clkfbout_use_fine_ps=false
|
||||
CSET mmcm_clkin1_period=10.000
|
||||
CSET mmcm_clkin2_period=10.000
|
||||
CSET mmcm_clkout0_divide_f=4.000
|
||||
CSET mmcm_clkout0_duty_cycle=0.500
|
||||
CSET mmcm_clkout0_phase=0.000
|
||||
CSET mmcm_clkout0_use_fine_ps=false
|
||||
CSET mmcm_clkout1_divide=1
|
||||
CSET mmcm_clkout1_duty_cycle=0.500
|
||||
CSET mmcm_clkout1_phase=0.000
|
||||
CSET mmcm_clkout1_use_fine_ps=false
|
||||
CSET mmcm_clkout2_divide=1
|
||||
CSET mmcm_clkout2_duty_cycle=0.500
|
||||
CSET mmcm_clkout2_phase=0.000
|
||||
CSET mmcm_clkout2_use_fine_ps=false
|
||||
CSET mmcm_clkout3_divide=1
|
||||
CSET mmcm_clkout3_duty_cycle=0.500
|
||||
CSET mmcm_clkout3_phase=0.000
|
||||
CSET mmcm_clkout3_use_fine_ps=false
|
||||
CSET mmcm_clkout4_cascade=false
|
||||
CSET mmcm_clkout4_divide=1
|
||||
CSET mmcm_clkout4_duty_cycle=0.500
|
||||
CSET mmcm_clkout4_phase=0.000
|
||||
CSET mmcm_clkout4_use_fine_ps=false
|
||||
CSET mmcm_clkout5_divide=1
|
||||
CSET mmcm_clkout5_duty_cycle=0.500
|
||||
CSET mmcm_clkout5_phase=0.000
|
||||
CSET mmcm_clkout5_use_fine_ps=false
|
||||
CSET mmcm_clkout6_divide=1
|
||||
CSET mmcm_clkout6_duty_cycle=0.500
|
||||
CSET mmcm_clkout6_phase=0.000
|
||||
CSET mmcm_clkout6_use_fine_ps=false
|
||||
CSET mmcm_clock_hold=false
|
||||
CSET mmcm_compensation=ZHOLD
|
||||
CSET mmcm_divclk_divide=1
|
||||
CSET mmcm_notes=None
|
||||
CSET mmcm_ref_jitter1=0.010
|
||||
CSET mmcm_ref_jitter2=0.010
|
||||
CSET mmcm_startup_wait=false
|
||||
CSET num_out_clks=3
|
||||
CSET override_dcm=false
|
||||
CSET override_dcm_clkgen=false
|
||||
CSET override_mmcm=false
|
||||
CSET override_pll=false
|
||||
CSET platform=lin64
|
||||
CSET pll_bandwidth=OPTIMIZED
|
||||
CSET pll_clk_feedback=CLKFBOUT
|
||||
CSET pll_clkfbout_mult=4
|
||||
CSET pll_clkfbout_phase=0.000
|
||||
CSET pll_clkin_period=10.000
|
||||
CSET pll_clkout0_divide=1
|
||||
CSET pll_clkout0_duty_cycle=0.500
|
||||
CSET pll_clkout0_phase=0.000
|
||||
CSET pll_clkout1_divide=1
|
||||
CSET pll_clkout1_duty_cycle=0.500
|
||||
CSET pll_clkout1_phase=0.000
|
||||
CSET pll_clkout2_divide=1
|
||||
CSET pll_clkout2_duty_cycle=0.500
|
||||
CSET pll_clkout2_phase=0.000
|
||||
CSET pll_clkout3_divide=1
|
||||
CSET pll_clkout3_duty_cycle=0.500
|
||||
CSET pll_clkout3_phase=0.000
|
||||
CSET pll_clkout4_divide=1
|
||||
CSET pll_clkout4_duty_cycle=0.500
|
||||
CSET pll_clkout4_phase=0.000
|
||||
CSET pll_clkout5_divide=1
|
||||
CSET pll_clkout5_duty_cycle=0.500
|
||||
CSET pll_clkout5_phase=0.000
|
||||
CSET pll_compensation=SYSTEM_SYNCHRONOUS
|
||||
CSET pll_divclk_divide=1
|
||||
CSET pll_notes=None
|
||||
CSET pll_ref_jitter=0.010
|
||||
CSET power_down_port=POWER_DOWN
|
||||
CSET prim_in_freq=40.000
|
||||
CSET prim_in_jitter=0.010
|
||||
CSET prim_source=Differential_clock_capable_pin
|
||||
CSET primary_port=CLK_IN1_40
|
||||
CSET primitive=MMCM
|
||||
CSET primtype_sel=PLL_BASE
|
||||
CSET psclk_port=PSCLK
|
||||
CSET psdone_port=PSDONE
|
||||
CSET psen_port=PSEN
|
||||
CSET psincdec_port=PSINCDEC
|
||||
CSET relative_inclk=REL_PRIMARY
|
||||
CSET reset_port=RESET
|
||||
CSET secondary_in_freq=100.000
|
||||
CSET secondary_in_jitter=0.010
|
||||
CSET secondary_port=CLK_IN2
|
||||
CSET secondary_source=Single_ended_clock_capable_pin
|
||||
CSET ss_mod_freq=250
|
||||
CSET ss_mode=CENTER_HIGH
|
||||
CSET status_port=STATUS
|
||||
CSET summary_strings=empty
|
||||
CSET use_clk_valid=false
|
||||
CSET use_clkfb_stopped=false
|
||||
CSET use_dyn_phase_shift=false
|
||||
CSET use_dyn_reconfig=false
|
||||
CSET use_freeze=false
|
||||
CSET use_freq_synth=true
|
||||
CSET use_inclk_stopped=false
|
||||
CSET use_inclk_switchover=false
|
||||
CSET use_locked=true
|
||||
CSET use_max_i_jitter=false
|
||||
CSET use_min_o_jitter=false
|
||||
CSET use_min_power=false
|
||||
CSET use_phase_alignment=true
|
||||
CSET use_power_down=false
|
||||
CSET use_reset=true
|
||||
CSET use_spread_spectrum=false
|
||||
CSET use_spread_spectrum_1=false
|
||||
CSET use_status=false
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-05-10T12:44:55Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: af7323ea
|
||||
Executable
+68
@@ -0,0 +1,68 @@
|
||||
# file: b200_clk_gen.xdc
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
# Differential clock only needs one constraint
|
||||
create_clock -name CLK_IN1_P -period 25.0 [get_ports CLK_IN1_P]
|
||||
set_propagated_clock CLK_IN1_P
|
||||
set_input_jitter CLK_IN1_P 0.25
|
||||
|
||||
set_false_path -from [get_ports "RESET"]
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
# automatically propogated by the tools
|
||||
# However, if you'd like to use them for module level testing, you
|
||||
# can copy them into your module level timing checks
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
@@ -0,0 +1,181 @@
|
||||
CHANGE LOG for LogiCORE Clocking Wizard V3.6
|
||||
|
||||
Release Date: July 25, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
|
||||
|
||||
................................................................................
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
|
||||
|
||||
Zynq-7000 devices
|
||||
Zynq-7000
|
||||
Defense Grade Zynq-7000Q (XQ)
|
||||
|
||||
|
||||
All Virtex-6 devices
|
||||
|
||||
|
||||
All Spartan-6 devices
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- Spread Spectrum support for 7 series MMCME2
|
||||
|
||||
- ISE 14.2 software support
|
||||
|
||||
................................................................................
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
Resolved issue with Virtex6 MMCM instantiation for VHDL project
|
||||
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
|
||||
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
|
||||
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
|
||||
01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
|
||||
06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
|
||||
03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
|
||||
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
|
||||
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
|
||||
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
|
||||
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
|
||||
04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
@@ -0,0 +1,181 @@
|
||||
CHANGE LOG for LogiCORE Clocking Wizard V3.6
|
||||
|
||||
Release Date: July 25, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
|
||||
|
||||
................................................................................
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
|
||||
|
||||
Zynq-7000 devices
|
||||
Zynq-7000
|
||||
Defense Grade Zynq-7000Q (XQ)
|
||||
|
||||
|
||||
All Virtex-6 devices
|
||||
|
||||
|
||||
All Spartan-6 devices
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- Spread Spectrum support for 7 series MMCME2
|
||||
|
||||
- ISE 14.2 software support
|
||||
|
||||
................................................................................
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
Resolved issue with Virtex6 MMCM instantiation for VHDL project
|
||||
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
|
||||
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
|
||||
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
|
||||
01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
|
||||
06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
|
||||
03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
|
||||
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
|
||||
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
|
||||
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
|
||||
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
|
||||
04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
@@ -0,0 +1,192 @@
|
||||
<HTML>
|
||||
<HEAD>
|
||||
<TITLE>clk_wiz_v3_6_vinfo</TITLE>
|
||||
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
|
||||
</HEAD>
|
||||
<BODY>
|
||||
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
|
||||
CHANGE LOG for LogiCORE Clocking Wizard V3.6
|
||||
|
||||
Release Date: July 25, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
|
||||
|
||||
For system requirements:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
<A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
|
||||
|
||||
Zynq-7000 devices
|
||||
Zynq-7000
|
||||
Defense Grade Zynq-7000Q (XQ)
|
||||
|
||||
|
||||
All Virtex-6 devices
|
||||
|
||||
|
||||
All Spartan-6 devices
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- Spread Spectrum support for 7 series MMCME2
|
||||
|
||||
- ISE 14.2 software support
|
||||
|
||||
................................................................................
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
Resolved issue with Virtex6 MMCM instantiation for VHDL project
|
||||
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes Guide
|
||||
located at
|
||||
|
||||
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
|
||||
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
|
||||
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
|
||||
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
|
||||
01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
|
||||
06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
|
||||
03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
|
||||
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
|
||||
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
|
||||
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
|
||||
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
|
||||
04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
</FONT>
|
||||
</PRE>
|
||||
</BODY>
|
||||
</HTML>
|
||||
Binary file not shown.
@@ -0,0 +1,73 @@
|
||||
# file: b200_clk_gen_exdes.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
# Differential clock only needs one constraint
|
||||
NET "CLK_IN1_P" TNM_NET = "CLK_IN1_P";
|
||||
TIMESPEC "TS_CLK_IN1_P" = PERIOD "CLK_IN1_P" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps;
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
# automatically propogated by the tools
|
||||
# However, if you'd like to use them for module level testing, you
|
||||
# can copy them into your module level timing checks
|
||||
#-----------------------------------------------------------------
|
||||
# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
|
||||
# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 40.000 MHz;
|
||||
|
||||
# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
|
||||
# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz;
|
||||
# NET "clk_int[3]" TNM_NET = "CLK_OUT3";
|
||||
# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz;
|
||||
|
||||
# FALSE PATH constraints
|
||||
PIN "COUNTER_RESET" TIG;
|
||||
PIN "RESET" TIG;
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
// file: b200_clk_gen_exdes.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Clocking wizard example design
|
||||
//----------------------------------------------------------------------------
|
||||
// This example design instantiates the created clocking network, where each
|
||||
// output clock drives a counter. The high bit of each counter is ported.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module b200_clk_gen_exdes
|
||||
#(
|
||||
parameter TCQ = 100
|
||||
)
|
||||
(// Clock in ports
|
||||
input CLK_IN1_P,
|
||||
input CLK_IN1_N,
|
||||
// Reset that only drives logic in example design
|
||||
input COUNTER_RESET,
|
||||
output [3:1] CLK_OUT,
|
||||
// High bits of counters driven by clocks
|
||||
output [3:1] COUNT,
|
||||
// Status and control signals
|
||||
input RESET,
|
||||
output LOCKED
|
||||
);
|
||||
|
||||
// Parameters for the counters
|
||||
//-------------------------------
|
||||
// Counter width
|
||||
localparam C_W = 16;
|
||||
// Number of counters
|
||||
localparam NUM_C = 3;
|
||||
genvar count_gen;
|
||||
// When the clock goes out of lock, reset the counters
|
||||
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
|
||||
|
||||
reg [NUM_C:1] rst_sync;
|
||||
reg [NUM_C:1] rst_sync_int;
|
||||
reg [NUM_C:1] rst_sync_int1;
|
||||
reg [NUM_C:1] rst_sync_int2;
|
||||
|
||||
|
||||
// Declare the clocks and counters
|
||||
wire [NUM_C:1] clk_int;
|
||||
wire [NUM_C:1] clk_n;
|
||||
wire [NUM_C:1] clk;
|
||||
reg [C_W-1:0] counter [NUM_C:1];
|
||||
|
||||
// Instantiation of the clocking network
|
||||
//--------------------------------------
|
||||
b200_clk_gen clknetwork
|
||||
(// Clock in ports
|
||||
.CLK_IN1_40_P (CLK_IN1_P),
|
||||
.CLK_IN1_40_N (CLK_IN1_N),
|
||||
// Clock out ports
|
||||
.CLK_OUT1_40_int (clk_int[1]),
|
||||
.CLK_OUT2_100_gpif (clk_int[2]),
|
||||
.CLK_OUT3_100_bus (clk_int[3]),
|
||||
// Status and control signals
|
||||
.RESET (RESET),
|
||||
.LOCKED (LOCKED));
|
||||
|
||||
genvar clk_out_pins;
|
||||
|
||||
generate
|
||||
for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1)
|
||||
begin: gen_outclk_oddr
|
||||
assign clk_n[clk_out_pins] = ~clk[clk_out_pins];
|
||||
|
||||
ODDR2 clkout_oddr
|
||||
(.Q (CLK_OUT[clk_out_pins1]),
|
||||
.C0 (clk[clk_out_pins]),
|
||||
.C1 (clk_n[clk_out_pins]),
|
||||
.CE (1'b1),
|
||||
.D0 (1'b1),
|
||||
.D1 (1'b0),
|
||||
.R (1'b0),
|
||||
.S (1'b0));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Connect the output clocks to the design
|
||||
//-----------------------------------------
|
||||
assign clk[1] = clk_int[1];
|
||||
assign clk[2] = clk_int[2];
|
||||
assign clk[3] = clk_int[3];
|
||||
|
||||
|
||||
// Reset synchronizer
|
||||
//-----------------------------------
|
||||
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
|
||||
always @(posedge reset_int or posedge clk[count_gen]) begin
|
||||
if (reset_int) begin
|
||||
rst_sync[count_gen] <= 1'b1;
|
||||
rst_sync_int[count_gen]<= 1'b1;
|
||||
rst_sync_int1[count_gen]<= 1'b1;
|
||||
rst_sync_int2[count_gen]<= 1'b1;
|
||||
end
|
||||
else begin
|
||||
rst_sync[count_gen] <= 1'b0;
|
||||
rst_sync_int[count_gen] <= rst_sync[count_gen];
|
||||
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
|
||||
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// Output clock sampling
|
||||
//-----------------------------------
|
||||
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
|
||||
|
||||
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
|
||||
if (rst_sync_int2[count_gen]) begin
|
||||
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
|
||||
end else begin
|
||||
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
|
||||
end
|
||||
end
|
||||
// alias the high bit of each counter to the corresponding
|
||||
// bit in the output bus
|
||||
assign COUNT[count_gen] = counter[count_gen][C_W-1];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,70 @@
|
||||
# file: b200_clk_gen_exdes.xdc
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
# Differential clock only needs one constraint
|
||||
create_clock -name CLK_IN1_P -period 25.0 [get_ports CLK_IN1_P]
|
||||
set_propagated_clock CLK_IN1_P
|
||||
set_input_jitter CLK_IN1_P 0.25
|
||||
|
||||
# FALSE PATH constraint added on COUNTER_RESET
|
||||
set_false_path -from [get_ports "COUNTER_RESET"]
|
||||
set_false_path -from [get_ports "RESET"]
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
# automatically propogated by the tools
|
||||
# However, if you'd like to use them for module level testing, you
|
||||
# can copy them into your module level timing checks
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
+90
@@ -0,0 +1,90 @@
|
||||
REM file: implement.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM -----------------------------------------------------------------------------
|
||||
REM Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
REM -----------------------------------------------------------------------------
|
||||
|
||||
REM Clean up the results directory
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
|
||||
REM Copy unisim_comp.v file to results directory
|
||||
copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
|
||||
|
||||
REM Synthesize the Verilog Wrapper Files
|
||||
echo 'Synthesizing Clocking Wizard design with XST'
|
||||
xst -ifn xst.scr
|
||||
move b200_clk_gen_exdes.ngc results\
|
||||
|
||||
REM Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
copy ..\example_design\b200_clk_gen_exdes.ucf results\
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
ngdbuild -uc b200_clk_gen_exdes.ucf b200_clk_gen_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map -timing -pr b b200_clk_gen_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par -w mapped.ncd routed mapped.pcf
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed -o routed mapped.pcf
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level model for the clocking wizard example design'
|
||||
netgen -ofmt verilog -sim -sdf_anno false -tm b200_clk_gen_exdes -w routed.ncd routed.v
|
||||
cd ..
|
||||
|
||||
+91
@@ -0,0 +1,91 @@
|
||||
#!/bin/sh
|
||||
# file: implement.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
# Clean up the results directory
|
||||
rm -rf results
|
||||
mkdir results
|
||||
|
||||
# Copy unisim_comp.v file to results directory
|
||||
cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
|
||||
|
||||
# Synthesize the Verilog Wrapper Files
|
||||
echo 'Synthesizing Clocking Wizard design with XST'
|
||||
xst -ifn xst.scr
|
||||
mv b200_clk_gen_exdes.ngc results/
|
||||
|
||||
# Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
cp ../example_design/b200_clk_gen_exdes.ucf results/
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
ngdbuild -uc b200_clk_gen_exdes.ucf b200_clk_gen_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map -timing b200_clk_gen_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par -w mapped.ncd routed mapped.pcf
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed -o routed mapped.pcf
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level model for the clocking wizard example design'
|
||||
netgen -ofmt verilog -sim -sdf_anno false -tm b200_clk_gen_exdes -w routed.ncd routed.v
|
||||
|
||||
cd ..
|
||||
@@ -0,0 +1,58 @@
|
||||
REM file: planAhead_ise.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM-----------------------------------------------------------------------------
|
||||
REM Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
REM-----------------------------------------------------------------------------
|
||||
|
||||
del \f results
|
||||
mkdir results
|
||||
cd results
|
||||
|
||||
planAhead -mode batch -source ..\planAhead_ise.tcl
|
||||
@@ -0,0 +1,59 @@
|
||||
#!/bin/sh
|
||||
# file: planAhead_ise.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
rm -rf results
|
||||
mkdir results
|
||||
cd results
|
||||
|
||||
planAhead -mode batch -source ../planAhead_ise.tcl
|
||||
@@ -0,0 +1,78 @@
|
||||
# file: planAhead_ise.tcl
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
set projDir [file dirname [info script]]
|
||||
set projName b200_clk_gen
|
||||
set topName b200_clk_gen_exdes
|
||||
set device xc6slx75csg484-2
|
||||
|
||||
create_project $projName $projDir/results/$projName -part $device
|
||||
|
||||
set_property design_mode RTL [get_filesets sources_1]
|
||||
|
||||
## Source files
|
||||
#set verilogSources [glob $srcDir/*.v]
|
||||
import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/b200_clk_gen_exdes.v
|
||||
import_files -fileset [get_filesets sources_1] -force -norecurse ../../../b200_clk_gen.v
|
||||
|
||||
|
||||
#UCF file
|
||||
import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/b200_clk_gen_exdes.ucf
|
||||
|
||||
set_property top $topName [get_property srcset [current_run]]
|
||||
|
||||
launch_runs -runs synth_1
|
||||
wait_on_run synth_1
|
||||
|
||||
set_property add_step Bitgen [get_runs impl_1]
|
||||
launch_runs -runs impl_1
|
||||
wait_on_run impl_1
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,58 @@
|
||||
REM file: planAhead_rdn.sh
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM-----------------------------------------------------------------------------
|
||||
REM Script to synthesize and implement the RTL provided for the XADC wizard
|
||||
REM-----------------------------------------------------------------------------
|
||||
|
||||
del \f results
|
||||
mkdir results
|
||||
cd results
|
||||
|
||||
planAhead -mode batch -source ..\planAhead_rdn.tcl
|
||||
@@ -0,0 +1,57 @@
|
||||
#!/bin/sh
|
||||
# file: planAhead_rdn.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the RTL provided for the XADC wizard
|
||||
#-----------------------------------------------------------------------------
|
||||
rm -rf results
|
||||
mkdir results
|
||||
cd results
|
||||
planAhead -mode batch -source ../planAhead_rdn.tcl
|
||||
@@ -0,0 +1,69 @@
|
||||
# file : planAhead_rdn.tcl
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
set device xc6slx75csg484-2
|
||||
set projName b200_clk_gen
|
||||
set design b200_clk_gen
|
||||
set projDir [file dirname [info script]]
|
||||
create_project $projName $projDir/results/$projName -part $device -force
|
||||
set_property design_mode RTL [current_fileset -srcset]
|
||||
set top_module b200_clk_gen_exdes
|
||||
set_property top b200_clk_gen_exdes [get_property srcset [current_run]]
|
||||
add_files -norecurse {../../../b200_clk_gen.v}
|
||||
add_files -norecurse {../../example_design/b200_clk_gen_exdes.v}
|
||||
import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/b200_clk_gen_exdes.xdc}
|
||||
synth_design
|
||||
opt_design
|
||||
place_design
|
||||
route_design
|
||||
write_sdf -rename_top_module b200_clk_gen_exdes -file routed.sdf
|
||||
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module b200_clk_gen_exdes -file routed.v
|
||||
report_timing -nworst 30 -path_type full -file routed.twr
|
||||
report_drc -file report.drc
|
||||
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
verilog work ../../b200_clk_gen.v
|
||||
verilog work ../example_design/b200_clk_gen_exdes.v
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
run
|
||||
-ifmt MIXED
|
||||
-top b200_clk_gen_exdes
|
||||
-p xc6slx75-csg484-2
|
||||
-ifn xst.prj
|
||||
-ofn b200_clk_gen_exdes
|
||||
-keep_hierarchy soft
|
||||
-equivalent_register_removal no
|
||||
-max_fanout 65535
|
||||
+146
@@ -0,0 +1,146 @@
|
||||
// file: b200_clk_gen_tb.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Clocking wizard demonstration testbench
|
||||
//----------------------------------------------------------------------------
|
||||
// This demonstration testbench instantiates the example design for the
|
||||
// clocking wizard. Input clocks are toggled, which cause the clocking
|
||||
// network to lock and the counters to increment.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`define wait_lock @(posedge LOCKED)
|
||||
|
||||
module b200_clk_gen_tb ();
|
||||
|
||||
// Clock to Q delay of 100ps
|
||||
localparam TCQ = 100;
|
||||
|
||||
|
||||
// timescale is 1ps/1ps
|
||||
localparam ONE_NS = 1000;
|
||||
localparam PHASE_ERR_MARGIN = 100; // 100ps
|
||||
// how many cycles to run
|
||||
localparam COUNT_PHASE = 1024;
|
||||
// we'll be using the period in many locations
|
||||
localparam time PER1 = 25.0*ONE_NS;
|
||||
localparam time PER1_1 = PER1/2;
|
||||
localparam time PER1_2 = PER1 - PER1/2;
|
||||
|
||||
// Declare the input clock signals
|
||||
reg CLK_IN1 = 1;
|
||||
wire CLK_IN1_P = CLK_IN1;
|
||||
wire CLK_IN1_N = ~CLK_IN1;
|
||||
|
||||
// The high bits of the sampling counters
|
||||
wire [3:1] COUNT;
|
||||
// Status and control signals
|
||||
reg RESET = 0;
|
||||
wire LOCKED;
|
||||
reg COUNTER_RESET = 0;
|
||||
wire [3:1] CLK_OUT;
|
||||
//Freq Check using the M & D values setting and actual Frequency generated
|
||||
|
||||
|
||||
// Input clock generation
|
||||
//------------------------------------
|
||||
always begin
|
||||
CLK_IN1 = #PER1_1 ~CLK_IN1;
|
||||
CLK_IN1 = #PER1_2 ~CLK_IN1;
|
||||
end
|
||||
|
||||
// Test sequence
|
||||
reg [15*8-1:0] test_phase = "";
|
||||
initial begin
|
||||
// Set up any display statements using time to be readable
|
||||
$timeformat(-12, 2, "ps", 10);
|
||||
COUNTER_RESET = 0;
|
||||
test_phase = "reset";
|
||||
RESET = 1;
|
||||
#(PER1*6);
|
||||
RESET = 0;
|
||||
test_phase = "wait lock";
|
||||
`wait_lock;
|
||||
#(PER1*6);
|
||||
COUNTER_RESET = 1;
|
||||
#(PER1*20)
|
||||
COUNTER_RESET = 0;
|
||||
|
||||
test_phase = "counting";
|
||||
#(PER1*COUNT_PHASE);
|
||||
|
||||
$display("SIMULATION PASSED");
|
||||
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Instantiation of the example design containing the clock
|
||||
// network and sampling counters
|
||||
//---------------------------------------------------------
|
||||
b200_clk_gen_exdes
|
||||
#(
|
||||
.TCQ (TCQ)
|
||||
) dut
|
||||
(// Clock in ports
|
||||
.CLK_IN1_P (CLK_IN1_P),
|
||||
.CLK_IN1_N (CLK_IN1_N),
|
||||
// Reset for logic in example design
|
||||
.COUNTER_RESET (COUNTER_RESET),
|
||||
.CLK_OUT (CLK_OUT),
|
||||
// High bits of the counters
|
||||
.COUNT (COUNT),
|
||||
// Status and control signals
|
||||
.RESET (RESET),
|
||||
.LOCKED (LOCKED));
|
||||
|
||||
// Freq Check
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,8 @@
|
||||
# file: simcmds.tcl
|
||||
|
||||
# create the simulation script
|
||||
vcd dumpfile isim.vcd
|
||||
vcd dumpvars -m /b200_clk_gen_tb -l 0
|
||||
wave add /
|
||||
run 50000ns
|
||||
quit
|
||||
@@ -0,0 +1,59 @@
|
||||
REM file: simulate_isim.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
vlogcomp -work work %XILINX%\verilog\src\glbl.v
|
||||
vlogcomp -work work ..\..\..\b200_clk_gen.v
|
||||
vlogcomp -work work ..\..\example_design\b200_clk_gen_exdes.v
|
||||
vlogcomp -work work ..\b200_clk_gen_tb.v
|
||||
|
||||
REM compile the project
|
||||
fuse work.b200_clk_gen_tb work.glbl -L unisims_ver -o b200_clk_gen_isim.exe
|
||||
|
||||
REM run the simulation script
|
||||
.\b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl
|
||||
@@ -0,0 +1,61 @@
|
||||
# file: simulate_isim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# lin64
|
||||
# create the project
|
||||
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
|
||||
vlogcomp -work work ../../../b200_clk_gen.v
|
||||
vlogcomp -work work ../../example_design/b200_clk_gen_exdes.v
|
||||
vlogcomp -work work ../b200_clk_gen_tb.v
|
||||
|
||||
# compile the project
|
||||
fuse work.b200_clk_gen_tb work.glbl -L unisims_ver -o b200_clk_gen_isim.exe
|
||||
|
||||
# run the simulation script
|
||||
./b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl
|
||||
@@ -0,0 +1,61 @@
|
||||
REM file: simulate_mti.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM set up the working directory
|
||||
vlib work
|
||||
|
||||
REM compile all of the files
|
||||
vlog -work work %XILINX%\verilog\src\glbl.v
|
||||
vlog -work work ..\..\..\b200_clk_gen.v
|
||||
vlog -work work ..\..\example_design\b200_clk_gen_exdes.v
|
||||
vlog -work work ..\b200_clk_gen_tb.v
|
||||
|
||||
REM run the simulation
|
||||
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b200_clk_gen_tb work.glbl
|
||||
|
||||
@@ -0,0 +1,65 @@
|
||||
# file: simulate_mti.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $env(XILINX)/verilog/src/glbl.v
|
||||
vlog -work work ../../../b200_clk_gen.v
|
||||
vlog -work work ../../example_design/b200_clk_gen_exdes.v
|
||||
vlog -work work ../b200_clk_gen_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -t ps -voptargs="+acc" -L unisims_ver work.b200_clk_gen_tb work.glbl
|
||||
do wave.do
|
||||
log b200_clk_gen_tb/dut/counter
|
||||
log -r /*
|
||||
run 50000ns
|
||||
@@ -0,0 +1,61 @@
|
||||
#/bin/sh
|
||||
# file: simulate_mti.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $XILINX/verilog/src/glbl.v
|
||||
vlog -work work ../../../b200_clk_gen.v
|
||||
vlog -work work ../../example_design/b200_clk_gen_exdes.v
|
||||
vlog -work work ../b200_clk_gen_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b200_clk_gen_tb work.glbl
|
||||
@@ -0,0 +1,62 @@
|
||||
#/bin/sh
|
||||
# file: simulate_ncsim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
mkdir work
|
||||
|
||||
# compile all of the files
|
||||
ncvlog -work work ${XILINX}/verilog/src/glbl.v
|
||||
ncvlog -work work ../../../b200_clk_gen.v
|
||||
ncvlog -work work ../../example_design/b200_clk_gen_exdes.v
|
||||
ncvlog -work work ../b200_clk_gen_tb.v
|
||||
|
||||
# elaborate and run the simulation
|
||||
ncelab -work work -access +wc work.b200_clk_gen_tb work.glbl
|
||||
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.b200_clk_gen_tb
|
||||
@@ -0,0 +1,72 @@
|
||||
#!/bin/sh
|
||||
# file: simulate_vcs.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# remove old files
|
||||
rm -rf simv* csrc DVEfiles AN.DB
|
||||
|
||||
# compile all of the files
|
||||
# Note that -sverilog is not strictly required- You can
|
||||
# remove the -sverilog if you change the type of the
|
||||
# localparam for the periods in the testbench file to
|
||||
# [63:0] from time
|
||||
vlogan -sverilog \
|
||||
${XILINX}/verilog/src/glbl.v \
|
||||
../../../b200_clk_gen.v \
|
||||
../../example_design/b200_clk_gen_exdes.v \
|
||||
../b200_clk_gen_tb.v
|
||||
|
||||
# prepare the simulation
|
||||
vcs +vcs+lic+wait -debug b200_clk_gen_tb glbl
|
||||
|
||||
# run the simulation
|
||||
./simv -ucli -i ucli_commands.key
|
||||
|
||||
# launch the viewer
|
||||
dve -vpd vcdplus.vpd -session vcs_session.tcl
|
||||
@@ -0,0 +1,5 @@
|
||||
call {$vcdpluson}
|
||||
call {$vcdplusmemon(b200_clk_gen_tb.dut.counter)}
|
||||
run
|
||||
call {$vcdplusclose}
|
||||
quit
|
||||
@@ -0,0 +1,18 @@
|
||||
gui_open_window Wave
|
||||
gui_sg_create b200_clk_gen_group
|
||||
gui_list_add_group -id Wave.1 {b200_clk_gen_group}
|
||||
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.test_phase}
|
||||
gui_set_radix -radix {ascii} -signals {b200_clk_gen_tb.test_phase}
|
||||
gui_sg_addsignal -group b200_clk_gen_group {{Input_clocks}} -divider
|
||||
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.CLK_IN1}
|
||||
gui_sg_addsignal -group b200_clk_gen_group {{Output_clocks}} -divider
|
||||
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.dut.clk}
|
||||
gui_list_expand -id Wave.1 b200_clk_gen_tb.dut.clk
|
||||
gui_sg_addsignal -group b200_clk_gen_group {{Status_control}} -divider
|
||||
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.RESET}
|
||||
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.LOCKED}
|
||||
gui_sg_addsignal -group b200_clk_gen_group {{Counters}} -divider
|
||||
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.COUNT}
|
||||
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.dut.counter}
|
||||
gui_list_expand -id Wave.1 b200_clk_gen_tb.dut.counter
|
||||
gui_zoom -window Wave.1 -full
|
||||
@@ -0,0 +1,60 @@
|
||||
# file: wave.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
add wave -noupdate -format Literal -radix ascii /b200_clk_gen_tb/test_phase
|
||||
add wave -noupdate -divider {Input clocks}
|
||||
add wave -noupdate -format Logic /b200_clk_gen_tb/CLK_IN1
|
||||
add wave -noupdate -divider {Output clocks}
|
||||
add wave -noupdate -format Literal -expand /b200_clk_gen_tb/dut/clk
|
||||
add wave -noupdate -divider Status/control
|
||||
add wave -noupdate -format Logic /b200_clk_gen_tb/RESET
|
||||
add wave -noupdate -format Logic /b200_clk_gen_tb/LOCKED
|
||||
add wave -noupdate -divider Counters
|
||||
add wave -noupdate -format Literal -radix hexadecimal /b200_clk_gen_tb/COUNT
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /b200_clk_gen_tb/dut/counter
|
||||
+119
@@ -0,0 +1,119 @@
|
||||
# file: wave.sv
|
||||
#
|
||||
# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# Get the windows set up
|
||||
#
|
||||
if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {
|
||||
window geometry "Design Browser 1" 1054x819+536+322
|
||||
}
|
||||
window target "Design Browser 1" on
|
||||
browser using {Design Browser 1}
|
||||
browser set \
|
||||
-scope nc::b200_clk_gen_tb
|
||||
browser yview see nc::b200_clk_gen_tb
|
||||
browser timecontrol set -lock 0
|
||||
|
||||
if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
|
||||
window geometry "Waveform 1" 1010x600+0+541
|
||||
}
|
||||
window target "Waveform 1" on
|
||||
waveform using {Waveform 1}
|
||||
waveform sidebar visibility partial
|
||||
waveform set \
|
||||
-primarycursor TimeA \
|
||||
-signalnames name \
|
||||
-signalwidth 175 \
|
||||
-units ns \
|
||||
-valuewidth 75
|
||||
cursor set -using TimeA -time 0
|
||||
waveform baseline set -time 0
|
||||
waveform xview limits 0 20000n
|
||||
|
||||
#
|
||||
# Define signal groups
|
||||
#
|
||||
catch {group new -name {Output clocks} -overlay 0}
|
||||
catch {group new -name {Status/control} -overlay 0}
|
||||
catch {group new -name {Counters} -overlay 0}
|
||||
|
||||
set id [waveform add -signals [list {nc::b200_clk_gen_tb.CLK_IN1}]]
|
||||
|
||||
group using {Output clocks}
|
||||
group set -overlay 0
|
||||
group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{b200_clk_gen_tb.dut.clk[1]} \
|
||||
{b200_clk_gen_tb.dut.clk[2]} \ {b200_clk_gen_tb.dut.clk[3]}
|
||||
group using {Counters}
|
||||
group set -overlay 0
|
||||
group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{b200_clk_gen_tb.dut.counter[1]} \
|
||||
{b200_clk_gen_tb.dut.counter[2]} \ {b200_clk_gen_tb.dut.counter[3]}
|
||||
group using {Status/control}
|
||||
group set -overlay 0
|
||||
group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{nc::b200_clk_gen_tb.RESET} {nc::b200_clk_gen_tb.LOCKED}
|
||||
|
||||
|
||||
set id [waveform add -signals [list {nc::b200_clk_gen_tb.COUNT} ]]
|
||||
|
||||
set id [waveform add -signals [list {nc::b200_clk_gen_tb.test_phase} ]]
|
||||
waveform format $id -radix %a
|
||||
|
||||
set groupId [waveform add -groups {{Input clocks}}]
|
||||
set groupId [waveform add -groups {{Output clocks}}]
|
||||
set groupId [waveform add -groups {{Status/control}}]
|
||||
set groupId [waveform add -groups {{Counters}}]
|
||||
@@ -0,0 +1,160 @@
|
||||
// file: b200_clk_gen_tb.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Clocking wizard demonstration testbench
|
||||
//----------------------------------------------------------------------------
|
||||
// This demonstration testbench instantiates the example design for the
|
||||
// clocking wizard. Input clocks are toggled, which cause the clocking
|
||||
// network to lock and the counters to increment.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`define wait_lock @(posedge LOCKED)
|
||||
|
||||
module b200_clk_gen_tb ();
|
||||
|
||||
// Clock to Q delay of 100ps
|
||||
localparam TCQ = 100;
|
||||
|
||||
|
||||
// timescale is 1ps/1ps
|
||||
localparam ONE_NS = 1000;
|
||||
localparam PHASE_ERR_MARGIN = 100; // 100ps
|
||||
// how many cycles to run
|
||||
localparam COUNT_PHASE = 1024;
|
||||
// we'll be using the period in many locations
|
||||
localparam time PER1 = 25.0*ONE_NS;
|
||||
localparam time PER1_1 = PER1/2;
|
||||
localparam time PER1_2 = PER1 - PER1/2;
|
||||
|
||||
// Declare the input clock signals
|
||||
reg CLK_IN1 = 1;
|
||||
wire CLK_IN1_P = CLK_IN1;
|
||||
wire CLK_IN1_N = ~CLK_IN1;
|
||||
|
||||
// The high bits of the sampling counters
|
||||
wire [3:1] COUNT;
|
||||
// Status and control signals
|
||||
reg RESET = 0;
|
||||
wire LOCKED;
|
||||
reg COUNTER_RESET = 0;
|
||||
wire [3:1] CLK_OUT;
|
||||
//Freq Check using the M & D values setting and actual Frequency generated
|
||||
|
||||
reg [13:0] timeout_counter = 14'b00000000000000;
|
||||
|
||||
// Input clock generation
|
||||
//------------------------------------
|
||||
always begin
|
||||
CLK_IN1 = #PER1_1 ~CLK_IN1;
|
||||
CLK_IN1 = #PER1_2 ~CLK_IN1;
|
||||
end
|
||||
|
||||
// Test sequence
|
||||
reg [15*8-1:0] test_phase = "";
|
||||
initial begin
|
||||
// Set up any display statements using time to be readable
|
||||
$timeformat(-12, 2, "ps", 10);
|
||||
$display ("Timing checks are not valid");
|
||||
COUNTER_RESET = 0;
|
||||
test_phase = "reset";
|
||||
RESET = 1;
|
||||
#(PER1*6);
|
||||
RESET = 0;
|
||||
test_phase = "wait lock";
|
||||
`wait_lock;
|
||||
#(PER1*6);
|
||||
COUNTER_RESET = 1;
|
||||
#(PER1*19.5)
|
||||
COUNTER_RESET = 0;
|
||||
#(PER1*1)
|
||||
$display ("Timing checks are valid");
|
||||
test_phase = "counting";
|
||||
#(PER1*COUNT_PHASE);
|
||||
|
||||
$display("SIMULATION PASSED");
|
||||
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge CLK_IN1) begin
|
||||
timeout_counter <= timeout_counter + 1'b1;
|
||||
if (timeout_counter == 14'b10000000000000) begin
|
||||
if (LOCKED != 1'b1) begin
|
||||
$display("ERROR : NO LOCK signal");
|
||||
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Instantiation of the example design containing the clock
|
||||
// network and sampling counters
|
||||
//---------------------------------------------------------
|
||||
b200_clk_gen_exdes
|
||||
dut
|
||||
(// Clock in ports
|
||||
.CLK_IN1_P (CLK_IN1_P),
|
||||
.CLK_IN1_N (CLK_IN1_N),
|
||||
// Reset for logic in example design
|
||||
.COUNTER_RESET (COUNTER_RESET),
|
||||
.CLK_OUT (CLK_OUT),
|
||||
// High bits of the counters
|
||||
.COUNT (COUNT),
|
||||
// Status and control signals
|
||||
.RESET (RESET),
|
||||
.LOCKED (LOCKED));
|
||||
|
||||
|
||||
// Freq Check
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,2 @@
|
||||
COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
|
||||
SCOPE = b200_clk_gen_tb.dut;
|
||||
@@ -0,0 +1,9 @@
|
||||
# file: simcmds.tcl
|
||||
|
||||
# create the simulation script
|
||||
vcd dumpfile isim.vcd
|
||||
vcd dumpvars -m /b200_clk_gen_tb -l 0
|
||||
wave add /
|
||||
run 50000ns
|
||||
quit
|
||||
|
||||
@@ -0,0 +1,62 @@
|
||||
# file: simulate_isim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# create the project
|
||||
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
|
||||
vlogcomp -work work ../../implement/results/routed.v
|
||||
vlogcomp -work work b200_clk_gen_tb.v
|
||||
|
||||
# compile the project
|
||||
fuse work.b200_clk_gen_tb work.glbl -L secureip -L simprims_ver -o b200_clk_gen_isim.exe
|
||||
|
||||
# run the simulation script
|
||||
./b200_clk_gen_isim.exe -tclbatch simcmds.tcl -sdfmax /b200_clk_gen_tb/dut=../../implement/results/routed.sdf
|
||||
|
||||
# run the simulation script
|
||||
#./b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl
|
||||
@@ -0,0 +1,59 @@
|
||||
REM file: simulate_mti.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
REM compile all of the files
|
||||
vlog -work work %XILINX%\verilog\src\glbl.v
|
||||
vlog -work work ..\..\implement\results\routed.v
|
||||
vlog -work work b200_clk_gen_tb.v
|
||||
|
||||
REM run the simulation
|
||||
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl
|
||||
@@ -0,0 +1,65 @@
|
||||
# file: simulate_mti.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $env(XILINX)/verilog/src/glbl.v
|
||||
vlog -work work ../../implement/results/routed.v
|
||||
vlog -work work b200_clk_gen_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl
|
||||
#do wave.do
|
||||
#log -r /*
|
||||
run 50000ns
|
||||
|
||||
|
||||
@@ -0,0 +1,61 @@
|
||||
#/bin/sh
|
||||
# file: simulate_mti.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $XILINX/verilog/src/glbl.v
|
||||
vlog -work work ../../implement/results/routed.v
|
||||
vlog -work work b200_clk_gen_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl
|
||||
@@ -0,0 +1,64 @@
|
||||
#!/bin/sh
|
||||
# file: simulate_ncsim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
mkdir work
|
||||
|
||||
# compile all of the files
|
||||
ncvlog -work work ${XILINX}/verilog/src/glbl.v
|
||||
ncvlog -work work ../../implement/results/routed.v
|
||||
ncvlog -work work b200_clk_gen_tb.v
|
||||
|
||||
# elaborate and run the simulation
|
||||
ncsdfc ../../implement/results/routed.sdf
|
||||
|
||||
ncelab -work work -access +wc -pulse_r 10 -nonotifier work.b200_clk_gen_tb work.glbl -sdf_cmd_file sdf_cmd_file
|
||||
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.b200_clk_gen_tb
|
||||
|
||||
@@ -0,0 +1,72 @@
|
||||
#!/bin/sh
|
||||
# file: simulate_vcs.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# remove old files
|
||||
rm -rf simv* csrc DVEfiles AN.DB
|
||||
|
||||
# compile all of the files
|
||||
# Note that -sverilog is not strictly required- You can
|
||||
# remove the -sverilog if you change the type of the
|
||||
# localparam for the periods in the testbench file to
|
||||
# [63:0] from time
|
||||
vlogan -sverilog \
|
||||
b200_clk_gen_tb.v \
|
||||
../../implement/results/routed.v
|
||||
|
||||
|
||||
# prepare the simulation
|
||||
vcs -sdf max:b200_clk_gen_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
|
||||
+libext+.v -debug b200_clk_gen_tb.v ../../implement/results/routed.v
|
||||
|
||||
# run the simulation
|
||||
./simv -ucli -i ucli_commands.key
|
||||
|
||||
# launch the viewer
|
||||
#dve -vpd vcdplus.vpd -session vcs_session.tcl
|
||||
@@ -0,0 +1,5 @@
|
||||
|
||||
call {$vcdpluson}
|
||||
run 50000ns
|
||||
call {$vcdplusclose}
|
||||
quit
|
||||
@@ -0,0 +1 @@
|
||||
gui_open_window Wave
|
||||
+72
@@ -0,0 +1,72 @@
|
||||
# file: wave.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /b200_clk_gen_tb/CLK_IN1
|
||||
add wave -noupdate /b200_clk_gen_tb/COUNT
|
||||
add wave -noupdate /b200_clk_gen_tb/LOCKED
|
||||
add wave -noupdate /b200_clk_gen_tb/RESET
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
|
||||
configure wave -namecolwidth 238
|
||||
configure wave -valuecolwidth 107
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ps
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {74848022 ps}
|
||||
@@ -0,0 +1,53 @@
|
||||
# Output products list for <b200_clk_gen>
|
||||
b200_clk_gen/clk_wiz_v3_6_readme.txt
|
||||
b200_clk_gen/doc/clk_wiz_v3_6_readme.txt
|
||||
b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html
|
||||
b200_clk_gen/doc/pg065_clk_wiz.pdf
|
||||
b200_clk_gen/example_design/b200_clk_gen_exdes.ucf
|
||||
b200_clk_gen/example_design/b200_clk_gen_exdes.v
|
||||
b200_clk_gen/example_design/b200_clk_gen_exdes.xdc
|
||||
b200_clk_gen/implement/implement.bat
|
||||
b200_clk_gen/implement/implement.sh
|
||||
b200_clk_gen/implement/planAhead_ise.bat
|
||||
b200_clk_gen/implement/planAhead_ise.sh
|
||||
b200_clk_gen/implement/planAhead_ise.tcl
|
||||
b200_clk_gen/implement/planAhead_rdn.bat
|
||||
b200_clk_gen/implement/planAhead_rdn.sh
|
||||
b200_clk_gen/implement/planAhead_rdn.tcl
|
||||
b200_clk_gen/implement/xst.prj
|
||||
b200_clk_gen/implement/xst.scr
|
||||
b200_clk_gen/simulation/b200_clk_gen_tb.v
|
||||
b200_clk_gen/simulation/functional/simcmds.tcl
|
||||
b200_clk_gen/simulation/functional/simulate_isim.bat
|
||||
b200_clk_gen/simulation/functional/simulate_isim.sh
|
||||
b200_clk_gen/simulation/functional/simulate_mti.bat
|
||||
b200_clk_gen/simulation/functional/simulate_mti.do
|
||||
b200_clk_gen/simulation/functional/simulate_mti.sh
|
||||
b200_clk_gen/simulation/functional/simulate_ncsim.sh
|
||||
b200_clk_gen/simulation/functional/simulate_vcs.sh
|
||||
b200_clk_gen/simulation/functional/ucli_commands.key
|
||||
b200_clk_gen/simulation/functional/vcs_session.tcl
|
||||
b200_clk_gen/simulation/functional/wave.do
|
||||
b200_clk_gen/simulation/functional/wave.sv
|
||||
b200_clk_gen/simulation/timing/b200_clk_gen_tb.v
|
||||
b200_clk_gen/simulation/timing/sdf_cmd_file
|
||||
b200_clk_gen/simulation/timing/simcmds.tcl
|
||||
b200_clk_gen/simulation/timing/simulate_isim.sh
|
||||
b200_clk_gen/simulation/timing/simulate_mti.bat
|
||||
b200_clk_gen/simulation/timing/simulate_mti.do
|
||||
b200_clk_gen/simulation/timing/simulate_mti.sh
|
||||
b200_clk_gen/simulation/timing/simulate_ncsim.sh
|
||||
b200_clk_gen/simulation/timing/simulate_vcs.sh
|
||||
b200_clk_gen/simulation/timing/ucli_commands.key
|
||||
b200_clk_gen/simulation/timing/vcs_session.tcl
|
||||
b200_clk_gen/simulation/timing/wave.do
|
||||
b200_clk_gen.asy
|
||||
b200_clk_gen.gise
|
||||
b200_clk_gen.ucf
|
||||
b200_clk_gen.v
|
||||
b200_clk_gen.veo
|
||||
b200_clk_gen.xco
|
||||
b200_clk_gen.xdc
|
||||
b200_clk_gen.xise
|
||||
b200_clk_gen_flist.txt
|
||||
b200_clk_gen_xmdf.tcl
|
||||
Executable
+144
@@ -0,0 +1,144 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide b200_clk_gen_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::b200_clk_gen_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::b200_clk_gen_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_clk_gen
|
||||
}
|
||||
# ::b200_clk_gen_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::b200_clk_gen_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/clk_wiz_readme.txt
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/example_design/b200_clk_gen_exdes.ucf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/doc/clk_wiz_ds709.pdf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/doc/clk_wiz_gsg521.pdf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/example_design/b200_clk_gen_exdes.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/implement.bat
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/implement.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/xst.prj
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/xst.scr
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/b200_clk_gen_tb.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simcmds.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_isim.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_mti.do
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_ncsim.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_vcs.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/ucli_commands.key
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/vcs_session.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/wave.do
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/wave.sv
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.ejp
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_clk_gen
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
@@ -0,0 +1,9 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 chipscope_icon
|
||||
RECTANGLE Normal 32 32 544 864
|
||||
LINE Wide 576 112 544 112
|
||||
PIN 576 112 RIGHT 36
|
||||
PINATTR PinName control0[35:0]
|
||||
PINATTR Polarity BOTH
|
||||
|
||||
@@ -0,0 +1,9 @@
|
||||
NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
|
||||
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
|
||||
#Update Constraints
|
||||
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
|
||||
NET "U0/iSHIFT_OUT" TIG ;
|
||||
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
|
||||
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
|
||||
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
|
||||
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
|
||||
@@ -0,0 +1,7 @@
|
||||
# icon XDC
|
||||
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
|
||||
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
|
||||
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
|
||||
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
|
||||
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,9 @@
|
||||
NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
|
||||
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
|
||||
#Update Constraints
|
||||
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
|
||||
NET "U0/iSHIFT_OUT" TIG ;
|
||||
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
|
||||
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
|
||||
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
|
||||
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
|
||||
@@ -0,0 +1,27 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2013 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 14.4
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : chipscope_icon.v
|
||||
// /___/ /\ Timestamp : Tue Oct 22 17:04:59 PDT 2013
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
// Design Name: Verilog Synthesis Wrapper
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// This wrapper is used to integrate with Project Navigator and PlanAhead
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module chipscope_icon(
|
||||
CONTROL0) /* synthesis syn_black_box syn_noprune=1 */;
|
||||
|
||||
|
||||
inout [35 : 0] CONTROL0;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,28 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2013 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 14.4
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : chipscope_icon.veo
|
||||
// /___/ /\ Timestamp : Tue Oct 22 17:05:00 PDT 2013
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
// Design Name: ISE Instantiation template
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
chipscope_icon YourInstanceName (
|
||||
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
@@ -0,0 +1,56 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Wed Oct 23 00:04:31 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc6slx75
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -3
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET component_name=chipscope_icon
|
||||
CSET constraint_type=external
|
||||
CSET enable_jtag_bufg=true
|
||||
CSET example_design=false
|
||||
CSET number_control_ports=1
|
||||
CSET use_ext_bscan=false
|
||||
CSET use_softbscan=false
|
||||
CSET use_unused_bscan=false
|
||||
CSET user_scan_chain=USER1
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-12-18T02:47:25Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 5ccf4baf
|
||||
@@ -0,0 +1,7 @@
|
||||
# icon XDC
|
||||
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
|
||||
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
|
||||
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
|
||||
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
|
||||
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
|
||||
@@ -0,0 +1,16 @@
|
||||
# Output products list for <chipscope_icon>
|
||||
_xmsgs/pn_parser.xmsgs
|
||||
chipscope_icon.asy
|
||||
chipscope_icon.constraints/chipscope_icon.ucf
|
||||
chipscope_icon.constraints/chipscope_icon.xdc
|
||||
chipscope_icon.gise
|
||||
chipscope_icon.ngc
|
||||
chipscope_icon.ucf
|
||||
chipscope_icon.v
|
||||
chipscope_icon.veo
|
||||
chipscope_icon.xco
|
||||
chipscope_icon.xdc
|
||||
chipscope_icon.xise
|
||||
chipscope_icon_flist.txt
|
||||
chipscope_icon_readme.txt
|
||||
chipscope_icon_xmdf.tcl
|
||||
@@ -0,0 +1,46 @@
|
||||
The following files were generated for 'chipscope_icon' in directory
|
||||
/home/ianb/fpgadev/usrp3/top/b200/coregen/
|
||||
|
||||
XCO file generator:
|
||||
Generate an XCO file for compatibility with legacy flows.
|
||||
|
||||
* chipscope_icon.xco
|
||||
|
||||
Creates an implementation netlist:
|
||||
Creates an implementation netlist for the IP.
|
||||
|
||||
* chipscope_icon.constraints/chipscope_icon.ucf
|
||||
* chipscope_icon.constraints/chipscope_icon.xdc
|
||||
* chipscope_icon.ngc
|
||||
* chipscope_icon.ucf
|
||||
* chipscope_icon.v
|
||||
* chipscope_icon.veo
|
||||
* chipscope_icon.xdc
|
||||
* chipscope_icon_xmdf.tcl
|
||||
|
||||
IP Symbol Generator:
|
||||
Generate an IP symbol based on the current project options'.
|
||||
|
||||
* chipscope_icon.asy
|
||||
|
||||
Generate ISE subproject:
|
||||
Create an ISE subproject for use when including this core in ISE designs
|
||||
|
||||
* _xmsgs/pn_parser.xmsgs
|
||||
* chipscope_icon.gise
|
||||
* chipscope_icon.xise
|
||||
|
||||
Deliver Readme:
|
||||
Readme file for the IP.
|
||||
|
||||
* chipscope_icon_readme.txt
|
||||
|
||||
Generate FLIST file:
|
||||
Text file listing all of the output files produced when a customized core was
|
||||
generated in the CORE Generator.
|
||||
|
||||
* chipscope_icon_flist.txt
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
Executable
+88
@@ -0,0 +1,88 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide chipscope_icon_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::chipscope_icon_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::chipscope_icon_xmdf::xmdfInit { instance } {
|
||||
# Variable containing name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_icon
|
||||
}
|
||||
# ::chipscope_icon_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::chipscope_icon_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.ucf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ncf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.xdc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xcf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_icon
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
|
||||
|
||||
@@ -0,0 +1,17 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 chipscope_ila_128
|
||||
RECTANGLE Normal 32 32 288 704
|
||||
LINE Wide 0 80 32 80
|
||||
PIN 0 80 LEFT 36
|
||||
PINATTR PinName control[35:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 112 32 112
|
||||
PIN 0 112 LEFT 36
|
||||
PINATTR PinName clk
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 176 32 176
|
||||
PIN 0 176 LEFT 36
|
||||
PINATTR PinName trig0[127:0]
|
||||
PINATTR Polarity IN
|
||||
|
||||
@@ -0,0 +1,144 @@
|
||||
#ChipScope Core Generator Project File Version 3.0
|
||||
#Tue Oct 22 15:45:46 PDT 2013
|
||||
SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
|
||||
SignalExport.bus<0000>.name=TRIG0
|
||||
SignalExport.bus<0000>.offset=0.0
|
||||
SignalExport.bus<0000>.precision=0
|
||||
SignalExport.bus<0000>.radix=Bin
|
||||
SignalExport.bus<0000>.scaleFactor=1.0
|
||||
SignalExport.clockChannel=CLK
|
||||
SignalExport.dataEqualsTrigger=true
|
||||
SignalExport.triggerChannel<0000><0000>=TRIG0[0]
|
||||
SignalExport.triggerChannel<0000><0001>=TRIG0[1]
|
||||
SignalExport.triggerChannel<0000><0002>=TRIG0[2]
|
||||
SignalExport.triggerChannel<0000><0003>=TRIG0[3]
|
||||
SignalExport.triggerChannel<0000><0004>=TRIG0[4]
|
||||
SignalExport.triggerChannel<0000><0005>=TRIG0[5]
|
||||
SignalExport.triggerChannel<0000><0006>=TRIG0[6]
|
||||
SignalExport.triggerChannel<0000><0007>=TRIG0[7]
|
||||
SignalExport.triggerChannel<0000><0008>=TRIG0[8]
|
||||
SignalExport.triggerChannel<0000><0009>=TRIG0[9]
|
||||
SignalExport.triggerChannel<0000><0010>=TRIG0[10]
|
||||
SignalExport.triggerChannel<0000><0011>=TRIG0[11]
|
||||
SignalExport.triggerChannel<0000><0012>=TRIG0[12]
|
||||
SignalExport.triggerChannel<0000><0013>=TRIG0[13]
|
||||
SignalExport.triggerChannel<0000><0014>=TRIG0[14]
|
||||
SignalExport.triggerChannel<0000><0015>=TRIG0[15]
|
||||
SignalExport.triggerChannel<0000><0016>=TRIG0[16]
|
||||
SignalExport.triggerChannel<0000><0017>=TRIG0[17]
|
||||
SignalExport.triggerChannel<0000><0018>=TRIG0[18]
|
||||
SignalExport.triggerChannel<0000><0019>=TRIG0[19]
|
||||
SignalExport.triggerChannel<0000><0020>=TRIG0[20]
|
||||
SignalExport.triggerChannel<0000><0021>=TRIG0[21]
|
||||
SignalExport.triggerChannel<0000><0022>=TRIG0[22]
|
||||
SignalExport.triggerChannel<0000><0023>=TRIG0[23]
|
||||
SignalExport.triggerChannel<0000><0024>=TRIG0[24]
|
||||
SignalExport.triggerChannel<0000><0025>=TRIG0[25]
|
||||
SignalExport.triggerChannel<0000><0026>=TRIG0[26]
|
||||
SignalExport.triggerChannel<0000><0027>=TRIG0[27]
|
||||
SignalExport.triggerChannel<0000><0028>=TRIG0[28]
|
||||
SignalExport.triggerChannel<0000><0029>=TRIG0[29]
|
||||
SignalExport.triggerChannel<0000><0030>=TRIG0[30]
|
||||
SignalExport.triggerChannel<0000><0031>=TRIG0[31]
|
||||
SignalExport.triggerChannel<0000><0032>=TRIG0[32]
|
||||
SignalExport.triggerChannel<0000><0033>=TRIG0[33]
|
||||
SignalExport.triggerChannel<0000><0034>=TRIG0[34]
|
||||
SignalExport.triggerChannel<0000><0035>=TRIG0[35]
|
||||
SignalExport.triggerChannel<0000><0036>=TRIG0[36]
|
||||
SignalExport.triggerChannel<0000><0037>=TRIG0[37]
|
||||
SignalExport.triggerChannel<0000><0038>=TRIG0[38]
|
||||
SignalExport.triggerChannel<0000><0039>=TRIG0[39]
|
||||
SignalExport.triggerChannel<0000><0040>=TRIG0[40]
|
||||
SignalExport.triggerChannel<0000><0041>=TRIG0[41]
|
||||
SignalExport.triggerChannel<0000><0042>=TRIG0[42]
|
||||
SignalExport.triggerChannel<0000><0043>=TRIG0[43]
|
||||
SignalExport.triggerChannel<0000><0044>=TRIG0[44]
|
||||
SignalExport.triggerChannel<0000><0045>=TRIG0[45]
|
||||
SignalExport.triggerChannel<0000><0046>=TRIG0[46]
|
||||
SignalExport.triggerChannel<0000><0047>=TRIG0[47]
|
||||
SignalExport.triggerChannel<0000><0048>=TRIG0[48]
|
||||
SignalExport.triggerChannel<0000><0049>=TRIG0[49]
|
||||
SignalExport.triggerChannel<0000><0050>=TRIG0[50]
|
||||
SignalExport.triggerChannel<0000><0051>=TRIG0[51]
|
||||
SignalExport.triggerChannel<0000><0052>=TRIG0[52]
|
||||
SignalExport.triggerChannel<0000><0053>=TRIG0[53]
|
||||
SignalExport.triggerChannel<0000><0054>=TRIG0[54]
|
||||
SignalExport.triggerChannel<0000><0055>=TRIG0[55]
|
||||
SignalExport.triggerChannel<0000><0056>=TRIG0[56]
|
||||
SignalExport.triggerChannel<0000><0057>=TRIG0[57]
|
||||
SignalExport.triggerChannel<0000><0058>=TRIG0[58]
|
||||
SignalExport.triggerChannel<0000><0059>=TRIG0[59]
|
||||
SignalExport.triggerChannel<0000><0060>=TRIG0[60]
|
||||
SignalExport.triggerChannel<0000><0061>=TRIG0[61]
|
||||
SignalExport.triggerChannel<0000><0062>=TRIG0[62]
|
||||
SignalExport.triggerChannel<0000><0063>=TRIG0[63]
|
||||
SignalExport.triggerChannel<0000><0064>=TRIG0[64]
|
||||
SignalExport.triggerChannel<0000><0065>=TRIG0[65]
|
||||
SignalExport.triggerChannel<0000><0066>=TRIG0[66]
|
||||
SignalExport.triggerChannel<0000><0067>=TRIG0[67]
|
||||
SignalExport.triggerChannel<0000><0068>=TRIG0[68]
|
||||
SignalExport.triggerChannel<0000><0069>=TRIG0[69]
|
||||
SignalExport.triggerChannel<0000><0070>=TRIG0[70]
|
||||
SignalExport.triggerChannel<0000><0071>=TRIG0[71]
|
||||
SignalExport.triggerChannel<0000><0072>=TRIG0[72]
|
||||
SignalExport.triggerChannel<0000><0073>=TRIG0[73]
|
||||
SignalExport.triggerChannel<0000><0074>=TRIG0[74]
|
||||
SignalExport.triggerChannel<0000><0075>=TRIG0[75]
|
||||
SignalExport.triggerChannel<0000><0076>=TRIG0[76]
|
||||
SignalExport.triggerChannel<0000><0077>=TRIG0[77]
|
||||
SignalExport.triggerChannel<0000><0078>=TRIG0[78]
|
||||
SignalExport.triggerChannel<0000><0079>=TRIG0[79]
|
||||
SignalExport.triggerChannel<0000><0080>=TRIG0[80]
|
||||
SignalExport.triggerChannel<0000><0081>=TRIG0[81]
|
||||
SignalExport.triggerChannel<0000><0082>=TRIG0[82]
|
||||
SignalExport.triggerChannel<0000><0083>=TRIG0[83]
|
||||
SignalExport.triggerChannel<0000><0084>=TRIG0[84]
|
||||
SignalExport.triggerChannel<0000><0085>=TRIG0[85]
|
||||
SignalExport.triggerChannel<0000><0086>=TRIG0[86]
|
||||
SignalExport.triggerChannel<0000><0087>=TRIG0[87]
|
||||
SignalExport.triggerChannel<0000><0088>=TRIG0[88]
|
||||
SignalExport.triggerChannel<0000><0089>=TRIG0[89]
|
||||
SignalExport.triggerChannel<0000><0090>=TRIG0[90]
|
||||
SignalExport.triggerChannel<0000><0091>=TRIG0[91]
|
||||
SignalExport.triggerChannel<0000><0092>=TRIG0[92]
|
||||
SignalExport.triggerChannel<0000><0093>=TRIG0[93]
|
||||
SignalExport.triggerChannel<0000><0094>=TRIG0[94]
|
||||
SignalExport.triggerChannel<0000><0095>=TRIG0[95]
|
||||
SignalExport.triggerChannel<0000><0096>=TRIG0[96]
|
||||
SignalExport.triggerChannel<0000><0097>=TRIG0[97]
|
||||
SignalExport.triggerChannel<0000><0098>=TRIG0[98]
|
||||
SignalExport.triggerChannel<0000><0099>=TRIG0[99]
|
||||
SignalExport.triggerChannel<0000><0100>=TRIG0[100]
|
||||
SignalExport.triggerChannel<0000><0101>=TRIG0[101]
|
||||
SignalExport.triggerChannel<0000><0102>=TRIG0[102]
|
||||
SignalExport.triggerChannel<0000><0103>=TRIG0[103]
|
||||
SignalExport.triggerChannel<0000><0104>=TRIG0[104]
|
||||
SignalExport.triggerChannel<0000><0105>=TRIG0[105]
|
||||
SignalExport.triggerChannel<0000><0106>=TRIG0[106]
|
||||
SignalExport.triggerChannel<0000><0107>=TRIG0[107]
|
||||
SignalExport.triggerChannel<0000><0108>=TRIG0[108]
|
||||
SignalExport.triggerChannel<0000><0109>=TRIG0[109]
|
||||
SignalExport.triggerChannel<0000><0110>=TRIG0[110]
|
||||
SignalExport.triggerChannel<0000><0111>=TRIG0[111]
|
||||
SignalExport.triggerChannel<0000><0112>=TRIG0[112]
|
||||
SignalExport.triggerChannel<0000><0113>=TRIG0[113]
|
||||
SignalExport.triggerChannel<0000><0114>=TRIG0[114]
|
||||
SignalExport.triggerChannel<0000><0115>=TRIG0[115]
|
||||
SignalExport.triggerChannel<0000><0116>=TRIG0[116]
|
||||
SignalExport.triggerChannel<0000><0117>=TRIG0[117]
|
||||
SignalExport.triggerChannel<0000><0118>=TRIG0[118]
|
||||
SignalExport.triggerChannel<0000><0119>=TRIG0[119]
|
||||
SignalExport.triggerChannel<0000><0120>=TRIG0[120]
|
||||
SignalExport.triggerChannel<0000><0121>=TRIG0[121]
|
||||
SignalExport.triggerChannel<0000><0122>=TRIG0[122]
|
||||
SignalExport.triggerChannel<0000><0123>=TRIG0[123]
|
||||
SignalExport.triggerChannel<0000><0124>=TRIG0[124]
|
||||
SignalExport.triggerChannel<0000><0125>=TRIG0[125]
|
||||
SignalExport.triggerChannel<0000><0126>=TRIG0[126]
|
||||
SignalExport.triggerChannel<0000><0127>=TRIG0[127]
|
||||
SignalExport.triggerPort<0000>.name=TRIG0
|
||||
SignalExport.triggerPortCount=1
|
||||
SignalExport.triggerPortIsData<0000>=true
|
||||
SignalExport.triggerPortWidth<0000>=128
|
||||
SignalExport.type=ila
|
||||
|
||||
@@ -0,0 +1,15 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
NET "CLK" TNM_NET = D_CLK ;
|
||||
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
|
||||
TIMESPEC TS_D2_TO_T2_chipscope_ila_128 = FROM D2_CLK TO "FFS" TIG;
|
||||
TIMESPEC TS_J2_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J3_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J4_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG;
|
||||
|
||||
#
|
||||
# Input keep/save net constraints
|
||||
#
|
||||
NET "TRIG0<*" S;
|
||||
NET "TRIG0<*" KEEP;
|
||||
@@ -0,0 +1,6 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
|
||||
set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
|
||||
set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,15 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
NET "CLK" TNM_NET = D_CLK ;
|
||||
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
|
||||
TIMESPEC TS_D2_TO_T2_chipscope_ila_128 = FROM D2_CLK TO "FFS" TIG;
|
||||
TIMESPEC TS_J2_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J3_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J4_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG;
|
||||
|
||||
#
|
||||
# Input keep/save net constraints
|
||||
#
|
||||
NET "TRIG0<*" S;
|
||||
NET "TRIG0<*" KEEP;
|
||||
@@ -0,0 +1,31 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2013 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 14.4
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : chipscope_ila_128.v
|
||||
// /___/ /\ Timestamp : Tue Oct 22 15:45:46 PDT 2013
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
// Design Name: Verilog Synthesis Wrapper
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// This wrapper is used to integrate with Project Navigator and PlanAhead
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module chipscope_ila_128(
|
||||
CONTROL,
|
||||
CLK,
|
||||
TRIG0) /* synthesis syn_black_box syn_noprune=1 */;
|
||||
|
||||
|
||||
inout [35 : 0] CONTROL;
|
||||
input CLK;
|
||||
input [127 : 0] TRIG0;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,30 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2013 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 14.4
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : chipscope_ila_128.veo
|
||||
// /___/ /\ Timestamp : Tue Oct 22 15:45:46 PDT 2013
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
// Design Name: ISE Instantiation template
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
chipscope_ila_128 YourInstanceName (
|
||||
.CONTROL(CONTROL), // INOUT BUS [35:0]
|
||||
.CLK(CLK), // IN
|
||||
.TRIG0(TRIG0) // IN BUS [127:0]
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user