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Merge FPGA repository back into UHD repository

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The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>


Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
2020-01-28 09:35:36 -08:00
co-authored by Alex Williams Andrej Rode Ashish Chaudhari Ben Hilburn Ciro Nishiguchi Daniel Jepson Derek Kozel EJ Kreinar Humberto Jimenez Ian Buckley Jörg Hofrichter Jon Kiser Josh Blum Jonathon Pendlum Matt Ettus Michael West Moritz Fischer Nick Foster Nicolas Cuervo Paul Butler Paul David Ryan Marlow Sugandha Gupta Sylvain Munaut Trung Tran Vidush Vishwanath Wade Fife
parent 74893643ca
commit 6b67702ad7
2157 changed files with 1282567 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/b200/.gitignore
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build*
catcap_tb
catgen_tb
fuse*
isim*
top/b200/Makefile
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#
# Copyright 2012-2014 Ettus Research LLC
#
# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
##-------------------
##USRP B2X0 FPGA Help
##-------------------
##Usage:
## make <Targets> <Options>
##
##Output:
## build/usrp_<product>_fpga.bit: Configuration bitstream with header
## build/usrp_<product>_fpga.bin: Configuration bitstream without header
## build/usrp_<product>_fpga.syr: Xilinx system report
## build/usrp_<product>_fpga.twr: Xilinx timing report
# Build USRP B2x0 design with a debug UART on J400
ifeq ($(DEBUG_UART),1)
OPTIONS += DEBUG_UART=1
endif
print_report = \
echo "========================================================================"; \
cat $(1)/b200.syr | grep "Device utilization summary:" -A 30; \
echo "========================================================================"; \
echo "Timing Summary:\n"; \
cat $(1)/b200.twr | grep constraint | grep met | grep -v "*"; \
echo "========================================================================";
# pre_build($1=Device)
ifeq ($(EXPORT_ONLY),1)
pre_build = @test -s build-$(1)/b200.bit || { echo "EXPORT_ONLY requires the project in build-$(1) to be fully built."; false; }
else
pre_build = @echo "ISE Version: $(shell xtclsh -h | head -n1)"
endif
# ise_build($1=Device, $2=Definitions)
ifeq ($(PROJECT_ONLY),1)
ise_build = make -f Makefile.b200.inc proj NAME=$@ DEVICE=$1 EXTRA_DEFS="$2 $(OPTIONS)"
else ifeq ($(EXPORT_ONLY),1)
ise_build = @echo "Skipping ISE build and exporting pre-built files.";
else
ise_build = make -f Makefile.b200.inc bin NAME=$@ DEVICE=$1 EXTRA_DEFS="$2 $(OPTIONS)"
endif
# post_build($1=Device)
ifeq ($(PROJECT_ONLY),1)
post_build = \
@echo "Generated $(shell pwd)/build-$(1)/b200.xise"; \
echo "\nProject Generation DONE ... $(1)\n";
else
post_build = \
@$(call print_report,build-$(1)) \
mkdir -p build; \
echo "Exporting bitstream files..."; \
cp build-$(1)/b200.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga.bin; \
cp build-$(1)/b200.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga.bit; \
echo "Exporting logs..."; \
cp build-$(1)/b200.syr build/usrp_`echo $(1) | tr A-Z a-z`_fpga.syr; \
cp build-$(1)/b200.twr build/usrp_`echo $(1) | tr A-Z a-z`_fpga.twr; \
echo "\nBuild DONE ... $(1)\n";
endif
##
##Supported Targets
##-----------------
all: B200 B210 ##(Default target)
B200: ##Build USRP B200 design.
$(call pre_build,B200)
$(call ise_build,XC6SLX75,)
$(call post_build,B200)
B210: ##Build USRP B210 design.
$(call pre_build,B210)
$(call ise_build,XC6SLX150,TARGET_B210=1)
$(call post_build,B210)
clean: ##Clean up all build output.
rm -rf build-*
rm -rf build
help: ## Show this help message.
@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
##
##Supported Options
##-----------------
##PROJECT_ONLY=1 Only create a Xilinx project for the specified target(s).
## Useful for use with the ISE GUI.
##EXPORT_ONLY=1 Export build targets from a GUI build to the build directory.
## Requires the project in build-*_* to be built.
##DEBUG_UART=1 Build USRP B2x0 design with a debug UART on J400
.PHONY: all clean help
top/b200/Makefile.b200.inc
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#
# Copyright 2012-2013 Ettus Research LLC
#
##################################################
# Project Setup
##################################################
TOP_MODULE := b200
BUILD_DIR := build-$(NAME)/
export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
# set me in a custom makefile
CUSTOM_SRCS =
CUSTOM_DEFS =
include ../Makefile.common
include ../../lib/gpif2/Makefile.srcs
include ../../lib/fifo/Makefile.srcs
include ../../lib/fifo_200/Makefile.srcs
include ../../lib/dsp/Makefile.srcs
include ../../lib/control/Makefile.srcs
include ../../lib/control_200/Makefile.srcs
include ../../lib/packet_proc/Makefile.srcs
include ../../lib/packet_proc_200/Makefile.srcs
include ../../lib/timing/Makefile.srcs
include ../../lib/vita_200/Makefile.srcs
include ../../lib/wishbone/Makefile.srcs
include ../../lib/axi/Makefile.srcs
include ../../lib/radio_200/Makefile.srcs
include ../../lib/io_cap_gen/Makefile.srcs
include coregen_dsp/Makefile.srcs
B200_COREGEN_SRCS = \
coregen/b200_clk_gen.v \
coregen/fifo_4k_2clk.xco \
coregen/fifo_short_2clk.xco \
coregen/chipscope_icon.v \
coregen/chipscope_icon.xco \
coregen/chipscope_ila_32.v \
coregen/chipscope_ila_32.xco \
coregen/chipscope_ila_128.v \
coregen/chipscope_ila_128.xco \
coregen/chipscope_ila_256.v \
coregen/chipscope_ila_256.xco
##################################################
# Project Properties
##################################################
export PROJECT_PROPERTIES := \
family "Spartan6" \
device $(DEVICE) \
package fgg484 \
speed -3 \
top_level_module_type "HDL" \
synthesis_tool "XST (VHDL/Verilog)" \
simulator "ISE Simulator (VHDL/Verilog)" \
"Preferred Language" "Verilog" \
"Enable Message Filtering" FALSE \
"Display Incremental Messages" FALSE
##################################################
# Sources
##################################################
TOP_SRCS = \
b200.v \
b200_core.v \
b200_io.v \
b200.ucf \
timing.ucf \
S6CLK2PIN.v \
$(B200_COREGEN_SRCS)
# GPIO only available for B210
# The LX75 on the B200 is missing the connection from the balls to the internal fabric
ifeq ($(NAME),B210)
TOP_SRCS+=gpio.ucf
endif
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) $(FIFO_200_SRCS) \
$(CONTROL_LIB_SRCS) $(CONTROL_LIB_200_SRCS) $(SDR_LIB_SRCS) \
$(TIMING_SRCS) $(OPENCORES_SRCS) \
$(VRT_SRCS) \
$(GPIF2_SRCS) $(PACKET_PROC_SRCS) $(PACKET_PROC_200_SRCS) \
$(WISHBONE_SRCS) \
$(TIMING_SRCS) \
$(DSP_SRCS) \
$(VITA_200_SRCS) \
$(AXI_SRCS) \
$(RADIO_200_SRCS) \
$(CAT_CAP_GEN_SRCS) \
$(COREGEN_DSP_SRCS)
##################################################
# Process Properties
##################################################
SYNTHESIZE_PROPERTIES = \
"Pack I/O Registers into IOBs" Yes \
"Optimization Effort" High \
"Optimize Instantiated Primitives" TRUE \
"Register Balancing" Yes \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
"Use Synchronous Set" Auto \
"Verilog Macros" "SPARTAN6=1 $(EXTRA_DEFS) $(CUSTOM_DEFS)" \
"Other XST Command Line Options" "-loop_iteration_limit 16385"
#"Number of Clock Buffers" 8 \
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
MAP_PROPERTIES = \
"Generate Detailed MAP Report" TRUE \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Map to Input Functions" 4 \
"Optimization Strategy (Cover Mode)" Speed \
"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
"Perform Timing-Driven Packing and Placement" TRUE \
"Map Effort Level" High \
"Extra Effort" Normal \
"Combinatorial Logic Optimization" TRUE \
"Register Duplication" TRUE
PLACE_ROUTE_PROPERTIES = \
"Place & Route Effort Level (Overall)" High
STATIC_TIMING_PROPERTIES = \
"Number of Paths in Error/Verbose Report" 10 \
"Report Type" "Error Report"
GEN_PROG_FILE_PROPERTIES = \
"Create Binary Configuration File" TRUE \
"Done (Output Events)" 5 \
"Enable Bitstream Compression" TRUE \
"Unused IOB Pins" "Pull Up"
#"Configuration Rate" 6 \
#"Enable Outputs (Output Events)" 6 \
SIM_MODEL_PROPERTIES = ""
top/b200/S6CLK2PIN.v
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module S6CLK2PIN
(
input I,
output O
);
ODDR2 #(
.DDR_ALIGNMENT("NONE"), // to "NONE", "C0" or "C1"
.INIT(1'b0), // output to 1'b0 or 1'b1
.SRTYPE("ASYNC")) // set/reset "SYNC" or "ASYNC"
ODDR2_S6CLK2PIN
(
.Q(O), // 1-bit DDR output data
.C0(I), // 1-bit clock input
.C1(~I), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b1), // 1-bit data input (associated with C0)
.D1(1'b0), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) );// 1-bit set input
endmodule //S6CLK2PIN
top/b200/b200.ucf
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## SPI Nets
NET "cat_ce" LOC = "Y1" | IOSTANDARD = LVCMOS18;
NET "cat_miso" LOC = "V1" | IOSTANDARD = LVCMOS18;
NET "cat_mosi" LOC = "T4" | IOSTANDARD = LVCMOS18;
NET "cat_sclk" LOC = "P7" | IOSTANDARD = LVCMOS18;
NET "fx3_ce" LOC = "H20" | IOSTANDARD = LVCMOS18 ;
NET "fx3_miso" LOC = "G20" | IOSTANDARD = LVCMOS18 ;
NET "fx3_mosi" LOC = "AA20" | IOSTANDARD = LVCMOS18 ;
#NET "fx3_mosi" LOC = "A9" | IOSTANDARD = LVCMOS33 ;
NET "fx3_sclk" LOC = "Y21" | IOSTANDARD = LVCMOS18 ;
NET "pll_ce" LOC = "W11" | IOSTANDARD = LVCMOS18 ;
NET "pll_mosi" LOC = "AB11" | IOSTANDARD = LVCMOS18 ;
NET "pll_sclk" LOC = "Y12" | IOSTANDARD = LVCMOS18 ;
## UART header not always connected so has pullups. Can also be GPIO as build option.
NET "FPGA_RXD0" LOC = "AB8" | IOSTANDARD = LVCMOS18 | PULLUP ;
NET "FPGA_TXD0" LOC = "AB7" | IOSTANDARD = LVCMOS18 | PULLUP ;
## Catalina Controls
NET "codec_enable" LOC = "J6" | IOSTANDARD = LVCMOS18;
NET "codec_en_agc" LOC = "P6" | IOSTANDARD = LVCMOS18;
NET "codec_reset" LOC = "Y2" | IOSTANDARD = LVCMOS18;
NET "codec_sync" LOC = "M3" | IOSTANDARD = LVCMOS18;
NET "codec_txrx" LOC = "M7" | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_in<0>" LOC = "E3" | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_in<1>" LOC = "F2" | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_in<2>" LOC = "F1" | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_in<3>" LOC = "E1" | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_out<0>" LOC = "D1" | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_out<1>" LOC = "C1" | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_out<2>" LOC = "H3" | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_out<3>" LOC = "F3" | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_out<4>" LOC = "P1" | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_out<5>" LOC = "J1" | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_out<6>" LOC = "B1" | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_out<7>" LOC = "H2" | IOSTANDARD = LVCMOS18;
## Catalina Data TX
NET "tx_codec_d<0>" LOC = "T2" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<1>" LOC = "R1" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<2>" LOC = "V2" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<3>" LOC = "N1" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<4>" LOC = "V3" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<5>" LOC = "T1" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<6>" LOC = "W1" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<7>" LOC = "U1" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<8>" LOC = "W3" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<9>" LOC = "U3" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<10>" LOC = "P2" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<11>" LOC = "R3" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d*" DRIVE = 2;
## Catalina Data RX
NET "rx_codec_d<0>" LOC = "M1" | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<1>" LOC = "K1" | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<2>" LOC = "K2" | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<3>" LOC = "G3" | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<4>" LOC = "M2" | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<5>" LOC = "J4" | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<6>" LOC = "L3" | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<7>" LOC = "H1" | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<8>" LOC = "L4" | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<9>" LOC = "G1" | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<10>" LOC = "N3" | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<11>" LOC = "M4" | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d*" DRIVE = 2;
## Catalina Clocks
NET "cat_clkout_fpga" LOC = "J3" | IOSTANDARD = LVCMOS18;
NET "codec_data_clk_p" LOC = "K3" | IOSTANDARD = LVCMOS18;
NET "codec_fb_clk_p" LOC = "P3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 ;
NET "codec_main_clk_p" LOC = "K5" | IOSTANDARD = LVDS_25;
NET "codec_main_clk_n" LOC = "K4" | IOSTANDARD = LVDS_25;
NET "rx_frame_p" LOC = "U4" | IOSTANDARD = LVCMOS18;
NET "tx_frame_p" LOC = "T3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 ;
## Debug Bus
NET "debug<0>" LOC = "D10" | IOSTANDARD = LVCMOS33 ;
NET "debug<1>" LOC = "D9" | IOSTANDARD = LVCMOS33 ;
NET "debug<2>" LOC = "A8" | IOSTANDARD = LVCMOS33 ;
NET "debug<3>" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
NET "debug<4>" LOC = "C8" | IOSTANDARD = LVCMOS33 ;
NET "debug<5>" LOC = "D8" | IOSTANDARD = LVCMOS33 ;
NET "debug<6>" LOC = "A7" | IOSTANDARD = LVCMOS33 ;
NET "debug<7>" LOC = "D7" | IOSTANDARD = LVCMOS33 ;
NET "debug<8>" LOC = "A6" | IOSTANDARD = LVCMOS33 ;
NET "debug<9>" LOC = "B6" | IOSTANDARD = LVCMOS33 ;
NET "debug<10>" LOC = "C6" | IOSTANDARD = LVCMOS33 ;
NET "debug<11>" LOC = "D6" | IOSTANDARD = LVCMOS33 ;
NET "debug<12>" LOC = "A5" | IOSTANDARD = LVCMOS33 ;
NET "debug<13>" LOC = "A4" | IOSTANDARD = LVCMOS33 ;
NET "debug<14>" LOC = "C5" | IOSTANDARD = LVCMOS33 ;
NET "debug<15>" LOC = "A3" | IOSTANDARD = LVCMOS33 ;
NET "debug<16>" LOC = "A18" | IOSTANDARD = LVCMOS33 ;
NET "debug<17>" LOC = "B18" | IOSTANDARD = LVCMOS33 ;
NET "debug<18>" LOC = "A17" | IOSTANDARD = LVCMOS33 ;
NET "debug<19>" LOC = "C17" | IOSTANDARD = LVCMOS33 ;
NET "debug<20>" LOC = "C14" | IOSTANDARD = LVCMOS33 ;
NET "debug<21>" LOC = "D12" | IOSTANDARD = LVCMOS33 ;
NET "debug<22>" LOC = "C10" | IOSTANDARD = LVCMOS33 ;
NET "debug<23>" LOC = "F15" | IOSTANDARD = LVCMOS33 ;
NET "debug<24>" LOC = "E14" | IOSTANDARD = LVCMOS33 ;
NET "debug<25>" LOC = "F14" | IOSTANDARD = LVCMOS33 ;
NET "debug<26>" LOC = "H14" | IOSTANDARD = LVCMOS33 ;
NET "debug<27>" LOC = "D13" | IOSTANDARD = LVCMOS33 ;
NET "debug<28>" LOC = "F13" | IOSTANDARD = LVCMOS33 ;
NET "debug<29>" LOC = "G13" | IOSTANDARD = LVCMOS33 ;
NET "debug<30>" LOC = "E12" | IOSTANDARD = LVCMOS33 ;
NET "debug<31>" LOC = "H13" | IOSTANDARD = LVCMOS33 ;
NET "debug_clk<0>" LOC = "A12" | IOSTANDARD = LVCMOS33 ;
NET "debug_clk<1>" LOC = "C12" | IOSTANDARD = LVCMOS33 ;
NET "debug*" DRIVE = 2;
## GPIF
NET "IFCLK" LOC = "H21" | IOSTANDARD = LVCMOS18 ;
NET "FX3_EXTINT" LOC = "U20" | IOSTANDARD = LVCMOS18 ;
NET "IFCLK" DRIVE = 8;
NET "IFCLK" SLEW = SLOW;
NET "GPIF_CTL0" LOC = "P22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL1" LOC = "N22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL2" LOC = "AA18" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL3" LOC = "AB18" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL4" LOC = "P19" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL5" LOC = "AA2" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL6" LOC = "M22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL7" LOC = "AB19" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL8" LOC = "M19" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL9" LOC = "R20" | IOSTANDARD = LVCMOS18 ;
##GPIF_CTL10 is "FPGA_CFG_DONE", defined later.
NET "GPIF_CTL11" LOC = "M21" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL12" LOC = "M20" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<0>" LOC = "T17" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<1>" LOC = "U14" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<2>" LOC = "U13" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<3>" LOC = "AA6" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<4>" LOC = "AB6" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<5>" LOC = "Y3" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<6>" LOC = "AB3" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<7>" LOC = "AA4" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<8>" LOC = "V20" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<9>" LOC = "AB2" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<10>" LOC = "V21" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<11>" LOC = "T22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<12>" LOC = "U22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<13>" LOC = "R22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<14>" LOC = "AA12" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<15>" LOC = "AB12" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<16>" LOC = "Y13" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<17>" LOC = "N20" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<18>" LOC = "T21" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<19>" LOC = "K18" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<20>" LOC = "H22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<21>" LOC = "J20" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<22>" LOC = "K19" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<23>" LOC = "L19" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<24>" LOC = "N19" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<25>" LOC = "K22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<26>" LOC = "L22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<27>" LOC = "L20" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<28>" LOC = "J22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<29>" LOC = "K20" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<30>" LOC = "G22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<31>" LOC = "F22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_*" DRIVE = 2;
NET "GPIF_*" SLEW = SLOW;
## GPS
NET "gps_lock" LOC = "B14" | IOSTANDARD = LVCMOS33 ;
NET "gps_rxd" LOC = "A15" | IOSTANDARD = LVCMOS33 ;
NET "gps_txd" LOC = "A14" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "gps_txd_nmea" LOC = "C15" | IOSTANDARD = LVCMOS33 | PULLUP ;
## LEDS
NET "LED_RX1" LOC = "C22" | IOSTANDARD = LVCMOS18 ;
NET "LED_RX2" LOC = "L15" | IOSTANDARD = LVCMOS18 ;
NET "LED_TXRX1_TX" LOC = "C20" | IOSTANDARD = LVCMOS18 ;
NET "LED_TXRX2_RX" LOC = "D21" | IOSTANDARD = LVCMOS18 ;
NET "LED_TXRX1_RX" LOC = "K16" | IOSTANDARD = LVCMOS18 ;
NET "LED_TXRX2_TX" LOC = "D22" | IOSTANDARD = LVCMOS18 ;
## Misc Hardware Control
NET "ref_sel" LOC = "AA14" | IOSTANDARD = LVCMOS18 ;
NET "pll_lock" LOC = "AB10" | IOSTANDARD = LVCMOS18 ;
NET "AUX_PWR_ON" LOC = "B16" | IOSTANDARD = LVCMOS33 ;
#NET "RFUSE" LOC = "P15" | IOSTANDARD = LVCMOS33 ;
## PPS
NET "PPS_IN_EXT" LOC = "B10" | IOSTANDARD = LVCMOS33 ;
NET "PPS_IN_INT" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
## RF Hardware Control
NET "SFDX1_RX" LOC = "A16" | IOSTANDARD = LVCMOS33 ;
NET "SFDX1_TX" LOC = "D14" | IOSTANDARD = LVCMOS33 ;
NET "SFDX2_RX" LOC = "C11" | IOSTANDARD = LVCMOS33 ;
NET "SFDX2_TX" LOC = "A11" | IOSTANDARD = LVCMOS33 ;
NET "SRX1_RX" LOC = "D15" | IOSTANDARD = LVCMOS33 ;
NET "SRX1_TX" LOC = "C16" | IOSTANDARD = LVCMOS33 ;
NET "SRX2_RX" LOC = "B12" | IOSTANDARD = LVCMOS33 ;
NET "SRX2_TX" LOC = "D11" | IOSTANDARD = LVCMOS33 ;
NET "tx_bandsel_a" LOC = "C13" | IOSTANDARD = LVCMOS33 ;
NET "tx_bandsel_b" LOC = "D17" | IOSTANDARD = LVCMOS33 ;
NET "tx_enable1" LOC = "Y4" | IOSTANDARD = LVCMOS18 ;
NET "tx_enable2" LOC = "R19" | IOSTANDARD = LVCMOS18 ;
NET "rx_bandsel_a" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "rx_bandsel_b" LOC = "A13" | IOSTANDARD = LVCMOS33 ;
NET "rx_bandsel_c" LOC = "E16" | IOSTANDARD = LVCMOS33 ;
## FPGA Config Pins
#NET "FPGA_CFG_INIT_B" LOC = "T6" | IOSTANDARD = LVCMOS18 ;
#NET "FPGA_CFG_DONE" LOC = "Y22" | IOSTANDARD = LVCMOS18 ;
#NET "FPGA_CFG_M0" LOC = "AA22" | IOSTANDARD = LVCMOS18 ;
#NET "FPGA_CFG_M1" LOC = "U15" | IOSTANDARD = LVCMOS18 ;
#NET "FPGA_CFG_PROG_B" LOC = "AA1" | IOSTANDARD = LVCMOS18 ;
## Special Pins
#NET "VFS" LOC = "P16" | IOSTANDARD = LVCMOS33 ;
#NET "TMS" LOC = "C18" | IOSTANDARD = LVCMOS33 ;
#NET "TDO" LOC = "A19" | IOSTANDARD = LVCMOS33 ;
#NET "TDI" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
#NET "TCK" LOC = "G15" | IOSTANDARD = LVCMOS33 ;
#NET "GND" LOC = "N15" | IOSTANDARD = LVCMOS33 ;
top/b200/b200.v
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//
// Copyright 2013 Ettus Research LLC
// Copyright 2017 Ettus Research, a National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
/***********************************************************
* B200 Module Declaration
**********************************************************/
module b200 (
// SPI Interfaces
output cat_ce,
input cat_miso,
output cat_mosi,
output cat_sclk,
input fx3_ce,
output fx3_miso,
input fx3_mosi,
input fx3_sclk,
output pll_ce,
output pll_mosi,
output pll_sclk,
// UART
// By default these provide an FX3 UART console output. Under compile time control they can alternatively
// provide 2 (1.8V) GPIO pins which are logically bits [9:8] of the fp_gpio bus.
// Used as a UART RXD is an input and TXD an output electrically.
// input FPGA_RXD0, // These pins goto 3 pin 0.1" header on B2x0 and
// output FPGA_TXD0, // carry FX3 UART.
inout FPGA_RXD0, // These pins goto 3 pin 0.1" header J400 on B2x0 and
inout FPGA_TXD0, // carry FX3 UART.
// Catalina Controls
output codec_enable,
output codec_en_agc,
output codec_reset,
output codec_sync,
output codec_txrx,
output [3:0] codec_ctrl_in, // These should be outputs
input [7:0] codec_ctrl_out, // MUST BE INPUT
// Catalina Data
input codec_data_clk_p, // Clock from CAT (RX)
output codec_fb_clk_p, // Clock to CAT (TX)
input [11:0] rx_codec_d,
output [11:0] tx_codec_d,
input rx_frame_p,
output tx_frame_p,
input cat_clkout_fpga,
//always on 40MHz clock
input codec_main_clk_p,
input codec_main_clk_n,
// Debug Bus
output [31:0] debug,
output [1:0] debug_clk,
// GPIF, FX3 Slave FIFO
output IFCLK, // pclk
input FX3_EXTINT,
output GPIF_CTL0, // n_slcs
output GPIF_CTL1, // n_slwr
output GPIF_CTL2, // n_sloe
output GPIF_CTL3, // n_slrd
output GPIF_CTL7, // n_pktend
input GPIF_CTL4, // slfifo_flags[0]
input GPIF_CTL5, // slfifo_flags[1]
input GPIF_CTL6, // Serial settings bus from FX3. SDA
input GPIF_CTL8, // Serial settings bus from FX3. SCL
output GPIF_CTL11, // slfifo_addr[1]
output GPIF_CTL12, // slfifo_addr[0]
inout [31:0] GPIF_D,
input GPIF_CTL9, // global_reset
// GPS
input gps_lock,
output gps_rxd,
input gps_txd, // FPGA has pullup for unpopulated GPS
input gps_txd_nmea, // FPGA has pullup for unpopulated GPS
// LEDS
output LED_RX1,
output LED_RX2,
output LED_TXRX1_RX,
output LED_TXRX1_TX,
output LED_TXRX2_RX,
output LED_TXRX2_TX,
// GPIO Header J504 - 10 pin 0.1" 3.3V.
// Only present on Rev6 and later boards...these pins unused on Rev5 and earlier.
// NOTE: These pins are allocated from complimentry pairs and could potentially be used
// as differential style I/O.
`ifdef TARGET_B210
inout [7:0] fp_gpio,
`endif
// Misc Hardware Control
output ref_sel,
input pll_lock,
input FPGA_CFG_CS, // Driven by FX3 gpio.
input AUX_PWR_ON, // Driven by FX3 gpio.
// PPS
input PPS_IN_EXT,
input PPS_IN_INT,
// RF Hardware Control
output SFDX1_RX,
output SFDX1_TX,
output SFDX2_RX,
output SFDX2_TX,
output SRX1_RX,
output SRX1_TX,
output SRX2_RX,
output SRX2_TX,
output tx_bandsel_a,
output tx_bandsel_b,
output tx_enable1,
output tx_enable2,
output rx_bandsel_a,
output rx_bandsel_b,
output rx_bandsel_c
);
wire reset_global = GPIF_CTL9;
///////////////////////////////////////////////////////////////////////
// generate clocks from always on codec main clk
///////////////////////////////////////////////////////////////////////
wire bus_clk, gpif_clk, radio_clk;
wire locked;
b200_clk_gen gen_clks
(
.CLK_IN1_40_P(codec_main_clk_p), .CLK_IN1_40_N(codec_main_clk_n),
.CLK_OUT1_40_int(), .CLK_OUT2_100_gpif(gpif_clk), .CLK_OUT3_100_bus(),
.RESET(reset_global), .LOCKED(locked)
);
// Bus Clock and GPIF Clock both same 100MHz clock.
assign bus_clk = gpif_clk;
//hold-off logic for clocks ready
reg [15:0] clocks_ready_count;
reg clocks_ready;
always @(posedge bus_clk or posedge reset_global or negedge locked) begin
if (reset_global | !locked) begin
clocks_ready_count <= 16'b0;
clocks_ready <= 1'b0;
end
else if (!clocks_ready) begin
clocks_ready_count <= clocks_ready_count + 1'b1;
clocks_ready <= (clocks_ready_count == 16'hffff);
end
end
///////////////////////////////////////////////////////////////////////
// drive output clocks
///////////////////////////////////////////////////////////////////////
wire [1:0] debug_clk_int;
//S6CLK2PIN S6CLK2PIN_dbg0 (.I(debug_clk_int[0]), .O(debug_clk[0]));
//S6CLK2PIN S6CLK2PIN_dbg1 (.I(debug_clk_int[1]), .O(debug_clk[1]));
assign debug_clk[1:0] = 2'b0;
S6CLK2PIN S6CLK2PIN_gpif (.I(gpif_clk), .O(IFCLK));
///////////////////////////////////////////////////////////////////////
// Create sync reset signals
///////////////////////////////////////////////////////////////////////
wire gpif_rst, bus_rst, radio_rst;
reset_sync gpif_sync(.clk(gpif_clk), .reset_in(!clocks_ready), .reset_out(gpif_rst));
reset_sync bus_sync(.clk(bus_clk), .reset_in(!clocks_ready), .reset_out(bus_rst));
reset_sync radio_sync(.clk(radio_clk), .reset_in(!clocks_ready), .reset_out(radio_rst));
///////////////////////////////////////////////////////////////////////
// I/O
///////////////////////////////////////////////////////////////////////
wire [31:0] rx_data0, rx_data1;
wire [31:0] tx_data0, tx_data1;
wire mimo;
b200_io b200_io_i0
(
.reset(reset),
.mimo(mimo),
// Baseband sample interface
.radio_clk(radio_clk),
.rx_i0(rx_data0[31:20]),
.rx_q0(rx_data0[15:4]),
.rx_i1(rx_data1[31:20]),
.rx_q1(rx_data1[15:4]),
.tx_i0(tx_data0[31:20]),
.tx_q0(tx_data0[15:4]),
.tx_i1(tx_data1[31:20]),
.tx_q1(tx_data1[15:4]),
// Catalina interface
.rx_clk(codec_data_clk_p),
.rx_frame(rx_frame_p),
.rx_data(rx_codec_d),
.tx_clk(codec_fb_clk_p),
.tx_frame(tx_frame_p),
.tx_data(tx_codec_d)
);
assign {rx_data0[19:16],rx_data0[3:0],rx_data1[19:16],rx_data1[3:0]} = 16'h0;
///////////////////////////////////////////////////////////////////////
// SPI connections
///////////////////////////////////////////////////////////////////////
wire mosi, miso, sclk;
wire [7:0] sen;
//AD9361 Slave
assign cat_ce = sen[0];
assign cat_mosi = ~sen[0] & mosi;
assign cat_sclk = ~sen[0] & sclk;
assign miso = cat_miso; //PLL does not have a miso
//ADF4001 Slave
assign pll_ce = sen[1];
assign pll_mosi = ~sen[1] & mosi;
assign pll_sclk = ~sen[1] & sclk;
//FX3 Master
//The following signals are routed to the FX3 and were used by an obsolete
//bit-banging SPI engine.
// fx3_ce, fx3_sclk, fx3_mosi <Unused>
assign fx3_miso = 1'bZ; //Safe state because we cannot guarantee the
//direction of this pin in the FX3
///////////////////////////////////////////////////////////////////////
// bus signals
///////////////////////////////////////////////////////////////////////
wire [63:0] ctrl_tdata, resp_tdata, rx_tdata, tx_tdata;
wire ctrl_tlast, resp_tlast, rx_tlast, tx_tlast;
wire ctrl_tvalid, resp_tvalid, rx_tvalid, tx_tvalid;
wire ctrl_tready, resp_tready, rx_tready, tx_tready;
///////////////////////////////////////////////////////////////////////
// frontend assignments
// Most B2x0's have frontends swapped (radio0 to FE2), but some hardware revisions do not.
// The ATR pins are mapped from radio to frontend here based on the swap_atr_n bit.
///////////////////////////////////////////////////////////////////////
wire swap_atr_n;
wire [7:0] radio0_gpio, radio1_gpio;
reg [7:0] fe0_gpio, fe1_gpio;
always @(posedge radio_clk) begin //Registers in the IOB
fe0_gpio <= swap_atr_n ? radio1_gpio : radio0_gpio;
fe1_gpio <= swap_atr_n ? radio0_gpio : radio1_gpio;
end
assign {tx_enable1, SFDX1_RX, SFDX1_TX, SRX1_RX, SRX1_TX, LED_RX1, LED_TXRX1_RX, LED_TXRX1_TX} = fe0_gpio;
assign {tx_enable2, SFDX2_RX, SFDX2_TX, SRX2_RX, SRX2_TX, LED_RX2, LED_TXRX2_RX, LED_TXRX2_TX} = fe1_gpio;
wire [31:0] misc_outs; reg [31:0] misc_outs_r;
always @(posedge bus_clk) misc_outs_r <= misc_outs; //register misc ios to ease routing to flop
wire codec_arst;
assign { swap_atr_n, tx_bandsel_a, tx_bandsel_b, rx_bandsel_a, rx_bandsel_b, rx_bandsel_c, codec_arst, mimo, ref_sel } = misc_outs_r[8:0];
assign codec_ctrl_in = 4'b1;
assign codec_en_agc = 1'b1;
assign codec_txrx = 1'b1;
assign codec_enable = 1'b1;
assign codec_reset = ~codec_arst; // Codec Reset // RESETB // Operates active-low
assign codec_sync = 1'b0;
///////////////////////////////////////////////////////////////////////
// b200 core
///////////////////////////////////////////////////////////////////////
wire [9:0] fp_gpio_in, fp_gpio_out, fp_gpio_ddr;
b200_core #(.EXTRA_BUFF_SIZE(12)) b200_core
(
.bus_clk(bus_clk), .bus_rst(bus_rst),
.tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
.rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready),
.ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast), .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready),
.resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready),
.radio_clk(radio_clk), .radio_rst(radio_rst),
.rx0(rx_data0), .rx1(rx_data1),
.tx0(tx_data0), .tx1(tx_data1),
.fe0_gpio_out(radio0_gpio), .fe1_gpio_out(radio1_gpio),
.fp_gpio_in(fp_gpio_in), .fp_gpio_out(fp_gpio_out), .fp_gpio_ddr(fp_gpio_ddr),
.pps_int(PPS_IN_INT), .pps_ext(PPS_IN_EXT),
.rxd(gps_txd), .txd(gps_rxd),
.sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso),
.rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs),
.debug_scl(GPIF_CTL8), .debug_sda(GPIF_CTL6),
`ifdef DEBUG_UART
.debug_txd(FPGA_TXD0), .debug_rxd(FPGA_RXD0),
`else
.debug_txd(), .debug_rxd(1'b0),
`endif
.lock_signals(codec_ctrl_out[7:6]),
.debug()
);
`ifdef TARGET_B210
`ifdef DEBUG_UART
gpio_atr_io #(.WIDTH(8)) gpio_atr_io_inst ( // B210 with UART
.clk(radio_clk), .gpio_pins(fp_gpio),
.gpio_ddr(fp_gpio_ddr[7:0]), .gpio_out(fp_gpio_out[7:0]), .gpio_in(fp_gpio_in[7:0])
);
assign fp_gpio_in[9:8] = 2'b00;
`else
gpio_atr_io #(.WIDTH(10)) gpio_atr_io_inst ( // B210 no UART
.clk(radio_clk), .gpio_pins({FPGA_RXD0, FPGA_TXD0, fp_gpio}),
.gpio_ddr(fp_gpio_ddr), .gpio_out(fp_gpio_out), .gpio_in(fp_gpio_in)
);
`endif
`else
`ifdef DEBUG_UART
assign fp_gpio_in = 10'h000; // B200 with UART
`else
gpio_atr_io #(.WIDTH(2)) gpio_atr_io_inst ( // B200 no UART
.clk(radio_clk), .gpio_pins({FPGA_RXD0, FPGA_TXD0}),
.gpio_ddr(fp_gpio_ddr[9:8]), .gpio_out(fp_gpio_out[9:8]), .gpio_in(fp_gpio_in[9:8])
);
assign fp_gpio_in[7:0] = 8'h00;
`endif
`endif
///////////////////////////////////////////////////////////////////////
// GPIF2
///////////////////////////////////////////////////////////////////////
gpif2_slave_fifo32 #(.DATA_RX_FIFO_SIZE(13), .DATA_TX_FIFO_SIZE(13)) slave_fifo32
(
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_enb(1'b1),
.gpif_ctl({GPIF_CTL8, GPIF_CTL6, GPIF_CTL5, GPIF_CTL4}), .fifoadr({GPIF_CTL11,GPIF_CTL12}),
.slwr(GPIF_CTL1), .sloe(GPIF_CTL2), .slcs(GPIF_CTL0), .slrd(GPIF_CTL3), .pktend(GPIF_CTL7),
.gpif_d(GPIF_D),
.fifo_clk(bus_clk), .fifo_rst(bus_rst),
.tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
.rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready),
.ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast), .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready),
.resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready),
.debug()
);
///////////////////////////////////////////////////////////////////////
// Debug port
///////////////////////////////////////////////////////////////////////
assign debug = 0;
endmodule // B200
top/b200/b200_core.v
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//
// Copyright 2013 Ettus Research LLC
// Copyright 2017 Ettus Research, a National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
/***********************************************************
* B200 Core Guts
**********************************************************/
module b200_core
#(
parameter R0_CTRL_SID = 8'h10,
parameter R1_CTRL_SID = 8'h20,
parameter U0_CTRL_SID = 8'h30,
parameter L0_CTRL_SID = 8'h40,
parameter R0_DATA_SID = 8'h50,
parameter R1_DATA_SID = 8'h60,
parameter DEMUX_SID_MASK = 8'hf0,
parameter EXTRA_BUFF_SIZE = 0,
parameter RADIO_FIFO_SIZE = 11,
parameter SAMPLE_FIFO_SIZE = 11
)
(
////////////////////////////////////////////////////////////////////
// bus interfaces
////////////////////////////////////////////////////////////////////
input bus_clk,
input bus_rst,
input [63:0] tx_tdata, input tx_tlast, input tx_tvalid, output tx_tready,
output [63:0] rx_tdata, output rx_tlast, output rx_tvalid, input rx_tready,
input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output ctrl_tready,
output [63:0] resp_tdata, output resp_tlast, output resp_tvalid, input resp_tready,
////////////////////////////////////////////////////////////////////
// radio interfaces
////////////////////////////////////////////////////////////////////
input radio_clk,
input radio_rst,
input [31:0] rx0, input [31:0] rx1,
output [31:0] tx0, output [31:0] tx1,
output [7:0] fe0_gpio_out, output [7:0] fe1_gpio_out,
input [9:0] fp_gpio_in, output [9:0] fp_gpio_out, output [9:0] fp_gpio_ddr,
input pps_int, input pps_ext,
////////////////////////////////////////////////////////////////////
// gpsdo uart
////////////////////////////////////////////////////////////////////
input rxd,
output txd,
////////////////////////////////////////////////////////////////////
// core interfaces
////////////////////////////////////////////////////////////////////
output [7:0] sen, output sclk, output mosi, input miso,
input [31:0] rb_misc,
output [31:0] misc_outs,
////////////////////////////////////////////////////////////////////
// debug UART
////////////////////////////////////////////////////////////////////
output debug_txd, input debug_rxd,
input debug_scl, input debug_sda,
////////////////////////////////////////////////////////////////////
// fe lock signals
////////////////////////////////////////////////////////////////////
input [1:0] lock_signals,
////////////////////////////////////////////////////////////////////
// debug signals
////////////////////////////////////////////////////////////////////
output [63:0] debug
);
localparam SR_CORE_SPI = 8'd8;
localparam SR_CORE_MISC = 8'd16;
localparam SR_CORE_COMPAT = 8'd24;
localparam SR_CORE_READBACK = 8'd32;
localparam SR_CORE_GPSDO_ST = 8'd40;
localparam SR_CORE_SYNC = 8'd48;
localparam COMPAT_MAJOR = 16'h0010;
localparam COMPAT_MINOR = 16'h0000;
reg [1:0] lock_state;
reg [1:0] lock_state_r;
always @(posedge bus_clk)
if (bus_rst)
{lock_state_r, lock_state} <= 4'h0;
else
{lock_state_r, lock_state} <= {lock_state, lock_signals};
/*******************************************************************
* PPS Timing stuff
******************************************************************/
// Generate an internal PPS signal
wire int_pps;
pps_generator #(.CLK_FREQ(100000000)) pps_gen
(.clk(bus_clk), .reset(1'b0), .pps(int_pps));
// Flop PPS signals into radio clock domain
reg [1:0] gpsdo_pps_del, ext_pps_del, int_pps_del;
always @(posedge radio_clk) ext_pps_del[1:0] <= {ext_pps_del[0], pps_ext};
always @(posedge radio_clk) gpsdo_pps_del[1:0] <= {gpsdo_pps_del[0], pps_int};
always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], int_pps};
// PPS mux
wire [1:0] pps_select;
wire pps = (pps_select == 2'b00)? gpsdo_pps_del[1] :
(pps_select == 2'b01)? ext_pps_del[1] :
(pps_select == 2'b10)? int_pps_del[1] :
1'b0;
/*******************************************************************
* Response mux Routing logic
******************************************************************/
wire [63:0] r0_resp_tdata; wire r0_resp_tlast, r0_resp_tvalid, r0_resp_tready;
wire [63:0] r1_resp_tdata; wire r1_resp_tlast, r1_resp_tvalid, r1_resp_tready;
wire [63:0] u0_resp_tdata; wire u0_resp_tlast, u0_resp_tvalid, u0_resp_tready;
wire [63:0] l0_resp_tdata; wire l0_resp_tlast, l0_resp_tvalid, l0_resp_tready;
axi_mux4 #(.WIDTH(64), .BUFFER(1)) mux_for_resp
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i0_tdata(r0_resp_tdata), .i0_tlast(r0_resp_tlast), .i0_tvalid(r0_resp_tvalid), .i0_tready(r0_resp_tready),
.i1_tdata(r1_resp_tdata), .i1_tlast(r1_resp_tlast), .i1_tvalid(r1_resp_tvalid), .i1_tready(r1_resp_tready),
.i2_tdata(u0_resp_tdata), .i2_tlast(u0_resp_tlast), .i2_tvalid(u0_resp_tvalid), .i2_tready(u0_resp_tready),
.i3_tdata(l0_resp_tdata), .i3_tlast(l0_resp_tlast), .i3_tvalid(l0_resp_tvalid), .i3_tready(l0_resp_tready),
.o_tdata(resp_tdata), .o_tlast(resp_tlast), .o_tvalid(resp_tvalid), .o_tready(resp_tready));
/*******************************************************************
* Control demux Routing logic
******************************************************************/
wire [63:0] r0_ctrl_tdata; wire r0_ctrl_tlast, r0_ctrl_tvalid, r0_ctrl_tready;
wire [63:0] r1_ctrl_tdata; wire r1_ctrl_tlast, r1_ctrl_tvalid, r1_ctrl_tready;
wire [63:0] u0_ctrl_tdata; wire u0_ctrl_tlast, u0_ctrl_tvalid, u0_ctrl_tready;
wire [63:0] l0_ctrl_tdata; wire l0_ctrl_tlast, l0_ctrl_tvalid, l0_ctrl_tready;
wire [63:0] ctrl_hdr;
wire [1:0] ctrl_dst =
((ctrl_hdr[7:0] & DEMUX_SID_MASK) == R0_CTRL_SID)? 0 : (
((ctrl_hdr[7:0] & DEMUX_SID_MASK) == R1_CTRL_SID)? 1 : (
((ctrl_hdr[7:0] & DEMUX_SID_MASK) == U0_CTRL_SID)? 2 : (
((ctrl_hdr[7:0] & DEMUX_SID_MASK) == L0_CTRL_SID)? 3 : (
3))));
axi_demux4 #(.ACTIVE_CHAN(4'b1111), .WIDTH(64), .BUFFER(1)) demux_for_ctrl
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.header(ctrl_hdr), .dest(ctrl_dst),
.i_tdata(ctrl_tdata), .i_tlast(ctrl_tlast), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready),
.o0_tdata(r0_ctrl_tdata), .o0_tlast(r0_ctrl_tlast), .o0_tvalid(r0_ctrl_tvalid), .o0_tready(r0_ctrl_tready),
.o1_tdata(r1_ctrl_tdata), .o1_tlast(r1_ctrl_tlast), .o1_tvalid(r1_ctrl_tvalid), .o1_tready(r1_ctrl_tready),
.o2_tdata(u0_ctrl_tdata), .o2_tlast(u0_ctrl_tlast), .o2_tvalid(u0_ctrl_tvalid), .o2_tready(u0_ctrl_tready),
.o3_tdata(l0_ctrl_tdata), .o3_tlast(l0_ctrl_tlast), .o3_tvalid(l0_ctrl_tvalid), .o3_tready(l0_ctrl_tready));
/*******************************************************************
* UART
******************************************************************/
wire [63:0] u0i_ctrl_tdata; wire u0i_ctrl_tlast, u0i_ctrl_tvalid, u0i_ctrl_tready;
axi_fifo #(.WIDTH(65), .SIZE(5)) uart_timing_fifo
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({u0_ctrl_tlast, u0_ctrl_tdata}), .i_tvalid(u0_ctrl_tvalid), .i_tready(u0_ctrl_tready), .space(),
.o_tdata({u0i_ctrl_tlast, u0i_ctrl_tdata}), .o_tvalid(u0i_ctrl_tvalid), .o_tready(u0i_ctrl_tready), .occupied()
);
cvita_uart #(.SIZE(7)) uart
(
.clk(bus_clk), .rst(bus_rst), .rxd(rxd), .txd(txd),
.i_tdata(u0i_ctrl_tdata), .i_tlast(u0i_ctrl_tlast), .i_tvalid(u0i_ctrl_tvalid), .i_tready(u0i_ctrl_tready),
.o_tdata(u0_resp_tdata), .o_tlast(u0_resp_tlast), .o_tvalid(u0_resp_tvalid), .o_tready(u0_resp_tready)
);
/*******************************************************************
* Misc controls
******************************************************************/
wire set_stb;
wire [7:0] set_addr;
wire [31:0] set_data;
wire spi_ready;
wire [31:0] spi_readback;
wire [7:0] gpsdo_st;
wire [7:0] radio_st;
wire [1:0] rb_addr;
reg [63:0] rb_data;
wire [63:0] l0i_ctrl_tdata; wire l0i_ctrl_tlast, l0i_ctrl_tvalid, l0i_ctrl_tready;
wire time_sync, time_sync_r;
axi_fifo #(.WIDTH(65), .SIZE(5)) radio_ctrl_proc_timing_fifo
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({l0_ctrl_tlast, l0_ctrl_tdata}), .i_tvalid(l0_ctrl_tvalid), .i_tready(l0_ctrl_tready), .space(),
.o_tdata({l0i_ctrl_tlast, l0i_ctrl_tdata}), .o_tvalid(l0i_ctrl_tvalid), .o_tready(l0i_ctrl_tready), .occupied()
);
radio_ctrl_proc radio_ctrl_proc
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.ctrl_tdata(l0i_ctrl_tdata), .ctrl_tlast(l0i_ctrl_tlast), .ctrl_tvalid(l0i_ctrl_tvalid), .ctrl_tready(l0i_ctrl_tready),
.resp_tdata(l0_resp_tdata), .resp_tlast(l0_resp_tlast), .resp_tvalid(l0_resp_tvalid), .resp_tready(l0_resp_tready),
.vita_time(64'b0),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.ready(spi_ready), .readback(rb_data),
.debug());
setting_reg #(.my_addr(SR_CORE_MISC), .awidth(8), .width(32), .at_reset(8'h0)) sr_misc
(.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(misc_outs), .changed());
setting_reg #(.my_addr(SR_CORE_READBACK), .awidth(8), .width(2)) sr_rdback
(.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(rb_addr), .changed());
setting_reg #(.my_addr(SR_CORE_GPSDO_ST), .awidth(8), .width(8)) sr_gpsdo_st
(.clk(bus_clk), .rst(1'b0/*keep*/), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(gpsdo_st), .changed());
setting_reg #(.my_addr(SR_CORE_SYNC), .awidth(8), .width(3)) sr_sync
(.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out({time_sync,pps_select}), .changed());
synchronizer time_sync_synchronizer
(.clk(radio_clk), .rst(radio_rst), .in(time_sync), .out(time_sync_r));
simple_spi_core #(.BASE(SR_CORE_SPI), .WIDTH(8), .CLK_IDLE(0), .SEN_IDLE(8'hFF)) misc_spi
(.clock(bus_clk), .reset(bus_rst),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.readback(spi_readback), .ready(spi_ready),
.sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso),
.debug());
always @*
case(rb_addr)
2'd0 : rb_data <= { 32'hACE0BA5E, COMPAT_MAJOR, COMPAT_MINOR };
2'd1 : rb_data <= { 32'b0, spi_readback };
2'd2 : rb_data <= { 16'b0, radio_st, gpsdo_st, rb_misc };
2'd3 : rb_data <= { 30'h0, lock_state_r };
default : rb_data <= 64'd0;
endcase // case (rb_addr)
/*******************************************************************
* RX Data mux Routing logic
******************************************************************/
wire [63:0] r0_rx_tdata; wire r0_rx_tlast, r0_rx_tvalid, r0_rx_tready;
wire [63:0] r1_rx_tdata; wire r1_rx_tlast, r1_rx_tvalid, r1_rx_tready;
wire [63:0] rx_tdata_int; wire rx_tlast_int, rx_tvalid_int, rx_tready_int;
axi_mux4 #(.WIDTH(64), .BUFFER(1)) mux_for_rx
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i0_tdata(r0_rx_tdata), .i0_tlast(r0_rx_tlast), .i0_tvalid(r0_rx_tvalid), .i0_tready(r0_rx_tready),
.i1_tdata(r1_rx_tdata), .i1_tlast(r1_rx_tlast), .i1_tvalid(r1_rx_tvalid), .i1_tready(r1_rx_tready),
.i2_tdata(64'b0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(),
.i3_tdata(64'b0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(),
.o_tdata(rx_tdata_int), .o_tlast(rx_tlast_int), .o_tvalid(rx_tvalid_int), .o_tready(rx_tready_int));
axi_fifo #(.WIDTH(65), .SIZE(EXTRA_BUFF_SIZE)) extra_rx_buff
(.clk(bus_clk), .reset(bus_rst),.clear(1'b0),
.i_tdata({rx_tlast_int, rx_tdata_int}), .i_tvalid(rx_tvalid_int), .i_tready(rx_tready_int),
.o_tdata({rx_tlast, rx_tdata}), .o_tvalid(rx_tvalid), .o_tready(rx_tready));
/*******************************************************************
* TX Data mux Routing logic
******************************************************************/
wire [63:0] r0_tx_tdata; wire r0_tx_tlast, r0_tx_tvalid, r0_tx_tready;
wire [63:0] r1_tx_tdata; wire r1_tx_tlast, r1_tx_tvalid, r1_tx_tready;
wire [63:0] tx_tdata_int; wire tx_tlast_int, tx_tvalid_int, tx_tready_int;
axi_fifo #(.WIDTH(65), .SIZE(EXTRA_BUFF_SIZE)) extra_tx_buff
(.clk(bus_clk), .reset(bus_rst),.clear(1'b0),
.i_tdata({tx_tlast, tx_tdata}), .i_tvalid(tx_tvalid), .i_tready(tx_tready),
.o_tdata({tx_tlast_int, tx_tdata_int}), .o_tvalid(tx_tvalid_int), .o_tready(tx_tready_int));
wire [63:0] tx_hdr;
wire [1:0] tx_dst =
((tx_hdr[7:0] & DEMUX_SID_MASK) == R0_DATA_SID)? 0 : (
((tx_hdr[7:0] & DEMUX_SID_MASK) == R1_DATA_SID)? 1 : (
3));
axi_demux4 #(.ACTIVE_CHAN(4'b0011), .WIDTH(64), .BUFFER(1)) demux_for_tx
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.header(tx_hdr), .dest(tx_dst),
.i_tdata(tx_tdata_int), .i_tlast(tx_tlast_int), .i_tvalid(tx_tvalid_int), .i_tready(tx_tready_int),
.o0_tdata(r0_tx_tdata), .o0_tlast(r0_tx_tlast), .o0_tvalid(r0_tx_tvalid), .o0_tready(r0_tx_tready),
.o1_tdata(r1_tx_tdata), .o1_tlast(r1_tx_tlast), .o1_tvalid(r1_tx_tvalid), .o1_tready(r1_tx_tready),
.o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1),
.o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1));
/*******************************************************************
* Radio 0
******************************************************************/
wire [63:0] radio0_debug;
wire [31:0] fe0_gpio_out32;
assign fe0_gpio_out = fe0_gpio_out32[7:0];
radio_legacy #(
.RADIO_FIFO_SIZE(RADIO_FIFO_SIZE),
.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE),
.FP_GPIO(1),
.NEW_HB_INTERP(1),
.NEW_HB_DECIM(1),
.SOURCE_FLOW_CONTROL(0),
.USER_SETTINGS(0),
.DEVICE("SPARTAN6")
) radio_0 (
.radio_clk(radio_clk), .radio_rst(radio_rst),
.rx(rx0), .tx(tx0), .pps(pps), .time_sync(time_sync_r),
.fe_gpio_in(32'h00000000), .fe_gpio_out(fe0_gpio_out32), .fe_gpio_ddr(/* Always assumed to be outputs */),
.fp_gpio_in(fp_gpio_in), .fp_gpio_out(fp_gpio_out), .fp_gpio_ddr(fp_gpio_ddr),
.bus_clk(bus_clk), .bus_rst(bus_rst),
.tx_tdata(r0_tx_tdata), .tx_tlast(r0_tx_tlast), .tx_tvalid(r0_tx_tvalid), .tx_tready(r0_tx_tready),
.rx_tdata(r0_rx_tdata), .rx_tlast(r0_rx_tlast), .rx_tvalid(r0_rx_tvalid), .rx_tready(r0_rx_tready),
.ctrl_tdata(r0_ctrl_tdata), .ctrl_tlast(r0_ctrl_tlast), .ctrl_tvalid(r0_ctrl_tvalid), .ctrl_tready(r0_ctrl_tready),
.resp_tdata(r0_resp_tdata), .resp_tlast(r0_resp_tlast), .resp_tvalid(r0_resp_tvalid), .resp_tready(r0_resp_tready),
.debug(radio0_debug)
);
/*******************************************************************
* Radio 1
******************************************************************/
`ifdef TARGET_B210 // B210 Has two radio instances.
assign radio_st = 8'h2;
wire [63:0] radio1_debug;
wire [31:0] fe1_gpio_out32;
assign fe1_gpio_out = fe1_gpio_out32[7:0];
radio_legacy #(
.RADIO_FIFO_SIZE(RADIO_FIFO_SIZE),
.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE),
.FP_GPIO(0),
.NEW_HB_INTERP(1),
.NEW_HB_DECIM(1),
.SOURCE_FLOW_CONTROL(0),
.USER_SETTINGS(0),
.DEVICE("SPARTAN6")
) radio_1 (
.radio_clk(radio_clk), .radio_rst(radio_rst),
.rx(rx1), .tx(tx1), .pps(pps), .time_sync(time_sync_r),
.fe_gpio_in(32'h00000000), .fe_gpio_out(fe1_gpio_out32), .fe_gpio_ddr(/* Always assumed to be outputs */),
.fp_gpio_in(32'h00000000), .fp_gpio_out(), .fp_gpio_ddr(),
.bus_clk(bus_clk), .bus_rst(bus_rst),
.tx_tdata(r1_tx_tdata), .tx_tlast(r1_tx_tlast), .tx_tvalid(r1_tx_tvalid), .tx_tready(r1_tx_tready),
.rx_tdata(r1_rx_tdata), .rx_tlast(r1_rx_tlast), .rx_tvalid(r1_rx_tvalid), .rx_tready(r1_rx_tready),
.ctrl_tdata(r1_ctrl_tdata), .ctrl_tlast(r1_ctrl_tlast), .ctrl_tvalid(r1_ctrl_tvalid), .ctrl_tready(r1_ctrl_tready),
.resp_tdata(r1_resp_tdata), .resp_tlast(r1_resp_tlast), .resp_tvalid(r1_resp_tvalid), .resp_tready(r1_resp_tready),
.debug(radio1_debug)
);
`else
assign radio_st = 8'h1;
//assign undriven outputs
assign fe1_gpio_out = 32'b0; //Always assumed to be outputs
assign tx1 = 32'b0;
//unused control signals -- leave in loopback
assign r1_resp_tdata = r1_ctrl_tdata;
assign r1_resp_tlast = r1_ctrl_tlast;
assign r1_resp_tvalid = r1_ctrl_tvalid;
assign r1_ctrl_tready = r1_resp_tready;
//unused data signals -- leave in loopback
assign r1_rx_tdata = r1_tx_tdata;
assign r1_rx_tlast = r1_tx_tlast;
assign r1_rx_tvalid = r1_tx_tvalid;
assign r1_tx_tready = r1_tx_tready;
`endif // !`ifdef TARGET_B210
/*******************************************************************
* Debug UART for FX3
******************************************************************/
wire debug_stb;
wire [31:0] debug_data;
wire [7:0] debug_addr;
wire [31:0] debug_serial;
serial_to_settings serial_to_settings_i1
(
.clk(bus_clk),
.reset(bus_rst),
.scl(debug_scl),
.sda(debug_sda),
.set_stb(debug_stb),
.set_addr(debug_addr),
.set_data(debug_data),
.debug(debug_serial)
);
// Nasty Hack to convert settings to wishbone crudely.
reg wb_stb;
wire wb_ack_o;
always @(posedge bus_clk)
wb_stb <= debug_stb ? 1 : ((wb_ack_o) ? 0 : wb_stb);
simple_uart debug_uart
(
.clk_i(bus_clk),
.rst_i(bus_rst),
.we_i(wb_stb),
.stb_i(wb_stb),
.cyc_i(wb_stb),
.ack_o(wb_ack_o),
.adr_i(debug_addr[2:0]),
.dat_i(debug_data[31:0]),
.dat_o(),
.rx_int_o(),
.tx_int_o(),
.tx_o(debug_txd),
.rx_i(debug_rxd),
.baud_o()
);
endmodule // b200_core
top/b200/b200_io.v
+554
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//
// Copyright 2013 Ettus Research LLC
// Copyright 2017 Ettus Research, a National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
//
//------------------------------------------------------------------
//
// In SISO mode, we output a clock thats 1x the frequency of the Catalina
// source-synchronous bus clock to be used as the radio_clk.
// In MIMO mode, we output a clock thats 1/2 the frequency of the Catalina
// source-synchronous bus clock to be used as the radio_clk.
//
//------------------------------------------------------------------
module b200_io
(
input reset,
input mimo,
// Baseband sample interface
output radio_clk,
output [11:0] rx_i0,
output [11:0] rx_q0,
output [11:0] rx_i1,
output [11:0] rx_q1,
input [11:0] tx_i0,
input [11:0] tx_q0,
input [11:0] tx_i1,
input [11:0] tx_q1,
// Catalina interface
input rx_clk,
input rx_frame,
input [11:0] rx_data,
output tx_clk,
output tx_frame,
output [11:0] tx_data
);
genvar z;
//------------------------------------------------------------------
//
// Synchronize MIMO signal from bus_clk to siso_clk.
//
//------------------------------------------------------------------
reg mimo_sync, mimo_sync2;
always @(posedge siso_clk) begin
mimo_sync <= mimo_sync2;
mimo_sync2 <= mimo;
end
//------------------------------------------------------------------
// Clock Buffering.
// BUFIO2 drives all IDDR2 and ODDR2 cells directly in bank3.
// Need two pairs of BUFIO2 one pair each for Top Left and Bottom Left half banks.
//------------------------------------------------------------------
wire rx_clk_buf;
wire mimo_clk_unbuf;
wire siso_clk_unbuf;
wire siso2_clk_unbuf;
IBUFG clk_ibufg (.O(rx_clk_buf), .I(rx_clk));
//------------------------------------------------------------------
//
// Buffers for LEFT TOP half bank pins
// BUFIO2_X0Y22
//
//------------------------------------------------------------------
BUFIO2 #(
.DIVIDE(4),
.DIVIDE_BYPASS("FALSE"),
.I_INVERT("FALSE"),
.USE_DOUBLER("TRUE"))
clk_bufio_lt
(
.IOCLK(io_clk_lt),
.DIVCLK(mimo_clk_unbuf), // Non-inverted source of 1/2x interface clock for radio_clk
.SERDESSTROBE(),
.I(rx_clk_buf)
);
// BUFIO2_X0Y23
BUFIO2 #(
.DIVIDE(1),
.DIVIDE_BYPASS("FALSE"),
.I_INVERT("TRUE"),
.USE_DOUBLER("FALSE"))
clk_bufio_lt_b
(
.IOCLK(io_clk_lt_b),
.DIVCLK(siso_clk2_unbuf), // Inverted source of 1x interface clock for radio_clk
.SERDESSTROBE(),
.I(rx_clk_buf)
);
//------------------------------------------------------------------
//
// Buffers for LEFT BOTTOM half bank pins
// BUFIO2_X1Y14
//
//------------------------------------------------------------------
BUFIO2 #(
.DIVIDE(1),
.DIVIDE_BYPASS("FALSE"),
.I_INVERT("FALSE"),
.USE_DOUBLER("FALSE"))
clk_bufio_lb
(
.IOCLK(io_clk_lb),
.DIVCLK(siso_clk_unbuf), // Non-inverted source of 1x interface clock for local IO use
.SERDESSTROBE(),
.I(rx_clk_buf)
);
// BUFIO2_X1Y15
BUFIO2 #(
.DIVIDE(1),
.DIVIDE_BYPASS("FALSE"),
.I_INVERT("TRUE"),
.USE_DOUBLER("FALSE"))
clk_bufio_lb_b
(
.IOCLK(io_clk_lb_b),
.DIVCLK(),
.SERDESSTROBE(),
.I(rx_clk_buf)
);
//------------------------------------------------------------------
// Always-on SISO clk needed to load/unload DDR2 I/O Regs
//------------------------------------------------------------------
BUFG siso_clk_bufg (
.I(siso_clk_unbuf),
.O(siso_clk)
);
//------------------------------------------------------------------
// 2-1 mux combined with BUFG to drive global radio_clk.
// Note: Not addressed setup/hold constraints of S input ...unsure if anything "bad" can happen here.
//------------------------------------------------------------------
BUFGMUX #(
.CLK_SEL_TYPE("SYNC"))
radio_clk_bufg (
.I0(siso_clk2_unbuf),
.I1(mimo_clk_unbuf),
.S(mimo_sync),
.O(radio_clk)
);
//------------------------------------------------------------------
// RX Frame Signal - In bank 3 LB
//------------------------------------------------------------------
wire rx_frame_0, rx_frame_1;
IDDR2 #(
.DDR_ALIGNMENT("C0"))
iddr2_frame (
.Q0(rx_frame_1),
.Q1(rx_frame_0),
.C0(io_clk_lb),
.C1(io_clk_lb_b),
.CE(1'b1),
.D(rx_frame),
.R(1'b0),
.S(1'b0));
reg rx_frame_d1, rx_frame_d2;
always @(posedge siso_clk)
if(~mimo_sync)
{ rx_frame_d2, rx_frame_d1 } <= { rx_frame_1, 1'b0 };
else
{ rx_frame_d2, rx_frame_d1 } <= { rx_frame_d1, rx_frame_1 };
//------------------------------------------------------------------
// RX Data Bus - In bank3 both LT and LB
//------------------------------------------------------------------
wire [11:0] rx_i,rx_q;
// Bit0 LB
IDDR2 #(
.DDR_ALIGNMENT("C0"))
iddr2_i0 (
.Q0(rx_q[0]),
.Q1(rx_i[0]),
.C0(io_clk_lb),
.C1(io_clk_lb_b),
.CE(1'b1),
.D(rx_data[0]),
.R(1'b0),
.S(1'b0));
// Bit1 LB
IDDR2 #(
.DDR_ALIGNMENT("C0"))
iddr2_i1 (
.Q0(rx_q[1]),
.Q1(rx_i[1]),
.C0(io_clk_lb),
.C1(io_clk_lb_b),
.CE(1'b1),
.D(rx_data[1]),
.R(1'b0),
.S(1'b0));
// Bit2 LB
IDDR2 #(
.DDR_ALIGNMENT("C0"))
iddr2_i2 (
.Q0(rx_q[2]),
.Q1(rx_i[2]),
.C0(io_clk_lb),
.C1(io_clk_lb_b),
.CE(1'b1),
.D(rx_data[2]),
.R(1'b0),
.S(1'b0));
// Bit3 LT
IDDR2 #(
.DDR_ALIGNMENT("C0"))
iddr2_i3 (
.Q0(rx_q[3]),
.Q1(rx_i[3]),
.C0(io_clk_lt),
.C1(io_clk_lt_b),
.CE(1'b1),
.D(rx_data[3]),
.R(1'b0),
.S(1'b0));
// Bit4 LB
IDDR2 #(
.DDR_ALIGNMENT("C0"))
iddr2_i4 (
.Q0(rx_q[4]),
.Q1(rx_i[4]),
.C0(io_clk_lb),
.C1(io_clk_lb_b),
.CE(1'b1),
.D(rx_data[4]),
.R(1'b0),
.S(1'b0));
// Bit5 LT
IDDR2 #(
.DDR_ALIGNMENT("C0"))
iddr2_i5 (
.Q0(rx_q[5]),
.Q1(rx_i[5]),
.C0(io_clk_lt),
.C1(io_clk_lt_b),
.CE(1'b1),
.D(rx_data[5]),
.R(1'b0),
.S(1'b0));
// Bit6 LB
IDDR2 #(
.DDR_ALIGNMENT("C0"))
iddr2_i6 (
.Q0(rx_q[6]),
.Q1(rx_i[6]),
.C0(io_clk_lb),
.C1(io_clk_lb_b),
.CE(1'b1),
.D(rx_data[6]),
.R(1'b0),
.S(1'b0));
// Bit7 LT
IDDR2 #(
.DDR_ALIGNMENT("C0"))
iddr2_i7 (
.Q0(rx_q[7]),
.Q1(rx_i[7]),
.C0(io_clk_lt),
.C1(io_clk_lt_b),
.CE(1'b1),
.D(rx_data[7]),
.R(1'b0),
.S(1'b0));
// Bit8 LB
IDDR2 #(
.DDR_ALIGNMENT("C0"))
iddr2_i8 (
.Q0(rx_q[8]),
.Q1(rx_i[8]),
.C0(io_clk_lb),
.C1(io_clk_lb_b),
.CE(1'b1),
.D(rx_data[8]),
.R(1'b0),
.S(1'b0));
// Bit9 LT
IDDR2 #(
.DDR_ALIGNMENT("C0"))
iddr2_i9 (
.Q0(rx_q[9]),
.Q1(rx_i[9]),
.C0(io_clk_lt),
.C1(io_clk_lt_b),
.CE(1'b1),
.D(rx_data[9]),
.R(1'b0),
.S(1'b0));
// Bit10 LB
IDDR2 #(
.DDR_ALIGNMENT("C0"))
iddr2_i10 (
.Q0(rx_q[10]),
.Q1(rx_i[10]),
.C0(io_clk_lb),
.C1(io_clk_lb_b),
.CE(1'b1),
.D(rx_data[10]),
.R(1'b0),
.S(1'b0));
// Bit11 LB
IDDR2 #(
.DDR_ALIGNMENT("C0"))
iddr2_i11 (
.Q0(rx_q[11]),
.Q1(rx_i[11]),
.C0(io_clk_lb),
.C1(io_clk_lb_b),
.CE(1'b1),
.D(rx_data[11]),
.R(1'b0),
.S(1'b0));
//------------------------------------------------------------------
//
// De-mux I & Q, Ch A & B onto fullrate clock.
//
// In all modes we grab data from the IDDR2 using negedge of siso_clk.
// IDDR2 updates all Q pins on posedge of io_clk. siso_clk does not have aligned phase
// with siso_clk...siso_clk is always a little more delayed than io_clk.
// This small delay is always much smaller than half a clk cycle. Thus by sampling the Q outputs
// with negedge siso_clk we avoid any risk of a race condition (hold violation on receiveing register).
//
// In SISO mode data is replicated onto both CH0 and CH1 for max flexibility in using the DDC's.
//
//------------------------------------------------------------------
reg [11:0] rx_i_del, rx_q_del;
reg [11:0] rx_i0_siso_pos;
reg [11:0] rx_q0_siso_pos;
reg [11:0] rx_i1_siso_pos;
reg [11:0] rx_q1_siso_pos;
reg [11:0] rx_i0_siso_neg;
reg [11:0] rx_q0_siso_neg;
reg [11:0] rx_i1_siso_neg;
reg [11:0] rx_q1_siso_neg;
reg [11:0] rx_i0_siso;
reg [11:0] rx_q0_siso;
reg [11:0] rx_i1_siso;
reg [11:0] rx_q1_siso;
always @(negedge siso_clk)
if(mimo_sync)
// rx_frame_0 was sampled by same falling io_clk edge as rx_i[x]
// rx_frame_0 == 0 causes I & Q to be allocated to CH0
if(rx_frame_0) begin
rx_i_del[11:0] <= rx_i[11:0];
rx_q_del[11:0] <= rx_q[11:0];
end
else begin
// Deal with the fact that Ch A and Ch B are labelled in silkscreen opposite to their documentation in AD9361.
rx_i0_siso[11:0] <= rx_i[11:0];
rx_q0_siso[11:0] <= rx_q[11:0];
rx_i1_siso[11:0] <= rx_i_del[11:0];
rx_q1_siso[11:0] <= rx_q_del[11:0];
end
else begin
rx_i0_siso[11:0] <= rx_i[11:0];
rx_q0_siso[11:0] <= rx_q[11:0];
rx_i1_siso[11:0] <= rx_i[11:0];
rx_q1_siso[11:0] <= rx_q[11:0];
end // else: !if(rx_frame_0)
//------------------------------------------------------------------
//
// Now prepare data for crossing into radio_clk domain which can be for SISO mode (inverted) siso_clk or for MIMO mode siso_clk/2.
// In MIMO mode tx_strobe is used to maintain a known phase relationship betwwen siso_clk and radio_clk.
// (Note: Negedge or posedge is used conditionally so that we have massive margin against a fast-path race condition
// betwwen siso_clk and radio_clk). This kind of arrangement could still lead to confusion in timing analysis
// even if it works in the real world depending on how well the STA tool can do automatic case analysis.
//
//------------------------------------------------------------------
// This code lock only relevent in MIMO mode.
always @(negedge siso_clk)
if (tx_strobe)
begin
rx_i0_siso_neg[11:0] <= rx_i0_siso[11:0];
rx_q0_siso_neg[11:0] <= rx_q0_siso[11:0];
rx_i1_siso_neg[11:0] <= rx_i1_siso[11:0];
rx_q1_siso_neg[11:0] <= rx_q1_siso[11:0];
end
// This code block only relevent in SISO mode.
always @(posedge siso_clk)
begin
rx_i0_siso_pos[11:0] <= rx_i0_siso[11:0];
rx_q0_siso_pos[11:0] <= rx_q0_siso[11:0];
rx_i1_siso_pos[11:0] <= rx_i1_siso[11:0];
rx_q1_siso_pos[11:0] <= rx_q1_siso[11:0];
end
assign rx_i0 = (mimo_sync) ? rx_i0_siso_neg : rx_i0_siso_pos;
assign rx_q0 = (mimo_sync) ? rx_q0_siso_neg : rx_q0_siso_pos;
assign rx_i1 = (mimo_sync) ? rx_i1_siso_neg : rx_i1_siso_pos;
assign rx_q1 = (mimo_sync) ? rx_q1_siso_neg : rx_q1_siso_pos;
//------------------------------------------------------------------
// TX Data Bus - In bank3 LB
//------------------------------------------------------------------
reg [11:0] tx_i,tx_q;
reg tx_strobe_del;
generate
for(z = 0; z < 12; z = z + 1)
begin : gen_pins
ODDR2 #(
.DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC"))
oddr2 (
.Q(tx_data[z]), .C0(io_clk_lb), .C1(io_clk_lb_b),
.CE(1'b1), .D0(tx_i[z]), .D1(tx_q[z]), .R(1'b0), .S(1'b0));
end
endgenerate
//------------------------------------------------------------------
// TX Frame Signal - In bank 3 LB
//------------------------------------------------------------------
ODDR2 #(
.DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC"))
oddr2_frame (
.Q(tx_frame), .C0(io_clk_lb), .C1(io_clk_lb_b),
.CE(1'b1), .D0(tx_strobe_del), .D1(mimo_sync & tx_strobe_del), .R(1'b0), .S(1'b0));
//------------------------------------------------------------------
// TX Clock Signal - In bank 3 LB
//------------------------------------------------------------------
ODDR2 #(
.DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC"))
oddr2_clk (
.Q(tx_clk), .C0(io_clk_lb), .C1(io_clk_lb_b),
.CE(1'b1), .D0(1'b1), .D1(1'b0), .R(1'b0), .S(1'b0));
//------------------------------------------------------------------
//
// Mux I & Q, Ch A & B onto fullrate clockTX bus to AD9361
//
//------------------------------------------------------------------
wire tx_strobe;
reg [11:0] tx_i_del, tx_q_del;
reg find_radio_clk_phase = 1'b0;
reg find_radio_clk_phase_del;
always @(posedge radio_clk)
find_radio_clk_phase <= ~find_radio_clk_phase;
always @(negedge radio_clk)
find_radio_clk_phase_del <= find_radio_clk_phase;
assign tx_strobe = mimo_sync ? (find_radio_clk_phase_del ^ find_radio_clk_phase) : 1'b1;
always @(posedge siso_clk)
tx_strobe_del <= tx_strobe;
// This strange piece of logic allows either USRP DUC to drive the AD9361 in SISO mode.
// This is principly used in the CODEC loopback test.
wire [11:0] tx_im = (mimo_sync || tx_i0 != 12'h0) ? tx_i0 : tx_i1;
wire [11:0] tx_qm = (mimo_sync || tx_q0 != 12'h0) ? tx_q0 : tx_q1;
// Deal with the fact that Ch A and Ch B are labelled in silkscreen opposite to their documentation in AD9361.
// (Except on B200 based on AD9364 where only the true Ch A is stuffed)
always @(posedge siso_clk)
if(tx_strobe)
begin
{tx_i,tx_q} <= mimo_sync ? {tx_i1,tx_q1} : {tx_im,tx_qm};
{tx_i_del,tx_q_del} <= {tx_i0,tx_q0};
end
else
{tx_i,tx_q} <= {tx_i_del,tx_q_del};
//
// Debug
//
/* -----\/----- EXCLUDED -----\/-----
wire [35:0] CONTROL0;
reg [11:0] tx_i_del_debug, tx_q_del_debug;
reg [11:0] tx_i_debug,tx_q_debug;
reg [11:0] tx_i0_debug,tx_q0_debug;
reg find_radio_clk_phase_debug;
reg find_radio_clk_phase_del_debug;
reg tx_strobe_debug;
reg tx_strobe_del_debug;
always @(posedge siso_clk) begin
tx_i_del_debug <= tx_i_del;
tx_q_del_debug <= tx_q_del;
tx_i_debug <= tx_i;
tx_q_debug <= tx_q;
tx_i0_debug <=tx_i0;
tx_q0_debug <= tx_q0;
find_radio_clk_phase_debug <= find_radio_clk_phase;
find_radio_clk_phase_del_debug <= find_radio_clk_phase_del;
tx_strobe_debug <= tx_strobe;
tx_strobe_del_debug <= tx_strobe_del;
end
chipscope_icon chipscope_icon_i0
(
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
chipscope_ila_128 chipscope_ila_i0
(
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(siso_clk), // IN
.TRIG0(
{
tx_i_del_debug[11:0],
tx_q_del_debug[11:0],
tx_i_debug[11:0],
tx_q_debug[11:0],
tx_i0_debug[11:0],
tx_q0_debug[11:0],
find_radio_clk_phase_debug,
find_radio_clk_phase_del_debug,
tx_strobe_debug,
tx_strobe_del_debug
}
)
);
-----/\----- EXCLUDED -----/\----- */
endmodule
top/b200/check.sh
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iverilog ../top/b200/b200.v -y control/ -y timing/ -y fifo/ -y vita/ -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ -y ../top/b200/ -y ../top/b200/coregen/ -y gpif2/ -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/XilinxCoreLib/ -Wall | grep -v timescale
top/b200/core_compile
Executable
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iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif2/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac B200.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models
top/b200/coregen/.gitignore
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/tmp
/_xmsgs
/*.log
/*.gise
/*.xise
top/b200/coregen/b200_chipscope_icon.asy
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Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 b200_chipscope_icon
RECTANGLE Normal 32 32 544 864
LINE Wide 576 112 544 112
PIN 576 112 RIGHT 36
PINATTR PinName control0[35:0]
PINATTR Polarity BOTH
top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
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NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
#Update Constraints
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
NET "U0/iSHIFT_OUT" TIG ;
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
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# icon XDC
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
top/b200/coregen/b200_chipscope_icon.ncf
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top/b200/coregen/b200_chipscope_icon.ngc
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File diff suppressed because one or more lines are too long
top/b200/coregen/b200_chipscope_icon.ucf
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NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
#Update Constraints
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
NET "U0/iSHIFT_OUT" TIG ;
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
top/b200/coregen/b200_chipscope_icon.v
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : b200_chipscope_icon.v
// /___/ /\ Timestamp : Tue Feb 19 14:28:40 PST 2013
// \ \ / \
// \___\/\___\
//
// Design Name: Verilog Synthesis Wrapper
///////////////////////////////////////////////////////////////////////////////
// This wrapper is used to integrate with Project Navigator and PlanAhead
`timescale 1ns/1ps
module b200_chipscope_icon(
CONTROL0) /* synthesis syn_black_box syn_noprune=1 */;
inout [35 : 0] CONTROL0;
endmodule
top/b200/coregen/b200_chipscope_icon.veo
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : b200_chipscope_icon.veo
// /___/ /\ Timestamp : Tue Feb 19 14:28:40 PST 2013
// \ \ / \
// \___\/\___\
//
// Design Name: ISE Instantiation template
///////////////////////////////////////////////////////////////////////////////
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
b200_chipscope_icon YourInstanceName (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
top/b200/coregen/b200_chipscope_icon.xco
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##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Tue Feb 19 22:27:58 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx75
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
# END Select
# BEGIN Parameters
CSET component_name=b200_chipscope_icon
CSET constraint_type=external
CSET enable_jtag_bufg=true
CSET example_design=false
CSET number_control_ports=1
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T02:47:25Z
# END Extra information
GENERATE
# CRC: 729764e8
top/b200/coregen/b200_chipscope_icon.xdc
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# icon XDC
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
top/b200/coregen/b200_chipscope_icon_flist.txt
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# Output products list for <b200_chipscope_icon>
b200_chipscope_icon.asy
b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
b200_chipscope_icon.gise
b200_chipscope_icon.ngc
b200_chipscope_icon.ucf
b200_chipscope_icon.v
b200_chipscope_icon.veo
b200_chipscope_icon.xco
b200_chipscope_icon.xdc
b200_chipscope_icon.xise
b200_chipscope_icon_flist.txt
b200_chipscope_icon_readme.txt
b200_chipscope_icon_xmdf.tcl
top/b200/coregen/b200_chipscope_icon_readme.txt
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The following files were generated for 'b200_chipscope_icon' in directory
/home/bhilburn/xilinx/
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* b200_chipscope_icon.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
* b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
* b200_chipscope_icon.ngc
* b200_chipscope_icon.ucf
* b200_chipscope_icon.v
* b200_chipscope_icon.veo
* b200_chipscope_icon.xdc
* b200_chipscope_icon_xmdf.tcl
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* b200_chipscope_icon.asy
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* b200_chipscope_icon.gise
* b200_chipscope_icon.xise
Deliver Readme:
Readme file for the IP.
* b200_chipscope_icon_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* b200_chipscope_icon_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
top/b200/coregen/b200_chipscope_icon_xmdf.tcl
Executable
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# The package naming convention is <core_name>_xmdf
package provide b200_chipscope_icon_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::b200_chipscope_icon_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::b200_chipscope_icon_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_chipscope_icon
}
# ::b200_chipscope_icon_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::b200_chipscope_icon_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.ncf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.xcf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_chipscope_icon
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/b200/coregen/b200_chipscope_ila.asy
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Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 b200_chipscope_ila
RECTANGLE Normal 32 32 288 704
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName control[35:0]
PINATTR Polarity IN
LINE Normal 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName clk
PINATTR Polarity IN
LINE Wide 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName data[63:0]
PINATTR Polarity IN
LINE Wide 0 176 32 176
PIN 0 176 LEFT 36
PINATTR PinName trig0[7:0]
PINATTR Polarity IN
top/b200/coregen/b200_chipscope_ila.cdc
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#ChipScope Core Generator Project File Version 3.0
#Tue Feb 19 16:52:47 PST 2013
SignalExport.clockChannel=CLK
SignalExport.dataChannel<0000>=DATA[0]
SignalExport.dataChannel<0001>=DATA[1]
SignalExport.dataChannel<0002>=DATA[2]
SignalExport.dataChannel<0003>=DATA[3]
SignalExport.dataChannel<0004>=DATA[4]
SignalExport.dataChannel<0005>=DATA[5]
SignalExport.dataChannel<0006>=DATA[6]
SignalExport.dataChannel<0007>=DATA[7]
SignalExport.dataChannel<0008>=DATA[8]
SignalExport.dataChannel<0009>=DATA[9]
SignalExport.dataChannel<0010>=DATA[10]
SignalExport.dataChannel<0011>=DATA[11]
SignalExport.dataChannel<0012>=DATA[12]
SignalExport.dataChannel<0013>=DATA[13]
SignalExport.dataChannel<0014>=DATA[14]
SignalExport.dataChannel<0015>=DATA[15]
SignalExport.dataChannel<0016>=DATA[16]
SignalExport.dataChannel<0017>=DATA[17]
SignalExport.dataChannel<0018>=DATA[18]
SignalExport.dataChannel<0019>=DATA[19]
SignalExport.dataChannel<0020>=DATA[20]
SignalExport.dataChannel<0021>=DATA[21]
SignalExport.dataChannel<0022>=DATA[22]
SignalExport.dataChannel<0023>=DATA[23]
SignalExport.dataChannel<0024>=DATA[24]
SignalExport.dataChannel<0025>=DATA[25]
SignalExport.dataChannel<0026>=DATA[26]
SignalExport.dataChannel<0027>=DATA[27]
SignalExport.dataChannel<0028>=DATA[28]
SignalExport.dataChannel<0029>=DATA[29]
SignalExport.dataChannel<0030>=DATA[30]
SignalExport.dataChannel<0031>=DATA[31]
SignalExport.dataChannel<0032>=DATA[32]
SignalExport.dataChannel<0033>=DATA[33]
SignalExport.dataChannel<0034>=DATA[34]
SignalExport.dataChannel<0035>=DATA[35]
SignalExport.dataChannel<0036>=DATA[36]
SignalExport.dataChannel<0037>=DATA[37]
SignalExport.dataChannel<0038>=DATA[38]
SignalExport.dataChannel<0039>=DATA[39]
SignalExport.dataChannel<0040>=DATA[40]
SignalExport.dataChannel<0041>=DATA[41]
SignalExport.dataChannel<0042>=DATA[42]
SignalExport.dataChannel<0043>=DATA[43]
SignalExport.dataChannel<0044>=DATA[44]
SignalExport.dataChannel<0045>=DATA[45]
SignalExport.dataChannel<0046>=DATA[46]
SignalExport.dataChannel<0047>=DATA[47]
SignalExport.dataChannel<0048>=DATA[48]
SignalExport.dataChannel<0049>=DATA[49]
SignalExport.dataChannel<0050>=DATA[50]
SignalExport.dataChannel<0051>=DATA[51]
SignalExport.dataChannel<0052>=DATA[52]
SignalExport.dataChannel<0053>=DATA[53]
SignalExport.dataChannel<0054>=DATA[54]
SignalExport.dataChannel<0055>=DATA[55]
SignalExport.dataChannel<0056>=DATA[56]
SignalExport.dataChannel<0057>=DATA[57]
SignalExport.dataChannel<0058>=DATA[58]
SignalExport.dataChannel<0059>=DATA[59]
SignalExport.dataChannel<0060>=DATA[60]
SignalExport.dataChannel<0061>=DATA[61]
SignalExport.dataChannel<0062>=DATA[62]
SignalExport.dataChannel<0063>=DATA[63]
SignalExport.dataEqualsTrigger=false
SignalExport.dataPortWidth=64
SignalExport.triggerChannel<0000><0000>=TRIG0[0]
SignalExport.triggerChannel<0000><0001>=TRIG0[1]
SignalExport.triggerChannel<0000><0002>=TRIG0[2]
SignalExport.triggerChannel<0000><0003>=TRIG0[3]
SignalExport.triggerChannel<0000><0004>=TRIG0[4]
SignalExport.triggerChannel<0000><0005>=TRIG0[5]
SignalExport.triggerChannel<0000><0006>=TRIG0[6]
SignalExport.triggerChannel<0000><0007>=TRIG0[7]
SignalExport.triggerPort<0000>.name=TRIG0
SignalExport.triggerPortCount=1
SignalExport.triggerPortIsData<0000>=false
SignalExport.triggerPortWidth<0000>=8
SignalExport.type=ila
top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
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#
# Clock constraints
#
NET "CLK" TNM_NET = D_CLK ;
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
TIMESPEC TS_D2_TO_T2_b200_chipscope_ila = FROM D2_CLK TO "FFS" TIG;
TIMESPEC TS_J2_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J3_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J4_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
#
# Input keep/save net constraints
#
NET "TRIG0<*" S;
NET "TRIG0<*" KEEP;
NET "DATA<*" S;
NET "DATA<*" KEEP;
top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
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#
# Clock constraints
#
set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
top/b200/coregen/b200_chipscope_ila.ncf
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top/b200/coregen/b200_chipscope_ila.ngc
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top/b200/coregen/b200_chipscope_ila.ucf
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#
# Clock constraints
#
NET "CLK" TNM_NET = D_CLK ;
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
TIMESPEC TS_D2_TO_T2_b200_chipscope_ila = FROM D2_CLK TO "FFS" TIG;
TIMESPEC TS_J2_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J3_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J4_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
#
# Input keep/save net constraints
#
NET "TRIG0<*" S;
NET "TRIG0<*" KEEP;
NET "DATA<*" S;
NET "DATA<*" KEEP;
top/b200/coregen/b200_chipscope_ila.v
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : b200_chipscope_ila.v
// /___/ /\ Timestamp : Tue Feb 19 16:52:47 PST 2013
// \ \ / \
// \___\/\___\
//
// Design Name: Verilog Synthesis Wrapper
///////////////////////////////////////////////////////////////////////////////
// This wrapper is used to integrate with Project Navigator and PlanAhead
`timescale 1ns/1ps
module b200_chipscope_ila(
CONTROL,
CLK,
DATA,
TRIG0) /* synthesis syn_black_box syn_noprune=1 */;
inout [35 : 0] CONTROL;
input CLK;
input [63 : 0] DATA;
input [7 : 0] TRIG0;
endmodule
top/b200/coregen/b200_chipscope_ila.veo
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : b200_chipscope_ila.veo
// /___/ /\ Timestamp : Tue Feb 19 16:52:47 PST 2013
// \ \ / \
// \___\/\___\
//
// Design Name: ISE Instantiation template
///////////////////////////////////////////////////////////////////////////////
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
b200_chipscope_ila YourInstanceName (
.CONTROL(CONTROL), // INOUT BUS [35:0]
.CLK(CLK), // IN
.DATA(DATA), // IN BUS [63:0]
.TRIG0(TRIG0) // IN BUS [7:0]
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
top/b200/coregen/b200_chipscope_ila.xco
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##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Feb 20 00:50:54 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx75
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET check_bramcount=false
CSET component_name=b200_chipscope_ila
CSET constraint_type=external
CSET counter_width_1=Disabled
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=64
CSET data_same_as_trigger=false
CSET disable_save_keep=false
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=false
CSET example_design=false
CSET exclude_from_data_storage_1=true
CSET exclude_from_data_storage_10=true
CSET exclude_from_data_storage_11=true
CSET exclude_from_data_storage_12=true
CSET exclude_from_data_storage_13=true
CSET exclude_from_data_storage_14=true
CSET exclude_from_data_storage_15=true
CSET exclude_from_data_storage_16=true
CSET exclude_from_data_storage_2=true
CSET exclude_from_data_storage_3=true
CSET exclude_from_data_storage_4=true
CSET exclude_from_data_storage_5=true
CSET exclude_from_data_storage_6=true
CSET exclude_from_data_storage_7=true
CSET exclude_from_data_storage_8=true
CSET exclude_from_data_storage_9=true
CSET match_type_1=basic_with_edges
CSET match_type_10=basic_with_edges
CSET match_type_11=basic_with_edges
CSET match_type_12=basic_with_edges
CSET match_type_13=basic_with_edges
CSET match_type_14=basic_with_edges
CSET match_type_15=basic_with_edges
CSET match_type_16=basic_with_edges
CSET match_type_2=basic_with_edges
CSET match_type_3=basic_with_edges
CSET match_type_4=basic_with_edges
CSET match_type_5=basic_with_edges
CSET match_type_6=basic_with_edges
CSET match_type_7=basic_with_edges
CSET match_type_8=basic_with_edges
CSET match_type_9=basic_with_edges
CSET match_units_1=1
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=1
CSET number_of_trigger_ports=1
CSET sample_data_depth=8192
CSET sample_on=Rising
CSET trigger_port_width_1=8
CSET trigger_port_width_10=8
CSET trigger_port_width_11=8
CSET trigger_port_width_12=8
CSET trigger_port_width_13=8
CSET trigger_port_width_14=8
CSET trigger_port_width_15=8
CSET trigger_port_width_16=8
CSET trigger_port_width_2=8
CSET trigger_port_width_3=8
CSET trigger_port_width_4=8
CSET trigger_port_width_5=8
CSET trigger_port_width_6=8
CSET trigger_port_width_7=8
CSET trigger_port_width_8=8
CSET trigger_port_width_9=8
CSET use_rpms=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T02:47:40Z
# END Extra information
GENERATE
# CRC: 92d75d38
top/b200/coregen/b200_chipscope_ila.xdc
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#
# Clock constraints
#
set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
top/b200/coregen/b200_chipscope_ila_flist.txt
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# Output products list for <b200_chipscope_ila>
_xmsgs/pn_parser.xmsgs
b200_chipscope_ila.asy
b200_chipscope_ila.cdc
b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
b200_chipscope_ila.gise
b200_chipscope_ila.ncf
b200_chipscope_ila.ngc
b200_chipscope_ila.ucf
b200_chipscope_ila.v
b200_chipscope_ila.veo
b200_chipscope_ila.xco
b200_chipscope_ila.xdc
b200_chipscope_ila.xise
b200_chipscope_ila_flist.txt
b200_chipscope_ila_readme.txt
b200_chipscope_ila_xmdf.tcl
top/b200/coregen/b200_chipscope_ila_readme.txt
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The following files were generated for 'b200_chipscope_ila' in directory
/home/bhilburn/code/ettus/b200_dev/fpgapriv.git/usrp3/top/b200/coregen/
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* b200_chipscope_ila.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* b200_chipscope_ila.cdc
* b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
* b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
* b200_chipscope_ila.ncf
* b200_chipscope_ila.ngc
* b200_chipscope_ila.ucf
* b200_chipscope_ila.v
* b200_chipscope_ila.veo
* b200_chipscope_ila.xdc
* b200_chipscope_ila_xmdf.tcl
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* b200_chipscope_ila.asy
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* _xmsgs/pn_parser.xmsgs
* b200_chipscope_ila.gise
* b200_chipscope_ila.xise
Deliver Readme:
Readme file for the IP.
* b200_chipscope_ila_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* b200_chipscope_ila_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
top/b200/coregen/b200_chipscope_ila_xmdf.tcl
Executable
+87
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# The package naming convention is <core_name>_xmdf
package provide b200_chipscope_ila_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::b200_chipscope_ila_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::b200_chipscope_ila_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_chipscope_ila
}
# ::b200_chipscope_ila_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::b200_chipscope_ila_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.cdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.ncf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_chipscope_ila
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/b200/coregen/b200_clk_gen.asy
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Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 b200_clk_gen
RECTANGLE Normal 32 32 576 1088
LINE Normal 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName clk_in1_p
PINATTR Polarity IN
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName clk_in1_n
PINATTR Polarity IN
LINE Normal 0 432 32 432
PIN 0 432 LEFT 36
PINATTR PinName reset
PINATTR Polarity IN
LINE Normal 608 80 576 80
PIN 608 80 RIGHT 36
PINATTR PinName clk_out1
PINATTR Polarity OUT
LINE Normal 608 176 576 176
PIN 608 176 RIGHT 36
PINATTR PinName clk_out2
PINATTR Polarity OUT
LINE Normal 608 272 576 272
PIN 608 272 RIGHT 36
PINATTR PinName clk_out3
PINATTR Polarity OUT
LINE Normal 608 976 576 976
PIN 608 976 RIGHT 36
PINATTR PinName locked
PINATTR Polarity OUT
top/b200/coregen/b200_clk_gen.ucf
Executable
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# file: b200_clk_gen.ucf
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# Input clock periods. These duplicate the values entered for the
# input clocks. You can use these to time your system
#----------------------------------------------------------------
# Differential clock only needs one constraint
NET "CLK_IN1_P" TNM_NET = "CLK_IN1_P";
TIMESPEC "TS_CLK_IN1_P" = PERIOD "CLK_IN1_P" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps;
# Derived clock periods. These are commented out because they are
# automatically propogated by the tools
# However, if you'd like to use them for module level testing, you
# can copy them into your module level timing checks
#-----------------------------------------------------------------
# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 40.000 MHz;
# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz;
# NET "clk_int[3]" TNM_NET = "CLK_OUT3";
# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz;
# FALSE PATH constraints
PIN "RESET" TIG;
top/b200/coregen/b200_clk_gen.v
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// file: b200_clk_gen.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____40.000______0.000______50.0______200.000____150.000
// CLK_OUT2___100.000______0.000______50.0______400.000____150.000
// CLK_OUT3___100.000______0.000______50.0______400.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary__________40.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "b200_clk_gen,clk_wiz_v3_6,{component_name=b200_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module b200_clk_gen
(// Clock in ports
input CLK_IN1_40_P,
input CLK_IN1_40_N,
// Clock out ports
output CLK_OUT1_40_int,
output CLK_OUT2_100_gpif,
output CLK_OUT3_100_bus,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFGDS clkin1_buf
(.O (clkin1),
.I (CLK_IN1_40_P),
.IB (CLK_IN1_40_N));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (2),
.CLKFX_MULTIPLY (5),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (25.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (RESET),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
assign clkfb = CLK_OUT1_40_int;
BUFG clkout1_buf
(.O (CLK_OUT1_40_int),
.I (clk0));
BUFG clkout2_buf
(.O (CLK_OUT2_100_gpif),
.I (clkfx));
BUFG clkout3_buf
(.O (CLK_OUT3_100_bus),
.I (clkfx));
endmodule
top/b200/coregen/b200_clk_gen.veo
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//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____40.000______0.000______50.0______200.000____150.000
// CLK_OUT2___100.000______0.000______50.0______400.000____150.000
// CLK_OUT3___100.000______0.000______50.0______400.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary__________40.000____________0.010
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
b200_clk_gen instance_name
(// Clock in ports
.CLK_IN1_40_P(CLK_IN1_40_P), // IN
.CLK_IN1_40_N(CLK_IN1_40_N), // IN
// Clock out ports
.CLK_OUT1_40_int(CLK_OUT1_40_int), // OUT
.CLK_OUT2_100_gpif(CLK_OUT2_100_gpif), // OUT
.CLK_OUT3_100_bus(CLK_OUT3_100_bus), // OUT
// Status and control signals
.RESET(RESET),// IN
.LOCKED(LOCKED)); // OUT
// INST_TAG_END ------ End INSTANTIATION Template ---------
top/b200/coregen/b200_clk_gen.xco
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##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Fri Jan 25 20:00:48 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:clk_wiz:3.6
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx75
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
# END Select
# BEGIN Parameters
CSET calc_done=DONE
CSET clk_in_sel_port=CLK_IN_SEL
CSET clk_out1_port=CLK_OUT1_40_int
CSET clk_out1_use_fine_ps_gui=false
CSET clk_out2_port=CLK_OUT2_100_gpif
CSET clk_out2_use_fine_ps_gui=false
CSET clk_out3_port=CLK_OUT3_100_bus
CSET clk_out3_use_fine_ps_gui=false
CSET clk_out4_port=CLK_OUT4
CSET clk_out4_use_fine_ps_gui=false
CSET clk_out5_port=CLK_OUT5
CSET clk_out5_use_fine_ps_gui=false
CSET clk_out6_port=CLK_OUT6
CSET clk_out6_use_fine_ps_gui=false
CSET clk_out7_port=CLK_OUT7
CSET clk_out7_use_fine_ps_gui=false
CSET clk_valid_port=CLK_VALID
CSET clkfb_in_n_port=CLKFB_IN_N
CSET clkfb_in_p_port=CLKFB_IN_P
CSET clkfb_in_port=CLKFB_IN
CSET clkfb_in_signaling=SINGLE
CSET clkfb_out_n_port=CLKFB_OUT_N
CSET clkfb_out_p_port=CLKFB_OUT_P
CSET clkfb_out_port=CLKFB_OUT
CSET clkfb_stopped_port=CLKFB_STOPPED
CSET clkin1_jitter_ps=250.0
CSET clkin1_ui_jitter=0.010
CSET clkin2_jitter_ps=100.0
CSET clkin2_ui_jitter=0.010
CSET clkout1_drives=BUFG
CSET clkout1_requested_duty_cycle=50.000
CSET clkout1_requested_out_freq=40.000
CSET clkout1_requested_phase=0.000
CSET clkout2_drives=BUFG
CSET clkout2_requested_duty_cycle=50.000
CSET clkout2_requested_out_freq=100.000
CSET clkout2_requested_phase=0.000
CSET clkout2_used=true
CSET clkout3_drives=BUFG
CSET clkout3_requested_duty_cycle=50.000
CSET clkout3_requested_out_freq=100.000
CSET clkout3_requested_phase=0.000
CSET clkout3_used=true
CSET clkout4_drives=BUFG
CSET clkout4_requested_duty_cycle=50.000
CSET clkout4_requested_out_freq=100.000
CSET clkout4_requested_phase=0.000
CSET clkout4_used=false
CSET clkout5_drives=BUFG
CSET clkout5_requested_duty_cycle=50.000
CSET clkout5_requested_out_freq=100.000
CSET clkout5_requested_phase=0.000
CSET clkout5_used=false
CSET clkout6_drives=BUFG
CSET clkout6_requested_duty_cycle=50.000
CSET clkout6_requested_out_freq=100.000
CSET clkout6_requested_phase=0.000
CSET clkout6_used=false
CSET clkout7_drives=BUFG
CSET clkout7_requested_duty_cycle=50.000
CSET clkout7_requested_out_freq=100.000
CSET clkout7_requested_phase=0.000
CSET clkout7_used=false
CSET clock_mgr_type=AUTO
CSET component_name=b200_clk_gen
CSET daddr_port=DADDR
CSET dclk_port=DCLK
CSET dcm_clk_feedback=1X
CSET dcm_clk_out1_port=CLK0
CSET dcm_clk_out2_port=CLKFX
CSET dcm_clk_out3_port=CLKFX
CSET dcm_clk_out4_port=CLK0
CSET dcm_clk_out5_port=CLK0
CSET dcm_clk_out6_port=CLK0
CSET dcm_clkdv_divide=2.0
CSET dcm_clkfx_divide=2
CSET dcm_clkfx_multiply=5
CSET dcm_clkgen_clk_out1_port=CLKFX
CSET dcm_clkgen_clk_out2_port=CLKFX
CSET dcm_clkgen_clk_out3_port=CLKFX
CSET dcm_clkgen_clkfx_divide=1
CSET dcm_clkgen_clkfx_md_max=0.000
CSET dcm_clkgen_clkfx_multiply=4
CSET dcm_clkgen_clkfxdv_divide=2
CSET dcm_clkgen_clkin_period=10.000
CSET dcm_clkgen_notes=None
CSET dcm_clkgen_spread_spectrum=NONE
CSET dcm_clkgen_startup_wait=false
CSET dcm_clkin_divide_by_2=false
CSET dcm_clkin_period=25.000
CSET dcm_clkout_phase_shift=NONE
CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
CSET dcm_notes=None
CSET dcm_phase_shift=0
CSET dcm_pll_cascade=NONE
CSET dcm_startup_wait=false
CSET den_port=DEN
CSET din_port=DIN
CSET dout_port=DOUT
CSET drdy_port=DRDY
CSET dwe_port=DWE
CSET feedback_source=FDBK_AUTO
CSET in_freq_units=Units_MHz
CSET in_jitter_units=Units_UI
CSET input_clk_stopped_port=INPUT_CLK_STOPPED
CSET jitter_options=UI
CSET jitter_sel=No_Jitter
CSET locked_port=LOCKED
CSET mmcm_bandwidth=OPTIMIZED
CSET mmcm_clkfbout_mult_f=4.000
CSET mmcm_clkfbout_phase=0.000
CSET mmcm_clkfbout_use_fine_ps=false
CSET mmcm_clkin1_period=10.000
CSET mmcm_clkin2_period=10.000
CSET mmcm_clkout0_divide_f=4.000
CSET mmcm_clkout0_duty_cycle=0.500
CSET mmcm_clkout0_phase=0.000
CSET mmcm_clkout0_use_fine_ps=false
CSET mmcm_clkout1_divide=1
CSET mmcm_clkout1_duty_cycle=0.500
CSET mmcm_clkout1_phase=0.000
CSET mmcm_clkout1_use_fine_ps=false
CSET mmcm_clkout2_divide=1
CSET mmcm_clkout2_duty_cycle=0.500
CSET mmcm_clkout2_phase=0.000
CSET mmcm_clkout2_use_fine_ps=false
CSET mmcm_clkout3_divide=1
CSET mmcm_clkout3_duty_cycle=0.500
CSET mmcm_clkout3_phase=0.000
CSET mmcm_clkout3_use_fine_ps=false
CSET mmcm_clkout4_cascade=false
CSET mmcm_clkout4_divide=1
CSET mmcm_clkout4_duty_cycle=0.500
CSET mmcm_clkout4_phase=0.000
CSET mmcm_clkout4_use_fine_ps=false
CSET mmcm_clkout5_divide=1
CSET mmcm_clkout5_duty_cycle=0.500
CSET mmcm_clkout5_phase=0.000
CSET mmcm_clkout5_use_fine_ps=false
CSET mmcm_clkout6_divide=1
CSET mmcm_clkout6_duty_cycle=0.500
CSET mmcm_clkout6_phase=0.000
CSET mmcm_clkout6_use_fine_ps=false
CSET mmcm_clock_hold=false
CSET mmcm_compensation=ZHOLD
CSET mmcm_divclk_divide=1
CSET mmcm_notes=None
CSET mmcm_ref_jitter1=0.010
CSET mmcm_ref_jitter2=0.010
CSET mmcm_startup_wait=false
CSET num_out_clks=3
CSET override_dcm=false
CSET override_dcm_clkgen=false
CSET override_mmcm=false
CSET override_pll=false
CSET platform=lin64
CSET pll_bandwidth=OPTIMIZED
CSET pll_clk_feedback=CLKFBOUT
CSET pll_clkfbout_mult=4
CSET pll_clkfbout_phase=0.000
CSET pll_clkin_period=10.000
CSET pll_clkout0_divide=1
CSET pll_clkout0_duty_cycle=0.500
CSET pll_clkout0_phase=0.000
CSET pll_clkout1_divide=1
CSET pll_clkout1_duty_cycle=0.500
CSET pll_clkout1_phase=0.000
CSET pll_clkout2_divide=1
CSET pll_clkout2_duty_cycle=0.500
CSET pll_clkout2_phase=0.000
CSET pll_clkout3_divide=1
CSET pll_clkout3_duty_cycle=0.500
CSET pll_clkout3_phase=0.000
CSET pll_clkout4_divide=1
CSET pll_clkout4_duty_cycle=0.500
CSET pll_clkout4_phase=0.000
CSET pll_clkout5_divide=1
CSET pll_clkout5_duty_cycle=0.500
CSET pll_clkout5_phase=0.000
CSET pll_compensation=SYSTEM_SYNCHRONOUS
CSET pll_divclk_divide=1
CSET pll_notes=None
CSET pll_ref_jitter=0.010
CSET power_down_port=POWER_DOWN
CSET prim_in_freq=40.000
CSET prim_in_jitter=0.010
CSET prim_source=Differential_clock_capable_pin
CSET primary_port=CLK_IN1_40
CSET primitive=MMCM
CSET primtype_sel=PLL_BASE
CSET psclk_port=PSCLK
CSET psdone_port=PSDONE
CSET psen_port=PSEN
CSET psincdec_port=PSINCDEC
CSET relative_inclk=REL_PRIMARY
CSET reset_port=RESET
CSET secondary_in_freq=100.000
CSET secondary_in_jitter=0.010
CSET secondary_port=CLK_IN2
CSET secondary_source=Single_ended_clock_capable_pin
CSET ss_mod_freq=250
CSET ss_mode=CENTER_HIGH
CSET status_port=STATUS
CSET summary_strings=empty
CSET use_clk_valid=false
CSET use_clkfb_stopped=false
CSET use_dyn_phase_shift=false
CSET use_dyn_reconfig=false
CSET use_freeze=false
CSET use_freq_synth=true
CSET use_inclk_stopped=false
CSET use_inclk_switchover=false
CSET use_locked=true
CSET use_max_i_jitter=false
CSET use_min_o_jitter=false
CSET use_min_power=false
CSET use_phase_alignment=true
CSET use_power_down=false
CSET use_reset=true
CSET use_spread_spectrum=false
CSET use_spread_spectrum_1=false
CSET use_status=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-05-10T12:44:55Z
# END Extra information
GENERATE
# CRC: af7323ea
top/b200/coregen/b200_clk_gen.xdc
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# file: b200_clk_gen.xdc
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# Input clock periods. These duplicate the values entered for the
# input clocks. You can use these to time your system
#----------------------------------------------------------------
# Differential clock only needs one constraint
create_clock -name CLK_IN1_P -period 25.0 [get_ports CLK_IN1_P]
set_propagated_clock CLK_IN1_P
set_input_jitter CLK_IN1_P 0.25
set_false_path -from [get_ports "RESET"]
# Derived clock periods. These are commented out because they are
# automatically propogated by the tools
# However, if you'd like to use them for module level testing, you
# can copy them into your module level timing checks
#-----------------------------------------------------------------
#-----------------------------------------------------------------
#-----------------------------------------------------------------
top/b200/coregen/b200_clk_gen/clk_wiz_v3_6_readme.txt
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CHANGE LOG for LogiCORE Clocking Wizard V3.6
Release Date: July 25, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURE HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
Zynq-7000
Defense Grade Zynq-7000Q (XQ)
All Virtex-6 devices
All Spartan-6 devices
................................................................................
3. NEW FEATURE HISTORY
3.1 ISE
- Spread Spectrum support for 7 series MMCME2
- ISE 14.2 software support
................................................................................
4. RESOLVED ISSUES
4.1 ISE
Resolved issue with Virtex6 MMCM instantiation for VHDL project
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
................................................................................
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
================================================================================
................................................................................
8. LEGAL DISCLAIMER
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
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CHANGE LOG for LogiCORE Clocking Wizard V3.6
Release Date: July 25, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURE HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
Zynq-7000
Defense Grade Zynq-7000Q (XQ)
All Virtex-6 devices
All Spartan-6 devices
................................................................................
3. NEW FEATURE HISTORY
3.1 ISE
- Spread Spectrum support for 7 series MMCME2
- ISE 14.2 software support
................................................................................
4. RESOLVED ISSUES
4.1 ISE
Resolved issue with Virtex6 MMCM instantiation for VHDL project
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
................................................................................
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
================================================================================
................................................................................
8. LEGAL DISCLAIMER
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
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</HEAD>
<BODY>
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
CHANGE LOG for LogiCORE Clocking Wizard V3.6
Release Date: July 25, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURE HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
For system requirements:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
solution. For the latest core updates, see the product page at:
<A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A>
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
Zynq-7000
Defense Grade Zynq-7000Q (XQ)
All Virtex-6 devices
All Spartan-6 devices
................................................................................
3. NEW FEATURE HISTORY
3.1 ISE
- Spread Spectrum support for 7 series MMCME2
- ISE 14.2 software support
................................................................................
4. RESOLVED ISSUES
4.1 ISE
Resolved issue with Virtex6 MMCM instantiation for VHDL project
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes Guide
located at
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
................................................................................
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
================================================================================
................................................................................
8. LEGAL DISCLAIMER
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
</FONT>
</PRE>
</BODY>
</HTML>
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# file: b200_clk_gen_exdes.ucf
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# Input clock periods. These duplicate the values entered for the
# input clocks. You can use these to time your system
#----------------------------------------------------------------
# Differential clock only needs one constraint
NET "CLK_IN1_P" TNM_NET = "CLK_IN1_P";
TIMESPEC "TS_CLK_IN1_P" = PERIOD "CLK_IN1_P" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps;
# Derived clock periods. These are commented out because they are
# automatically propogated by the tools
# However, if you'd like to use them for module level testing, you
# can copy them into your module level timing checks
#-----------------------------------------------------------------
# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 40.000 MHz;
# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz;
# NET "clk_int[3]" TNM_NET = "CLK_OUT3";
# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz;
# FALSE PATH constraints
PIN "COUNTER_RESET" TIG;
PIN "RESET" TIG;
top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.v
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// file: b200_clk_gen_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module b200_clk_gen_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1_P,
input CLK_IN1_N,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [3:1] CLK_OUT,
// High bits of counters driven by clocks
output [3:1] COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 3;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk_n;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
b200_clk_gen clknetwork
(// Clock in ports
.CLK_IN1_40_P (CLK_IN1_P),
.CLK_IN1_40_N (CLK_IN1_N),
// Clock out ports
.CLK_OUT1_40_int (clk_int[1]),
.CLK_OUT2_100_gpif (clk_int[2]),
.CLK_OUT3_100_bus (clk_int[3]),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
genvar clk_out_pins;
generate
for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1)
begin: gen_outclk_oddr
assign clk_n[clk_out_pins] = ~clk[clk_out_pins];
ODDR2 clkout_oddr
(.Q (CLK_OUT[clk_out_pins1]),
.C0 (clk[clk_out_pins]),
.C1 (clk_n[clk_out_pins]),
.CE (1'b1),
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0),
.S (1'b0));
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
assign clk[3] = clk_int[3];
// Reset synchronizer
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen]<= 1'b1;
rst_sync_int1[count_gen]<= 1'b1;
rst_sync_int2[count_gen]<= 1'b1;
end
else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.xdc
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# file: b200_clk_gen_exdes.xdc
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# Input clock periods. These duplicate the values entered for the
# input clocks. You can use these to time your system
#----------------------------------------------------------------
# Differential clock only needs one constraint
create_clock -name CLK_IN1_P -period 25.0 [get_ports CLK_IN1_P]
set_propagated_clock CLK_IN1_P
set_input_jitter CLK_IN1_P 0.25
# FALSE PATH constraint added on COUNTER_RESET
set_false_path -from [get_ports "COUNTER_RESET"]
set_false_path -from [get_ports "RESET"]
# Derived clock periods. These are commented out because they are
# automatically propogated by the tools
# However, if you'd like to use them for module level testing, you
# can copy them into your module level timing checks
#-----------------------------------------------------------------
#-----------------------------------------------------------------
#-----------------------------------------------------------------
top/b200/coregen/b200_clk_gen/implement/implement.bat
Executable
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REM file: implement.bat
REM
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
REM
REM This file contains confidential and proprietary information
REM of Xilinx, Inc. and is protected under U.S. and
REM international copyright and other intellectual property
REM laws.
REM
REM DISCLAIMER
REM This disclaimer is not a license and does not grant any
REM rights to the materials distributed herewith. Except as
REM otherwise provided in a valid license issued to you by
REM Xilinx, and to the maximum extent permitted by applicable
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
REM (2) Xilinx shall not be liable (whether in contract or tort,
REM including negligence, or under any other theory of
REM liability) for any loss or damage of any kind or nature
REM related to, arising under or in connection with these
REM materials, including for any direct, or any indirect,
REM special, incidental, or consequential loss or damage
REM (including loss of data, profits, goodwill, or any type of
REM loss or damage suffered as a result of any action brought
REM by a third party) even if such damage or loss was
REM reasonably foreseeable or Xilinx had been advised of the
REM possibility of the same.
REM
REM CRITICAL APPLICATIONS
REM Xilinx products are not designed or intended to be fail-
REM safe, or for use in any application requiring fail-safe
REM performance, such as life-support or safety devices or
REM systems, Class III medical devices, nuclear facilities,
REM applications related to the deployment of airbags, or any
REM other applications that could lead to death, personal
REM injury, or severe property or environmental damage
REM (individually and collectively, "Critical
REM Applications"). Customer assumes the sole risk and
REM liability of any use of Xilinx products in Critical
REM Applications, subject only to applicable laws and
REM regulations governing limitations on product liability.
REM
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
REM PART OF THIS FILE AT ALL TIMES.
REM
REM -----------------------------------------------------------------------------
REM Script to synthesize and implement the RTL provided for the clocking wizard
REM -----------------------------------------------------------------------------
REM Clean up the results directory
rmdir /S /Q results
mkdir results
REM Copy unisim_comp.v file to results directory
copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
REM Synthesize the Verilog Wrapper Files
echo 'Synthesizing Clocking Wizard design with XST'
xst -ifn xst.scr
move b200_clk_gen_exdes.ngc results\
REM Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\b200_clk_gen_exdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -uc b200_clk_gen_exdes.ucf b200_clk_gen_exdes
echo 'Running map'
map -timing -pr b b200_clk_gen_exdes -o mapped.ncd
echo 'Running par'
par -w mapped.ncd routed mapped.pcf
echo 'Running trce'
trce -e 10 routed -o routed mapped.pcf
echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level model for the clocking wizard example design'
netgen -ofmt verilog -sim -sdf_anno false -tm b200_clk_gen_exdes -w routed.ncd routed.v
cd ..
top/b200/coregen/b200_clk_gen/implement/implement.sh
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#!/bin/sh
# file: implement.sh
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
#-----------------------------------------------------------------------------
# Script to synthesize and implement the RTL provided for the clocking wizard
#-----------------------------------------------------------------------------
# Clean up the results directory
rm -rf results
mkdir results
# Copy unisim_comp.v file to results directory
cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
# Synthesize the Verilog Wrapper Files
echo 'Synthesizing Clocking Wizard design with XST'
xst -ifn xst.scr
mv b200_clk_gen_exdes.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/b200_clk_gen_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -uc b200_clk_gen_exdes.ucf b200_clk_gen_exdes
echo 'Running map'
map -timing b200_clk_gen_exdes -o mapped.ncd
echo 'Running par'
par -w mapped.ncd routed mapped.pcf
echo 'Running trce'
trce -e 10 routed -o routed mapped.pcf
echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level model for the clocking wizard example design'
netgen -ofmt verilog -sim -sdf_anno false -tm b200_clk_gen_exdes -w routed.ncd routed.v
cd ..
top/b200/coregen/b200_clk_gen/implement/planAhead_ise.bat
Executable
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REM file: planAhead_ise.bat
REM
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
REM
REM This file contains confidential and proprietary information
REM of Xilinx, Inc. and is protected under U.S. and
REM international copyright and other intellectual property
REM laws.
REM
REM DISCLAIMER
REM This disclaimer is not a license and does not grant any
REM rights to the materials distributed herewith. Except as
REM otherwise provided in a valid license issued to you by
REM Xilinx, and to the maximum extent permitted by applicable
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
REM (2) Xilinx shall not be liable (whether in contract or tort,
REM including negligence, or under any other theory of
REM liability) for any loss or damage of any kind or nature
REM related to, arising under or in connection with these
REM materials, including for any direct, or any indirect,
REM special, incidental, or consequential loss or damage
REM (including loss of data, profits, goodwill, or any type of
REM loss or damage suffered as a result of any action brought
REM by a third party) even if such damage or loss was
REM reasonably foreseeable or Xilinx had been advised of the
REM possibility of the same.
REM
REM CRITICAL APPLICATIONS
REM Xilinx products are not designed or intended to be fail-
REM safe, or for use in any application requiring fail-safe
REM performance, such as life-support or safety devices or
REM systems, Class III medical devices, nuclear facilities,
REM applications related to the deployment of airbags, or any
REM other applications that could lead to death, personal
REM injury, or severe property or environmental damage
REM (individually and collectively, "Critical
REM Applications"). Customer assumes the sole risk and
REM liability of any use of Xilinx products in Critical
REM Applications, subject only to applicable laws and
REM regulations governing limitations on product liability.
REM
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
REM PART OF THIS FILE AT ALL TIMES.
REM
REM-----------------------------------------------------------------------------
REM Script to synthesize and implement the RTL provided for the clocking wizard
REM-----------------------------------------------------------------------------
del \f results
mkdir results
cd results
planAhead -mode batch -source ..\planAhead_ise.tcl
top/b200/coregen/b200_clk_gen/implement/planAhead_ise.sh
Executable
+59
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#!/bin/sh
# file: planAhead_ise.sh
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
#-----------------------------------------------------------------------------
# Script to synthesize and implement the RTL provided for the clocking wizard
#-----------------------------------------------------------------------------
rm -rf results
mkdir results
cd results
planAhead -mode batch -source ../planAhead_ise.tcl
top/b200/coregen/b200_clk_gen/implement/planAhead_ise.tcl
Executable
+78
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# file: planAhead_ise.tcl
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
set projDir [file dirname [info script]]
set projName b200_clk_gen
set topName b200_clk_gen_exdes
set device xc6slx75csg484-2
create_project $projName $projDir/results/$projName -part $device
set_property design_mode RTL [get_filesets sources_1]
## Source files
#set verilogSources [glob $srcDir/*.v]
import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/b200_clk_gen_exdes.v
import_files -fileset [get_filesets sources_1] -force -norecurse ../../../b200_clk_gen.v
#UCF file
import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/b200_clk_gen_exdes.ucf
set_property top $topName [get_property srcset [current_run]]
launch_runs -runs synth_1
wait_on_run synth_1
set_property add_step Bitgen [get_runs impl_1]
launch_runs -runs impl_1
wait_on_run impl_1
top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.bat
Executable
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REM file: planAhead_rdn.sh
REM
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
REM
REM This file contains confidential and proprietary information
REM of Xilinx, Inc. and is protected under U.S. and
REM international copyright and other intellectual property
REM laws.
REM
REM DISCLAIMER
REM This disclaimer is not a license and does not grant any
REM rights to the materials distributed herewith. Except as
REM otherwise provided in a valid license issued to you by
REM Xilinx, and to the maximum extent permitted by applicable
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
REM (2) Xilinx shall not be liable (whether in contract or tort,
REM including negligence, or under any other theory of
REM liability) for any loss or damage of any kind or nature
REM related to, arising under or in connection with these
REM materials, including for any direct, or any indirect,
REM special, incidental, or consequential loss or damage
REM (including loss of data, profits, goodwill, or any type of
REM loss or damage suffered as a result of any action brought
REM by a third party) even if such damage or loss was
REM reasonably foreseeable or Xilinx had been advised of the
REM possibility of the same.
REM
REM CRITICAL APPLICATIONS
REM Xilinx products are not designed or intended to be fail-
REM safe, or for use in any application requiring fail-safe
REM performance, such as life-support or safety devices or
REM systems, Class III medical devices, nuclear facilities,
REM applications related to the deployment of airbags, or any
REM other applications that could lead to death, personal
REM injury, or severe property or environmental damage
REM (individually and collectively, "Critical
REM Applications"). Customer assumes the sole risk and
REM liability of any use of Xilinx products in Critical
REM Applications, subject only to applicable laws and
REM regulations governing limitations on product liability.
REM
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
REM PART OF THIS FILE AT ALL TIMES.
REM
REM-----------------------------------------------------------------------------
REM Script to synthesize and implement the RTL provided for the XADC wizard
REM-----------------------------------------------------------------------------
del \f results
mkdir results
cd results
planAhead -mode batch -source ..\planAhead_rdn.tcl
top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.sh
Executable
+57
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#!/bin/sh
# file: planAhead_rdn.sh
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
#-----------------------------------------------------------------------------
# Script to synthesize and implement the RTL provided for the XADC wizard
#-----------------------------------------------------------------------------
rm -rf results
mkdir results
cd results
planAhead -mode batch -source ../planAhead_rdn.tcl
top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.tcl
Executable
+69
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# file : planAhead_rdn.tcl
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
set device xc6slx75csg484-2
set projName b200_clk_gen
set design b200_clk_gen
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module b200_clk_gen_exdes
set_property top b200_clk_gen_exdes [get_property srcset [current_run]]
add_files -norecurse {../../../b200_clk_gen.v}
add_files -norecurse {../../example_design/b200_clk_gen_exdes.v}
import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/b200_clk_gen_exdes.xdc}
synth_design
opt_design
place_design
route_design
write_sdf -rename_top_module b200_clk_gen_exdes -file routed.sdf
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module b200_clk_gen_exdes -file routed.v
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file report.drc
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
top/b200/coregen/b200_clk_gen/implement/xst.prj
Executable
+2
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verilog work ../../b200_clk_gen.v
verilog work ../example_design/b200_clk_gen_exdes.v
top/b200/coregen/b200_clk_gen/implement/xst.scr
Executable
+9
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@@ -0,0 +1,9 @@
run
-ifmt MIXED
-top b200_clk_gen_exdes
-p xc6slx75-csg484-2
-ifn xst.prj
-ofn b200_clk_gen_exdes
-keep_hierarchy soft
-equivalent_register_removal no
-max_fanout 65535
top/b200/coregen/b200_clk_gen/simulation/b200_clk_gen_tb.v
Executable
+146
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@@ -0,0 +1,146 @@
// file: b200_clk_gen_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module b200_clk_gen_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 25.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
wire CLK_IN1_P = CLK_IN1;
wire CLK_IN1_N = ~CLK_IN1;
// The high bits of the sampling counters
wire [3:1] COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [3:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
b200_clk_gen_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1_P (CLK_IN1_P),
.CLK_IN1_N (CLK_IN1_N),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Freq Check
endmodule
top/b200/coregen/b200_clk_gen/simulation/functional/simcmds.tcl
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# file: simcmds.tcl
# create the simulation script
vcd dumpfile isim.vcd
vcd dumpvars -m /b200_clk_gen_tb -l 0
wave add /
run 50000ns
quit
top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.bat
Executable
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REM file: simulate_isim.bat
REM
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
REM
REM This file contains confidential and proprietary information
REM of Xilinx, Inc. and is protected under U.S. and
REM international copyright and other intellectual property
REM laws.
REM
REM DISCLAIMER
REM This disclaimer is not a license and does not grant any
REM rights to the materials distributed herewith. Except as
REM otherwise provided in a valid license issued to you by
REM Xilinx, and to the maximum extent permitted by applicable
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
REM (2) Xilinx shall not be liable (whether in contract or tort,
REM including negligence, or under any other theory of
REM liability) for any loss or damage of any kind or nature
REM related to, arising under or in connection with these
REM materials, including for any direct, or any indirect,
REM special, incidental, or consequential loss or damage
REM (including loss of data, profits, goodwill, or any type of
REM loss or damage suffered as a result of any action brought
REM by a third party) even if such damage or loss was
REM reasonably foreseeable or Xilinx had been advised of the
REM possibility of the same.
REM
REM CRITICAL APPLICATIONS
REM Xilinx products are not designed or intended to be fail-
REM safe, or for use in any application requiring fail-safe
REM performance, such as life-support or safety devices or
REM systems, Class III medical devices, nuclear facilities,
REM applications related to the deployment of airbags, or any
REM other applications that could lead to death, personal
REM injury, or severe property or environmental damage
REM (individually and collectively, "Critical
REM Applications"). Customer assumes the sole risk and
REM liability of any use of Xilinx products in Critical
REM Applications, subject only to applicable laws and
REM regulations governing limitations on product liability.
REM
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
REM PART OF THIS FILE AT ALL TIMES.
REM
vlogcomp -work work %XILINX%\verilog\src\glbl.v
vlogcomp -work work ..\..\..\b200_clk_gen.v
vlogcomp -work work ..\..\example_design\b200_clk_gen_exdes.v
vlogcomp -work work ..\b200_clk_gen_tb.v
REM compile the project
fuse work.b200_clk_gen_tb work.glbl -L unisims_ver -o b200_clk_gen_isim.exe
REM run the simulation script
.\b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl
top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.sh
Executable
+61
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# file: simulate_isim.sh
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# lin64
# create the project
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp -work work ../../../b200_clk_gen.v
vlogcomp -work work ../../example_design/b200_clk_gen_exdes.v
vlogcomp -work work ../b200_clk_gen_tb.v
# compile the project
fuse work.b200_clk_gen_tb work.glbl -L unisims_ver -o b200_clk_gen_isim.exe
# run the simulation script
./b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl
top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.bat
Executable
+61
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REM file: simulate_mti.bat
REM
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
REM
REM This file contains confidential and proprietary information
REM of Xilinx, Inc. and is protected under U.S. and
REM international copyright and other intellectual property
REM laws.
REM
REM DISCLAIMER
REM This disclaimer is not a license and does not grant any
REM rights to the materials distributed herewith. Except as
REM otherwise provided in a valid license issued to you by
REM Xilinx, and to the maximum extent permitted by applicable
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
REM (2) Xilinx shall not be liable (whether in contract or tort,
REM including negligence, or under any other theory of
REM liability) for any loss or damage of any kind or nature
REM related to, arising under or in connection with these
REM materials, including for any direct, or any indirect,
REM special, incidental, or consequential loss or damage
REM (including loss of data, profits, goodwill, or any type of
REM loss or damage suffered as a result of any action brought
REM by a third party) even if such damage or loss was
REM reasonably foreseeable or Xilinx had been advised of the
REM possibility of the same.
REM
REM CRITICAL APPLICATIONS
REM Xilinx products are not designed or intended to be fail-
REM safe, or for use in any application requiring fail-safe
REM performance, such as life-support or safety devices or
REM systems, Class III medical devices, nuclear facilities,
REM applications related to the deployment of airbags, or any
REM other applications that could lead to death, personal
REM injury, or severe property or environmental damage
REM (individually and collectively, "Critical
REM Applications"). Customer assumes the sole risk and
REM liability of any use of Xilinx products in Critical
REM Applications, subject only to applicable laws and
REM regulations governing limitations on product liability.
REM
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
REM PART OF THIS FILE AT ALL TIMES.
REM
REM set up the working directory
vlib work
REM compile all of the files
vlog -work work %XILINX%\verilog\src\glbl.v
vlog -work work ..\..\..\b200_clk_gen.v
vlog -work work ..\..\example_design\b200_clk_gen_exdes.v
vlog -work work ..\b200_clk_gen_tb.v
REM run the simulation
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b200_clk_gen_tb work.glbl
top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.do
Executable
+65
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# file: simulate_mti.do
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# set up the working directory
set work work
vlib work
# compile all of the files
vlog -work work $env(XILINX)/verilog/src/glbl.v
vlog -work work ../../../b200_clk_gen.v
vlog -work work ../../example_design/b200_clk_gen_exdes.v
vlog -work work ../b200_clk_gen_tb.v
# run the simulation
vsim -t ps -voptargs="+acc" -L unisims_ver work.b200_clk_gen_tb work.glbl
do wave.do
log b200_clk_gen_tb/dut/counter
log -r /*
run 50000ns
top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.sh
Executable
+61
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#/bin/sh
# file: simulate_mti.sh
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# set up the working directory
set work work
vlib work
# compile all of the files
vlog -work work $XILINX/verilog/src/glbl.v
vlog -work work ../../../b200_clk_gen.v
vlog -work work ../../example_design/b200_clk_gen_exdes.v
vlog -work work ../b200_clk_gen_tb.v
# run the simulation
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b200_clk_gen_tb work.glbl
top/b200/coregen/b200_clk_gen/simulation/functional/simulate_ncsim.sh
Executable
+62
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#/bin/sh
# file: simulate_ncsim.sh
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# set up the working directory
mkdir work
# compile all of the files
ncvlog -work work ${XILINX}/verilog/src/glbl.v
ncvlog -work work ../../../b200_clk_gen.v
ncvlog -work work ../../example_design/b200_clk_gen_exdes.v
ncvlog -work work ../b200_clk_gen_tb.v
# elaborate and run the simulation
ncelab -work work -access +wc work.b200_clk_gen_tb work.glbl
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.b200_clk_gen_tb
top/b200/coregen/b200_clk_gen/simulation/functional/simulate_vcs.sh
Executable
+72
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#!/bin/sh
# file: simulate_vcs.sh
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# remove old files
rm -rf simv* csrc DVEfiles AN.DB
# compile all of the files
# Note that -sverilog is not strictly required- You can
# remove the -sverilog if you change the type of the
# localparam for the periods in the testbench file to
# [63:0] from time
vlogan -sverilog \
${XILINX}/verilog/src/glbl.v \
../../../b200_clk_gen.v \
../../example_design/b200_clk_gen_exdes.v \
../b200_clk_gen_tb.v
# prepare the simulation
vcs +vcs+lic+wait -debug b200_clk_gen_tb glbl
# run the simulation
./simv -ucli -i ucli_commands.key
# launch the viewer
dve -vpd vcdplus.vpd -session vcs_session.tcl
top/b200/coregen/b200_clk_gen/simulation/functional/ucli_commands.key
Executable
+5
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call {$vcdpluson}
call {$vcdplusmemon(b200_clk_gen_tb.dut.counter)}
run
call {$vcdplusclose}
quit
top/b200/coregen/b200_clk_gen/simulation/functional/vcs_session.tcl
Executable
+18
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gui_open_window Wave
gui_sg_create b200_clk_gen_group
gui_list_add_group -id Wave.1 {b200_clk_gen_group}
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.test_phase}
gui_set_radix -radix {ascii} -signals {b200_clk_gen_tb.test_phase}
gui_sg_addsignal -group b200_clk_gen_group {{Input_clocks}} -divider
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.CLK_IN1}
gui_sg_addsignal -group b200_clk_gen_group {{Output_clocks}} -divider
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.dut.clk}
gui_list_expand -id Wave.1 b200_clk_gen_tb.dut.clk
gui_sg_addsignal -group b200_clk_gen_group {{Status_control}} -divider
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.RESET}
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.LOCKED}
gui_sg_addsignal -group b200_clk_gen_group {{Counters}} -divider
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.COUNT}
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.dut.counter}
gui_list_expand -id Wave.1 b200_clk_gen_tb.dut.counter
gui_zoom -window Wave.1 -full
top/b200/coregen/b200_clk_gen/simulation/functional/wave.do
Executable
+60
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# file: wave.do
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
add wave -noupdate -format Literal -radix ascii /b200_clk_gen_tb/test_phase
add wave -noupdate -divider {Input clocks}
add wave -noupdate -format Logic /b200_clk_gen_tb/CLK_IN1
add wave -noupdate -divider {Output clocks}
add wave -noupdate -format Literal -expand /b200_clk_gen_tb/dut/clk
add wave -noupdate -divider Status/control
add wave -noupdate -format Logic /b200_clk_gen_tb/RESET
add wave -noupdate -format Logic /b200_clk_gen_tb/LOCKED
add wave -noupdate -divider Counters
add wave -noupdate -format Literal -radix hexadecimal /b200_clk_gen_tb/COUNT
add wave -noupdate -format Literal -radix hexadecimal -expand /b200_clk_gen_tb/dut/counter
top/b200/coregen/b200_clk_gen/simulation/functional/wave.sv
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# file: wave.sv
#
# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# Get the windows set up
#
if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {
window geometry "Design Browser 1" 1054x819+536+322
}
window target "Design Browser 1" on
browser using {Design Browser 1}
browser set \
-scope nc::b200_clk_gen_tb
browser yview see nc::b200_clk_gen_tb
browser timecontrol set -lock 0
if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
window geometry "Waveform 1" 1010x600+0+541
}
window target "Waveform 1" on
waveform using {Waveform 1}
waveform sidebar visibility partial
waveform set \
-primarycursor TimeA \
-signalnames name \
-signalwidth 175 \
-units ns \
-valuewidth 75
cursor set -using TimeA -time 0
waveform baseline set -time 0
waveform xview limits 0 20000n
#
# Define signal groups
#
catch {group new -name {Output clocks} -overlay 0}
catch {group new -name {Status/control} -overlay 0}
catch {group new -name {Counters} -overlay 0}
set id [waveform add -signals [list {nc::b200_clk_gen_tb.CLK_IN1}]]
group using {Output clocks}
group set -overlay 0
group set -comment {}
group clear 0 end
group insert \
{b200_clk_gen_tb.dut.clk[1]} \
{b200_clk_gen_tb.dut.clk[2]} \ {b200_clk_gen_tb.dut.clk[3]}
group using {Counters}
group set -overlay 0
group set -comment {}
group clear 0 end
group insert \
{b200_clk_gen_tb.dut.counter[1]} \
{b200_clk_gen_tb.dut.counter[2]} \ {b200_clk_gen_tb.dut.counter[3]}
group using {Status/control}
group set -overlay 0
group set -comment {}
group clear 0 end
group insert \
{nc::b200_clk_gen_tb.RESET} {nc::b200_clk_gen_tb.LOCKED}
set id [waveform add -signals [list {nc::b200_clk_gen_tb.COUNT} ]]
set id [waveform add -signals [list {nc::b200_clk_gen_tb.test_phase} ]]
waveform format $id -radix %a
set groupId [waveform add -groups {{Input clocks}}]
set groupId [waveform add -groups {{Output clocks}}]
set groupId [waveform add -groups {{Status/control}}]
set groupId [waveform add -groups {{Counters}}]
top/b200/coregen/b200_clk_gen/simulation/timing/b200_clk_gen_tb.v
Executable
+160
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// file: b200_clk_gen_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module b200_clk_gen_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 25.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
wire CLK_IN1_P = CLK_IN1;
wire CLK_IN1_N = ~CLK_IN1;
// The high bits of the sampling counters
wire [3:1] COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [3:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
b200_clk_gen_exdes
dut
(// Clock in ports
.CLK_IN1_P (CLK_IN1_P),
.CLK_IN1_N (CLK_IN1_N),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Freq Check
endmodule
top/b200/coregen/b200_clk_gen/simulation/timing/sdf_cmd_file
Executable
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COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
SCOPE = b200_clk_gen_tb.dut;
top/b200/coregen/b200_clk_gen/simulation/timing/simcmds.tcl
Executable
+9
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# file: simcmds.tcl
# create the simulation script
vcd dumpfile isim.vcd
vcd dumpvars -m /b200_clk_gen_tb -l 0
wave add /
run 50000ns
quit
top/b200/coregen/b200_clk_gen/simulation/timing/simulate_isim.sh
Executable
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# file: simulate_isim.sh
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# create the project
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
vlogcomp -work work ../../implement/results/routed.v
vlogcomp -work work b200_clk_gen_tb.v
# compile the project
fuse work.b200_clk_gen_tb work.glbl -L secureip -L simprims_ver -o b200_clk_gen_isim.exe
# run the simulation script
./b200_clk_gen_isim.exe -tclbatch simcmds.tcl -sdfmax /b200_clk_gen_tb/dut=../../implement/results/routed.sdf
# run the simulation script
#./b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl
top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.bat
Executable
+59
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REM file: simulate_mti.bat
REM
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
REM
REM This file contains confidential and proprietary information
REM of Xilinx, Inc. and is protected under U.S. and
REM international copyright and other intellectual property
REM laws.
REM
REM DISCLAIMER
REM This disclaimer is not a license and does not grant any
REM rights to the materials distributed herewith. Except as
REM otherwise provided in a valid license issued to you by
REM Xilinx, and to the maximum extent permitted by applicable
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
REM (2) Xilinx shall not be liable (whether in contract or tort,
REM including negligence, or under any other theory of
REM liability) for any loss or damage of any kind or nature
REM related to, arising under or in connection with these
REM materials, including for any direct, or any indirect,
REM special, incidental, or consequential loss or damage
REM (including loss of data, profits, goodwill, or any type of
REM loss or damage suffered as a result of any action brought
REM by a third party) even if such damage or loss was
REM reasonably foreseeable or Xilinx had been advised of the
REM possibility of the same.
REM
REM CRITICAL APPLICATIONS
REM Xilinx products are not designed or intended to be fail-
REM safe, or for use in any application requiring fail-safe
REM performance, such as life-support or safety devices or
REM systems, Class III medical devices, nuclear facilities,
REM applications related to the deployment of airbags, or any
REM other applications that could lead to death, personal
REM injury, or severe property or environmental damage
REM (individually and collectively, "Critical
REM Applications"). Customer assumes the sole risk and
REM liability of any use of Xilinx products in Critical
REM Applications, subject only to applicable laws and
REM regulations governing limitations on product liability.
REM
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
REM PART OF THIS FILE AT ALL TIMES.
REM
# set up the working directory
set work work
vlib work
REM compile all of the files
vlog -work work %XILINX%\verilog\src\glbl.v
vlog -work work ..\..\implement\results\routed.v
vlog -work work b200_clk_gen_tb.v
REM run the simulation
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl
top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.do
Executable
+65
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# file: simulate_mti.do
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# set up the working directory
set work work
vlib work
# compile all of the files
vlog -work work $env(XILINX)/verilog/src/glbl.v
vlog -work work ../../implement/results/routed.v
vlog -work work b200_clk_gen_tb.v
# run the simulation
vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl
#do wave.do
#log -r /*
run 50000ns
top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.sh
Executable
+61
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#/bin/sh
# file: simulate_mti.sh
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# set up the working directory
set work work
vlib work
# compile all of the files
vlog -work work $XILINX/verilog/src/glbl.v
vlog -work work ../../implement/results/routed.v
vlog -work work b200_clk_gen_tb.v
# run the simulation
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl
top/b200/coregen/b200_clk_gen/simulation/timing/simulate_ncsim.sh
Executable
+64
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#!/bin/sh
# file: simulate_ncsim.sh
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# set up the working directory
mkdir work
# compile all of the files
ncvlog -work work ${XILINX}/verilog/src/glbl.v
ncvlog -work work ../../implement/results/routed.v
ncvlog -work work b200_clk_gen_tb.v
# elaborate and run the simulation
ncsdfc ../../implement/results/routed.sdf
ncelab -work work -access +wc -pulse_r 10 -nonotifier work.b200_clk_gen_tb work.glbl -sdf_cmd_file sdf_cmd_file
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.b200_clk_gen_tb
top/b200/coregen/b200_clk_gen/simulation/timing/simulate_vcs.sh
Executable
+72
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#!/bin/sh
# file: simulate_vcs.sh
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# remove old files
rm -rf simv* csrc DVEfiles AN.DB
# compile all of the files
# Note that -sverilog is not strictly required- You can
# remove the -sverilog if you change the type of the
# localparam for the periods in the testbench file to
# [63:0] from time
vlogan -sverilog \
b200_clk_gen_tb.v \
../../implement/results/routed.v
# prepare the simulation
vcs -sdf max:b200_clk_gen_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
+libext+.v -debug b200_clk_gen_tb.v ../../implement/results/routed.v
# run the simulation
./simv -ucli -i ucli_commands.key
# launch the viewer
#dve -vpd vcdplus.vpd -session vcs_session.tcl
top/b200/coregen/b200_clk_gen/simulation/timing/ucli_commands.key
Executable
+5
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@@ -0,0 +1,5 @@
call {$vcdpluson}
run 50000ns
call {$vcdplusclose}
quit
top/b200/coregen/b200_clk_gen/simulation/timing/vcs_session.tcl
Executable
+1
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@@ -0,0 +1 @@
gui_open_window Wave
top/b200/coregen/b200_clk_gen/simulation/timing/wave.do
Executable
+72
View File
@@ -0,0 +1,72 @@
# file: wave.do
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /b200_clk_gen_tb/CLK_IN1
add wave -noupdate /b200_clk_gen_tb/COUNT
add wave -noupdate /b200_clk_gen_tb/LOCKED
add wave -noupdate /b200_clk_gen_tb/RESET
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
configure wave -namecolwidth 238
configure wave -valuecolwidth 107
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {74848022 ps}
top/b200/coregen/b200_clk_gen_flist.txt
+53
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@@ -0,0 +1,53 @@
# Output products list for <b200_clk_gen>
b200_clk_gen/clk_wiz_v3_6_readme.txt
b200_clk_gen/doc/clk_wiz_v3_6_readme.txt
b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html
b200_clk_gen/doc/pg065_clk_wiz.pdf
b200_clk_gen/example_design/b200_clk_gen_exdes.ucf
b200_clk_gen/example_design/b200_clk_gen_exdes.v
b200_clk_gen/example_design/b200_clk_gen_exdes.xdc
b200_clk_gen/implement/implement.bat
b200_clk_gen/implement/implement.sh
b200_clk_gen/implement/planAhead_ise.bat
b200_clk_gen/implement/planAhead_ise.sh
b200_clk_gen/implement/planAhead_ise.tcl
b200_clk_gen/implement/planAhead_rdn.bat
b200_clk_gen/implement/planAhead_rdn.sh
b200_clk_gen/implement/planAhead_rdn.tcl
b200_clk_gen/implement/xst.prj
b200_clk_gen/implement/xst.scr
b200_clk_gen/simulation/b200_clk_gen_tb.v
b200_clk_gen/simulation/functional/simcmds.tcl
b200_clk_gen/simulation/functional/simulate_isim.bat
b200_clk_gen/simulation/functional/simulate_isim.sh
b200_clk_gen/simulation/functional/simulate_mti.bat
b200_clk_gen/simulation/functional/simulate_mti.do
b200_clk_gen/simulation/functional/simulate_mti.sh
b200_clk_gen/simulation/functional/simulate_ncsim.sh
b200_clk_gen/simulation/functional/simulate_vcs.sh
b200_clk_gen/simulation/functional/ucli_commands.key
b200_clk_gen/simulation/functional/vcs_session.tcl
b200_clk_gen/simulation/functional/wave.do
b200_clk_gen/simulation/functional/wave.sv
b200_clk_gen/simulation/timing/b200_clk_gen_tb.v
b200_clk_gen/simulation/timing/sdf_cmd_file
b200_clk_gen/simulation/timing/simcmds.tcl
b200_clk_gen/simulation/timing/simulate_isim.sh
b200_clk_gen/simulation/timing/simulate_mti.bat
b200_clk_gen/simulation/timing/simulate_mti.do
b200_clk_gen/simulation/timing/simulate_mti.sh
b200_clk_gen/simulation/timing/simulate_ncsim.sh
b200_clk_gen/simulation/timing/simulate_vcs.sh
b200_clk_gen/simulation/timing/ucli_commands.key
b200_clk_gen/simulation/timing/vcs_session.tcl
b200_clk_gen/simulation/timing/wave.do
b200_clk_gen.asy
b200_clk_gen.gise
b200_clk_gen.ucf
b200_clk_gen.v
b200_clk_gen.veo
b200_clk_gen.xco
b200_clk_gen.xdc
b200_clk_gen.xise
b200_clk_gen_flist.txt
b200_clk_gen_xmdf.tcl
top/b200/coregen/b200_clk_gen_xmdf.tcl
Executable
+144
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@@ -0,0 +1,144 @@
# The package naming convention is <core_name>_xmdf
package provide b200_clk_gen_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::b200_clk_gen_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::b200_clk_gen_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_clk_gen
}
# ::b200_clk_gen_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::b200_clk_gen_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/clk_wiz_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/example_design/b200_clk_gen_exdes.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/doc/clk_wiz_ds709.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/doc/clk_wiz_gsg521.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/example_design/b200_clk_gen_exdes.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/implement.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/implement.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/xst.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/xst.scr
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/b200_clk_gen_tb.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simcmds.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_isim.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_mti.do
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_ncsim.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_vcs.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/ucli_commands.key
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/vcs_session.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/wave.do
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/wave.sv
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.ejp
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_clk_gen
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/b200/coregen/chipscope_icon.asy
+9
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@@ -0,0 +1,9 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 chipscope_icon
RECTANGLE Normal 32 32 544 864
LINE Wide 576 112 544 112
PIN 576 112 RIGHT 36
PINATTR PinName control0[35:0]
PINATTR Polarity BOTH
top/b200/coregen/chipscope_icon.constraints/chipscope_icon.ucf
+9
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@@ -0,0 +1,9 @@
NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
#Update Constraints
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
NET "U0/iSHIFT_OUT" TIG ;
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
top/b200/coregen/chipscope_icon.constraints/chipscope_icon.xdc
+7
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@@ -0,0 +1,7 @@
# icon XDC
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
top/b200/coregen/chipscope_icon.ncf
View File
top/b200/coregen/chipscope_icon.ngc
+3
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File diff suppressed because one or more lines are too long
top/b200/coregen/chipscope_icon.ucf
+9
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@@ -0,0 +1,9 @@
NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
#Update Constraints
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
NET "U0/iSHIFT_OUT" TIG ;
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
top/b200/coregen/chipscope_icon.v
+27
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@@ -0,0 +1,27 @@
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_icon.v
// /___/ /\ Timestamp : Tue Oct 22 17:04:59 PDT 2013
// \ \ / \
// \___\/\___\
//
// Design Name: Verilog Synthesis Wrapper
///////////////////////////////////////////////////////////////////////////////
// This wrapper is used to integrate with Project Navigator and PlanAhead
`timescale 1ns/1ps
module chipscope_icon(
CONTROL0) /* synthesis syn_black_box syn_noprune=1 */;
inout [35 : 0] CONTROL0;
endmodule
top/b200/coregen/chipscope_icon.veo
+28
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@@ -0,0 +1,28 @@
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_icon.veo
// /___/ /\ Timestamp : Tue Oct 22 17:05:00 PDT 2013
// \ \ / \
// \___\/\___\
//
// Design Name: ISE Instantiation template
///////////////////////////////////////////////////////////////////////////////
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
chipscope_icon YourInstanceName (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
top/b200/coregen/chipscope_icon.xco
+56
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@@ -0,0 +1,56 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Oct 23 00:04:31 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx75
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
# END Select
# BEGIN Parameters
CSET component_name=chipscope_icon
CSET constraint_type=external
CSET enable_jtag_bufg=true
CSET example_design=false
CSET number_control_ports=1
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-12-18T02:47:25Z
# END Extra information
GENERATE
# CRC: 5ccf4baf
top/b200/coregen/chipscope_icon.xdc
+7
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@@ -0,0 +1,7 @@
# icon XDC
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
top/b200/coregen/chipscope_icon_flist.txt
+16
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@@ -0,0 +1,16 @@
# Output products list for <chipscope_icon>
_xmsgs/pn_parser.xmsgs
chipscope_icon.asy
chipscope_icon.constraints/chipscope_icon.ucf
chipscope_icon.constraints/chipscope_icon.xdc
chipscope_icon.gise
chipscope_icon.ngc
chipscope_icon.ucf
chipscope_icon.v
chipscope_icon.veo
chipscope_icon.xco
chipscope_icon.xdc
chipscope_icon.xise
chipscope_icon_flist.txt
chipscope_icon_readme.txt
chipscope_icon_xmdf.tcl
top/b200/coregen/chipscope_icon_readme.txt
+46
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@@ -0,0 +1,46 @@
The following files were generated for 'chipscope_icon' in directory
/home/ianb/fpgadev/usrp3/top/b200/coregen/
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* chipscope_icon.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* chipscope_icon.constraints/chipscope_icon.ucf
* chipscope_icon.constraints/chipscope_icon.xdc
* chipscope_icon.ngc
* chipscope_icon.ucf
* chipscope_icon.v
* chipscope_icon.veo
* chipscope_icon.xdc
* chipscope_icon_xmdf.tcl
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* chipscope_icon.asy
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* _xmsgs/pn_parser.xmsgs
* chipscope_icon.gise
* chipscope_icon.xise
Deliver Readme:
Readme file for the IP.
* chipscope_icon_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* chipscope_icon_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

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