Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>


Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f

tools/scripts/viv_generate_bd.tcl

@@ -0,0 +1,78 @@
+#
+# Copyright 2016 Ettus Research
+#
+
+# ---------------------------------------
+# Gather all external parameters
+# ---------------------------------------
+set bd_file         $::env(BD_FILE)               ;# Absolute path to BD/Tcl file from src dir
+set src_ext [file extension $bd_file]             ;# BD or Tcl file?
+set part_name       $::env(PART_NAME)              ;# Full Xilinx part name
+set bd_name [file rootname [file tail $bd_file]]   ;# Extract IP name
+if {[info exists env(BD_IP_REPOS)]} {
+    set ip_repos $::env(BD_IP_REPOS);# Any supporting IP repos
+} else {
+    set ip_repos {}
+}
+if {[info exists env(BD_HDL_SRCS)]} {
+    set hdl_sources $::env(BD_HDL_SRCS);# Any supporting HDL files
+} else {
+    set hdl_sources {}
+}
+
+# Delete any previous output cookie file
+file delete -force "$bd_file.out"
+# ---------------------------------------
+# Vivado Commands
+# ---------------------------------------
+create_project -part $part_name -in_memory
+# In non-project mode, the hierarchy must be updated for the HDL source files to be
+# correctly applied to the BD. See AR:
+# https://www.xilinx.com/support/answers/63488.html
+set_property source_mgmt_mode All [current_project]
+set_property ip_repo_paths "{$ip_repos}" [current_project]
+update_ip_catalog
+# Add supplementary HDL sources, if they exist.
+foreach src_file $hdl_sources {
+    set hdl_ext [file extension $src_file ]
+    if [expr [lsearch {.vhd .vhdl} $hdl_ext] >= 0] {
+        puts "BUILDER: Adding VHDL    : $src_file"
+        read_vhdl -library work $src_file
+    } elseif [expr [lsearch {.v .sv .vh .svh} $hdl_ext] >= 0] {
+        puts "BUILDER: Adding Verilog : $src_file"
+        read_verilog $src_file
+    } else {
+        puts "BUILDER: \[WARNING\] File ignored!!!: $src_file"
+    }
+}
+# Open .tcl or .bd design directly.
+if [expr [lsearch {.tcl} $src_ext] >= 0] {
+    puts "BUILDER: Generating Block Diagram from script: $bd_file"
+    create_bd_design -dir . $bd_name
+    source $bd_file
+    report_ip_status
+    puts "BUILDER: Report_ip_status done"
+    set bd_file $bd_name.bd
+} else {
+    puts "BUILDER: Adding Block Diagram: $bd_file"
+    add_files -norecurse $bd_file
+    puts "BUILDER: Generating BD Target first pass..."
+    generate_target all [get_files $bd_file] -force
+    report_ip_status
+    puts "BUILDER: Report_ip_status done"
+    open_bd_design $bd_file
+}
+# Generate outputs.
+puts "BUILDER: Generating BD Target..."
+generate_target all [get_files $bd_file]
+puts "BUILDER: Generate all done"
+
+if { [get_msg_config -count -severity ERROR] == 0 } {
+    # Write output cookie file
+    set outfile [open "$bd_file.out" w]
+    puts $outfile "This file was auto-generated by viv_generate_bd.tcl and signifies that BD generation is done."
+    close $outfile
+} else {
+    exit 1
+}
+