Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>


Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f

sim/rfnoc/sim_clock_gen.sv

@@ -0,0 +1,127 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: sim_clock_gen
+//
+// Description: This module generates a clock and reset signal for the purposes 
+// of simulation. Both clock and reset are configurable at run time for 
+// software-based simulation control.
+//
+
+
+
+module sim_clock_gen #(
+  parameter realtime PERIOD     = 10.0,  // Period in ns
+  parameter real     DUTY_CYCLE = 0.5,   // Duty cycle, in the range (0.0, 1.0)
+  parameter bit      AUTOSTART  = 1      // Start clock automatically at time 0
+) (
+  output bit clk,
+  output bit rst
+);
+  timeunit      1ns;
+  timeprecision 1ps;
+
+  realtime period       = PERIOD;
+  real     duty         = DUTY_CYCLE;
+  realtime low_time     = PERIOD * (1.0 - DUTY_CYCLE);
+  realtime high_time    = PERIOD * DUTY_CYCLE;
+  bit      toggle       = AUTOSTART;
+  bit      alive        = 1;
+
+
+  //-----------------------
+  // Clock and Reset Tasks
+  //-----------------------
+
+  // Set the period and duty cycle for the clock
+  function void set_clock(real new_period, real new_duty);
+    low_time  = new_period * (1.0 - new_duty);
+    high_time = new_period * new_duty;
+  endfunction
+
+  // Set the period, only, for the clock
+  function void set_period(real new_period);
+    set_clock(new_period, duty);
+  endfunction
+
+  // Set the duty cycle, only, for the clock
+  function void set_duty(real new_duty);
+    set_clock(period, new_duty);
+  endfunction
+
+  // Start toggling the clock
+  function void start();
+    toggle = 1;
+  endfunction
+
+  // Stop toggling the clock
+  function void stop();
+    toggle = 0;
+  endfunction
+
+  // Stop running the clock loop (no new simulation events will be created)
+  function void kill();
+    alive = 0;
+  endfunction
+
+  // Start running the clock loop (new simulation events will be created)
+  function void revive();
+    alive = 1;
+  endfunction
+
+  // Asynchronously assert the reset signal and synchronously deassert it after 
+  // "length" clock cycles.
+  task reset(int length = 8);
+    fork
+      begin
+        rst <= 1;
+        repeat (length) @(posedge clk);
+        rst <= 0;
+      end
+    join_none
+
+    // Make sure rst asserts before we return
+    wait(rst);
+  endtask : reset
+
+  // Assert reset
+  task set_reset();
+    rst <= 1'b1;
+  endtask : set_reset
+
+  // Deassert reset
+  task clr_reset();
+    rst <= 1'b0;
+  endtask : clr_reset
+
+  // Wait for num rising edges of the clock
+  task clk_wait_r(int num = 1);
+    repeat(num) @(posedge clk);
+  endtask
+
+  // Wait for num falling edges of the clock
+  task clkd_wait_f(int num = 1);
+    repeat(num) @(negedge clk);
+  endtask
+
+
+  //--------------------------
+  // Clock Generation Process
+  //--------------------------
+
+  initial begin : clock_block
+    // Toggle the clock in a loop
+    forever begin : clock_loop
+      #(low_time);
+      if (toggle) clk = 0;
+      
+      #(high_time);
+      if (toggle) clk = 1;
+
+      wait (alive);
+    end
+  end
+
+endmodule : sim_clock_gen