Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,37 @@
|
||||
#
|
||||
# Copyright 2016 Ettus Research
|
||||
#
|
||||
|
||||
#-------------------------------------------------
|
||||
# Top-of-Makefile
|
||||
#-------------------------------------------------
|
||||
# Define BASE_DIR to point to the "top" dir
|
||||
BASE_DIR = $(abspath ../../../../top)
|
||||
# Include viv_sim_preamble after defining BASE_DIR
|
||||
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
|
||||
|
||||
#-------------------------------------------------
|
||||
# Testbench Specific
|
||||
#-------------------------------------------------
|
||||
# Define only one toplevel module
|
||||
SIM_TOP = axi_rate_change_tb
|
||||
|
||||
# Add test bench, user design under test, and
|
||||
# additional user created files
|
||||
SIM_SRCS = $(abspath \
|
||||
axi_rate_change_tb.sv \
|
||||
$(LIB_DIR)/control/ram_2port.v \
|
||||
$(LIB_DIR)/fifo/axi_packet_gate.v \
|
||||
$(LIB_DIR)/rfnoc/axi_rate_change.v \
|
||||
$(LIB_DIR)/rfnoc/axi_drop_partial_packet.v \
|
||||
)
|
||||
|
||||
MODELSIM_USER_DO = $(abspath wave.do)
|
||||
|
||||
#-------------------------------------------------
|
||||
# Bottom-of-Makefile
|
||||
#-------------------------------------------------
|
||||
# Include all simulator specific makefiles here
|
||||
# Each should define a unique target to simulate
|
||||
# e.g. xsim, vsim, etc and a common "clean" target
|
||||
include $(BASE_DIR)/../tools/make/viv_simulator.mak
|
||||
@@ -0,0 +1,323 @@
|
||||
`timescale 1ns/1ps
|
||||
`define NS_PER_TICK 1
|
||||
`define NUM_TEST_CASES 4
|
||||
|
||||
`include "sim_exec_report.vh"
|
||||
`include "sim_clks_rsts.vh"
|
||||
`include "sim_cvita_lib.svh"
|
||||
`include "sim_axis_lib.svh"
|
||||
`include "sim_set_rb_lib.svh"
|
||||
|
||||
module axi_rate_change_tb();
|
||||
`TEST_BENCH_INIT("axi_rate_change_tb",`NUM_TEST_CASES,`NS_PER_TICK);
|
||||
localparam CLK_PERIOD = $ceil(1e9/166.67e6);
|
||||
`DEFINE_CLK(clk, CLK_PERIOD, 50);
|
||||
`DEFINE_RESET(reset, 0, 100);
|
||||
|
||||
localparam SR_N_ADDR = 0;
|
||||
localparam SR_M_ADDR = 1;
|
||||
localparam SR_CONFIG_ADDR = 2;
|
||||
localparam MAX_N = 16;
|
||||
localparam MAX_M = 16;
|
||||
|
||||
logic [15:0] src_sid = 16'h0000;
|
||||
logic [15:0] dst_sid = 16'h0010;
|
||||
settings_bus_master sb (.clk(clk));
|
||||
axis_master #(.DWIDTH(32+128)) m_axis (.clk(clk));
|
||||
axis_slave #(.DWIDTH(32+128)) s_axis (.clk(clk));
|
||||
logic clear, clear_user;
|
||||
logic [31:0] m_axis_data_tdata, s_axis_data_tdata;
|
||||
logic m_axis_data_tlast, m_axis_data_tvalid, m_axis_data_tready;
|
||||
logic s_axis_data_tlast, s_axis_data_tvalid, s_axis_data_tready;
|
||||
logic warning_long_throttle, error_extra_outputs, error_drop_pkt_lockup;
|
||||
axi_rate_change #(
|
||||
.WIDTH(32),
|
||||
.MAX_N(MAX_N),
|
||||
.MAX_M(MAX_M),
|
||||
.SR_N_ADDR(SR_N_ADDR),
|
||||
.SR_M_ADDR(SR_M_ADDR),
|
||||
.SR_CONFIG_ADDR(SR_CONFIG_ADDR))
|
||||
axi_rate_change (
|
||||
.clk(clk), .reset(reset), .clear(clear), .clear_user(clear_user),
|
||||
.src_sid(src_sid), .dst_sid(dst_sid),
|
||||
.set_stb(sb.settings_bus.set_stb), .set_addr(sb.settings_bus.set_addr), .set_data(sb.settings_bus.set_data),
|
||||
.i_tdata(m_axis.axis.tdata[31:0]), .i_tlast(m_axis.axis.tlast), .i_tvalid(m_axis.axis.tvalid), .i_tready(m_axis.axis.tready), .i_tuser(m_axis.axis.tdata[159:32]),
|
||||
.o_tdata(s_axis.axis.tdata[31:0]), .o_tlast(s_axis.axis.tlast), .o_tvalid(s_axis.axis.tvalid), .o_tready(s_axis.axis.tready), .o_tuser(s_axis.axis.tdata[159:32]),
|
||||
.m_axis_data_tdata(m_axis_data_tdata), .m_axis_data_tlast(m_axis_data_tlast),
|
||||
.m_axis_data_tvalid(m_axis_data_tvalid), .m_axis_data_tready(m_axis_data_tready),
|
||||
.s_axis_data_tdata(s_axis_data_tdata), .s_axis_data_tlast(s_axis_data_tlast),
|
||||
.s_axis_data_tvalid(s_axis_data_tvalid), .s_axis_data_tready(s_axis_data_tready),
|
||||
.warning_long_throttle(warning_long_throttle),
|
||||
.error_extra_outputs(error_extra_outputs),
|
||||
.error_drop_pkt_lockup(error_drop_pkt_lockup));
|
||||
|
||||
// Simulate user logic that can handle various decimation / interpolation rates
|
||||
// - Generates a word count sequence that is checked in the test_rate() task.
|
||||
// - Introduces a single clock cycle delay which is useful for testing that
|
||||
// the DUT is not reliant on user logic having a large built in delay.
|
||||
integer rate_n, rate_m, count_n, count_m, count_in, count_out;
|
||||
always @(posedge clk) begin
|
||||
if (reset | clear_user | clear) begin
|
||||
s_axis_data_tlast <= 1'b0;
|
||||
count_n <= 1;
|
||||
count_m <= 1;
|
||||
count_in <= 0;
|
||||
count_out <= 0;
|
||||
end else begin
|
||||
// Rate change = N/M
|
||||
if (m_axis_data_tvalid & m_axis_data_tready) begin
|
||||
if (count_n == rate_n) begin
|
||||
count_n <= 1;
|
||||
count_in <= count_in + 1;
|
||||
end else begin
|
||||
count_n <= count_n + 1;
|
||||
end
|
||||
end
|
||||
if (count_in != count_out) begin
|
||||
if (s_axis_data_tvalid & s_axis_data_tready) begin
|
||||
if (count_m == rate_m) begin
|
||||
count_m <= 1;
|
||||
count_out <= count_out + 1;
|
||||
end else begin
|
||||
count_m <= count_m + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign s_axis_data_tdata = {count_out[15:0], count_m[15:0]};
|
||||
assign s_axis_data_tvalid = (count_in != count_out);
|
||||
assign m_axis_data_tready = s_axis_data_tready;
|
||||
|
||||
// Used with test 3 to count output clock cycles
|
||||
int clock_cnt;
|
||||
logic clock_cnt_en = 1'b0;
|
||||
logic clock_cnt_start = 1'b0;
|
||||
always @(posedge clk) begin
|
||||
if (clock_cnt_en == 1'b1) begin
|
||||
// Wait until output data starts
|
||||
if (s_axis.axis.tvalid & ~clock_cnt_start) begin
|
||||
clock_cnt_start <= 1'b1;
|
||||
clock_cnt <= clock_cnt + 1;
|
||||
end else if (clock_cnt_start) begin
|
||||
clock_cnt <= clock_cnt + 1;
|
||||
end
|
||||
end else begin
|
||||
clock_cnt_start <= 1'b0;
|
||||
clock_cnt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
/********************************************************
|
||||
** Verification
|
||||
********************************************************/
|
||||
task random_wait(int unsigned min_cycles, int unsigned max_cycles);
|
||||
begin
|
||||
int unsigned num_cycles;
|
||||
do begin
|
||||
num_cycles = $random() & (2**($clog2(max_cycles))-1);
|
||||
end while ((num_cycles < min_cycles) || (num_cycles > max_cycles));
|
||||
|
||||
if (num_cycles != 0) begin
|
||||
for (int unsigned i = 0; i < num_cycles; i++) begin
|
||||
@(posedge clk);
|
||||
end
|
||||
@(negedge clk); // Realign with negedge
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
task test_rate(int n, int m, int num_words, int spp = 16, bit rand_delay_in = 0, bit rand_delay_out = 0);
|
||||
begin
|
||||
clear = 1'b1;
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
clear = 1'b0;
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
rate_n = n;
|
||||
rate_m = m;
|
||||
sb.write(SR_N_ADDR, n);
|
||||
sb.write(SR_M_ADDR, m);
|
||||
@(posedge clk);
|
||||
fork
|
||||
begin
|
||||
cvita_hdr_t send_header;
|
||||
int words_left_to_send, words_to_send;
|
||||
logic [31:0] words_sent;
|
||||
real timestamp;
|
||||
timestamp = 0.0;
|
||||
words_sent = 0;
|
||||
words_left_to_send = num_words;
|
||||
|
||||
while (words_left_to_send > 0) begin
|
||||
// Setup header
|
||||
send_header = '{default:0};
|
||||
send_header.has_time = 1;
|
||||
send_header.timestamp = longint'(timestamp);
|
||||
send_header.eob = (words_left_to_send <= spp);
|
||||
if (words_left_to_send >= spp) begin
|
||||
send_header.length = 16+4*spp;
|
||||
words_to_send = spp;
|
||||
words_left_to_send -= spp;
|
||||
end else begin
|
||||
send_header.length = 16+4*words_left_to_send;
|
||||
words_to_send = words_left_to_send;
|
||||
words_left_to_send = 0;
|
||||
end
|
||||
// Send packet
|
||||
for (int i = 0; i < words_to_send; i++) begin
|
||||
if (rand_delay_in) random_wait(0,2*spp);
|
||||
m_axis.push_word({send_header,words_sent + i},i == words_to_send-1);
|
||||
end
|
||||
words_sent += words_to_send;
|
||||
// Update seq num, timestamp
|
||||
send_header.seqnum++;
|
||||
timestamp += (1.0*m/n)*words_to_send;
|
||||
end
|
||||
end
|
||||
begin
|
||||
string s;
|
||||
cvita_hdr_t recv_header;
|
||||
logic last, expected_eob;
|
||||
real timestamp;
|
||||
logic [63:0] expected_timestamp;
|
||||
logic [31:0] word;
|
||||
logic [15:0] word_cnt_div_m, word_cnt_div_m_frac;
|
||||
logic [15:0] word_cnt_div_spp_frac;
|
||||
int words_left_to_recv, words_recvd;
|
||||
timestamp = 0.0;
|
||||
expected_timestamp = 0; // Timestamp starts at 0
|
||||
word_cnt_div_spp_frac = 0;
|
||||
word_cnt_div_m = 0;
|
||||
word_cnt_div_m_frac = 0;
|
||||
words_recvd = 0;
|
||||
words_left_to_recv = $floor(num_words/n)*m; // Order matters!
|
||||
|
||||
while (words_left_to_recv > 0) begin
|
||||
s_axis.pull_word({recv_header,word},last);
|
||||
word_cnt_div_spp_frac++;
|
||||
word_cnt_div_m_frac++;
|
||||
words_recvd++;
|
||||
words_left_to_recv--;
|
||||
timestamp += 1.0*n;
|
||||
// Check packet length
|
||||
if ((word_cnt_div_spp_frac == spp) || (words_left_to_recv == 0)) begin
|
||||
`ASSERT_FATAL(last == 1, "Incorrect packet length! Last not asserted!");
|
||||
word_cnt_div_spp_frac = 0;
|
||||
end else begin
|
||||
$sformat(s, "Incorrect packet length! Expected: %0d, Actual %0d", spp, words_recvd);
|
||||
`ASSERT_FATAL(last == 0, s);
|
||||
end
|
||||
// Check for EOB
|
||||
if (last) begin
|
||||
words_recvd = 0;
|
||||
expected_eob = (words_left_to_recv == 0);
|
||||
$sformat(s, "Incorrect EOB state! Expected: %0d, Actual %0d", expected_eob, recv_header.eob);
|
||||
`ASSERT_FATAL(recv_header.eob == expected_eob, s);
|
||||
end
|
||||
// Check timestamp
|
||||
if (last) begin
|
||||
$sformat(s, "Incorrect timestamp! Expected: %0d, Actual %0d", expected_timestamp, recv_header.timestamp);
|
||||
`ASSERT_FATAL(recv_header.timestamp == expected_timestamp, s);
|
||||
expected_timestamp = longint'(timestamp);
|
||||
end
|
||||
// Check word
|
||||
$sformat(s, "Incorrect packet data! Expected: 0x%08h, Actual: 0x%08h", {word_cnt_div_m, word_cnt_div_m_frac}, word);
|
||||
`ASSERT_FATAL(((word[31:16] == word_cnt_div_m) && (word[15:0] == word_cnt_div_m_frac)), s);
|
||||
// Track number of received words, do at end of loop
|
||||
if (word_cnt_div_m_frac == m) begin
|
||||
word_cnt_div_m_frac = 0;
|
||||
word_cnt_div_m++;
|
||||
end
|
||||
end
|
||||
end
|
||||
join
|
||||
end
|
||||
endtask
|
||||
|
||||
initial begin : tb_main
|
||||
string s;
|
||||
cvita_hdr_t tmp_header;
|
||||
logic [63:0] word;
|
||||
logic last;
|
||||
integer spp, number_words;
|
||||
spp = 16;
|
||||
|
||||
/********************************************************
|
||||
** Test 1 -- Reset
|
||||
********************************************************/
|
||||
`TEST_CASE_START("Wait for Reset");
|
||||
sb.reset();
|
||||
m_axis.reset();
|
||||
s_axis.reset();
|
||||
while (reset) @(posedge clk);
|
||||
`TEST_CASE_DONE(~reset);
|
||||
|
||||
/********************************************************
|
||||
** Test 2 -- Test various rates
|
||||
** - Try many decimation / interpolation rates (including
|
||||
** fractional rates) and use randomized delays.
|
||||
********************************************************/
|
||||
`TEST_CASE_START("Check various rates");
|
||||
for (int _n = 1; _n <= MAX_N; _n++) begin
|
||||
for (int _m = 1; _m <= MAX_M; _m++) begin
|
||||
$display("Testing rate %0d:%0d", _n, _m);
|
||||
test_rate(_n, _m, _n*spp*3, spp, 1, 1);
|
||||
end
|
||||
end
|
||||
`TEST_CASE_DONE(1);
|
||||
|
||||
#2000; // Delay to make the tests visually distinct in waveform viewer
|
||||
|
||||
/********************************************************
|
||||
** Test 3 -- Test partial packets
|
||||
** - Send packets with extra data that is less than SPP.
|
||||
** Module should output the maximum number of samples
|
||||
** possible while dropping the "partial" sample.
|
||||
********************************************************/
|
||||
`TEST_CASE_START("Test partial packets");
|
||||
for (int _n = 1; _n <= MAX_N; _n++) begin
|
||||
for (int _m = 1; _m <= MAX_M; _m++) begin
|
||||
$display("Testing rate %0d:%0d", _n, _m);
|
||||
test_rate(_n, _m, _n*spp + spp-1, spp, 1, 1);
|
||||
end
|
||||
end
|
||||
`TEST_CASE_DONE(1);
|
||||
|
||||
#2000;
|
||||
|
||||
/********************************************************
|
||||
** Test 3 -- Test for bubble states
|
||||
** - Send many packets at full rate and make sure number
|
||||
** of input clock cycles == output clock cycles. If
|
||||
** they do not match, then the module likely has
|
||||
** bubble states that would prevent it from running
|
||||
** continuously at full rate.
|
||||
********************************************************/
|
||||
`TEST_CASE_START("Test for bubble states");
|
||||
clock_cnt_en = 1'b1;
|
||||
number_words = 100000;
|
||||
test_rate(1, 1, number_words, spp, 0, 0);
|
||||
$sformat(s, "Incorrect number of clock cycles -- Possible bubble states detected! Expected: %0d, Actual: %0d", number_words, clock_cnt);
|
||||
`ASSERT_FATAL(clock_cnt == number_words, s);
|
||||
clock_cnt_en = 1'b0;
|
||||
`TEST_CASE_DONE(1);
|
||||
|
||||
`TEST_BENCH_DONE;
|
||||
|
||||
end
|
||||
|
||||
// The warning, error signals should never assert.
|
||||
initial begin
|
||||
while (reset) @(posedge clk);
|
||||
forever begin
|
||||
@(posedge clk);
|
||||
`ASSERT_FATAL(~warning_long_throttle, "Throttle state deadlock!");
|
||||
`ASSERT_FATAL(~error_extra_outputs, "Extra outputs detected!");
|
||||
`ASSERT_FATAL(~error_drop_pkt_lockup, "Drop packet deadlock!");
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,115 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/clk
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/reset
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/clear
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/clear_user
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/active
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_tdata
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_tlast
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_tvalid
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_tready
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_tuser
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_frac
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_tdata
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_tready
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_tvalid
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/in_pkt_cnt
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_reg_tdata
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_reg_tlast
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_reg_tvalid
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_reg_tready
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/i_reg_tuser
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/m_axis_data_tdata
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/m_axis_data_tlast
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/m_axis_data_tvalid
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/m_axis_data_tready
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/s_axis_data_tdata
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/s_axis_data_tlast
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/s_axis_data_tvalid
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/s_axis_data_tready
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/out_payload_cnt
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/payload_length_out
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_m
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_fifo_tdata
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_fifo_tready
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/word_cnt_div_n_fifo_tvalid
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/first_pkt_out
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/vita_time_out
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/vita_time_accum
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/vita_time_reg
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/header_fifo_out_tready
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/header_fifo_out_tvalid
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_reg_tdata
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_reg_tlast
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_reg_tvalid
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_reg_tready
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_reg_tuser
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_tdata
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_tlast
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_tvalid
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_tready
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/o_tuser
|
||||
add wave -noupdate -divider {AXI Drop Partial Packet}
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_tdata
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_terror
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_tlast
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_tlast_int
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_tready
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/i_tvalid
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/in_cnt
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/large_pkt
|
||||
add wave -noupdate {/axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/o_tdata[32]}
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/o_tdata
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/o_tlast
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/o_tready
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/o_tvalid
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/small_pkt
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/flush
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/hold_last_sample
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/in_pkt_cnt
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/out_pkt_cnt
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/release_due_to_error
|
||||
add wave -noupdate -divider {AXI Drop Packet}
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/hold
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/i_tdata
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/i_tvalid
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/i_terror
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/i_tlast
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/i_tready
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/empty
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/full
|
||||
add wave -noupdate -radix unsigned /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/rd_addr
|
||||
add wave -noupdate -radix unsigned /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/wr_addr
|
||||
add wave -noupdate -radix unsigned /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/in_pkt_cnt
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/int_tdata
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/int_tvalid
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/int_tlast
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/int_tready
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/mem
|
||||
add wave -noupdate -radix hexadecimal /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/o_tdata
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/o_tvalid
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/o_tready
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/o_tlast
|
||||
add wave -noupdate -radix unsigned /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/out_pkt_cnt
|
||||
add wave -noupdate -radix unsigned /axi_rate_change_tb/axi_rate_change/axi_drop_partial_packet/axi_drop_packet/prev_wr_addr
|
||||
add wave -noupdate /axi_rate_change_tb/axi_rate_change/n
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {1112517 ps} 0} {{Cursor 2} {1974349848 ps} 0}
|
||||
quietly wave cursor active 2
|
||||
configure wave -namecolwidth 633
|
||||
configure wave -valuecolwidth 184
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {1974303474 ps} {1974374671 ps}
|
||||
Reference in New Issue
Block a user