Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,49 @@
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#
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# Copyright 2018 Ettus Research, A National Instruments Company
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/axi/Makefile.srcs
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include $(BASE_DIR)/../lib/fifo/Makefile.srcs
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include $(BASE_DIR)/../lib/control/Makefile.srcs
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DESIGN_SRCS = $(abspath \
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$(AXI_SRCS) \
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$(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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SIM_TOP = axis_shift_register_tb
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# Add test bench, user design under test, and
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# additional user created files
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SIM_SRCS = $(abspath \
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axis_shift_register_tb.sv \
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)
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# MODELSIM_USER_DO = $(abspath wave.do)
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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@@ -0,0 +1,325 @@
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//
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// Copyright 2018 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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`timescale 1ns/1ps
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`define NS_PER_TICK 1
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`define NUM_TEST_CASES 8
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`include "sim_exec_report.vh"
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`include "sim_clks_rsts.vh"
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`include "sim_axis_lib.svh"
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module axis_shift_register_tb();
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`TEST_BENCH_INIT("axis_shift_register_tb", `NUM_TEST_CASES, `NS_PER_TICK);
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localparam CLK_PERIOD = $ceil(1e9/100.0e6);
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`DEFINE_CLK(clk, CLK_PERIOD, 50);
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`DEFINE_RESET(reset, 0, 100);
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localparam WIDTH = 32;
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localparam integer NUM_INST = 4;
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logic [WIDTH:0] i_tdata[0:NUM_INST-1];
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logic i_tlast[0:NUM_INST-1], i_tvalid[0:NUM_INST-1];
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wire i_tready[0:NUM_INST-1];
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wire [WIDTH:0] o_tdata[0:NUM_INST-1];
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wire o_tlast[0:NUM_INST-1], o_tvalid[0:NUM_INST-1];
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logic o_tready[0:NUM_INST-1];
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wire [15:0] stage_stb[0:NUM_INST-1], stage_eop[0:NUM_INST-1];
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wire [WIDTH-1:0] sb_dout, sb_din;
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wire sb_keep;
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reg [WIDTH-1:0] sb_shreg[0:2];
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always @(posedge clk) begin
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if (stage_stb[2][0])
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sb_shreg[0] <= sb_dout;
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if (stage_stb[2][1])
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sb_shreg[1] <= sb_shreg[0];
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if (stage_stb[2][2])
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sb_shreg[2] <= sb_shreg[1];
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end
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assign sb_din = sb_shreg[2];
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axis_shift_register #(
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.WIDTH(WIDTH), .NSPC(1), .LATENCY(2),
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.SIDEBAND_DATAPATH(0), .GAPLESS(0),
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.PIPELINE("NONE")
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) inst_0 (
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.clk(clk), .reset(reset),
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.s_axis_tdata(i_tdata[0]), .s_axis_tkeep(i_tdata[0][WIDTH]), .s_axis_tlast(i_tlast[0]),
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.s_axis_tvalid(i_tvalid[0]), .s_axis_tready(i_tready[0]),
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.m_axis_tdata(o_tdata[0]), .m_axis_tkeep(o_tdata[0][WIDTH]), .m_axis_tlast(o_tlast[0]),
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.m_axis_tvalid(o_tvalid[0]), .m_axis_tready(o_tready[0]),
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.stage_stb(stage_stb[0]), .stage_eop(stage_eop[0]),
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.m_sideband_data(), .m_sideband_keep(), .s_sideband_data()
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);
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axis_shift_register #(
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.WIDTH(WIDTH), .NSPC(1), .LATENCY(9),
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.SIDEBAND_DATAPATH(0), .GAPLESS(0),
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.PIPELINE("BOTH")
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) inst_1 (
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.clk(clk), .reset(reset),
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.s_axis_tdata(i_tdata[1]), .s_axis_tkeep(i_tdata[1][WIDTH]), .s_axis_tlast(i_tlast[1]),
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.s_axis_tvalid(i_tvalid[1]), .s_axis_tready(i_tready[1]),
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.m_axis_tdata(o_tdata[1]), .m_axis_tkeep(o_tdata[1][WIDTH]), .m_axis_tlast(o_tlast[1]),
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.m_axis_tvalid(o_tvalid[1]), .m_axis_tready(o_tready[1]),
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.stage_stb(stage_stb[1]), .stage_eop(stage_eop[1]),
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.m_sideband_data(), .m_sideband_keep(), .s_sideband_data()
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);
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axis_shift_register #(
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.WIDTH(WIDTH/2), .NSPC(2), .LATENCY(3),
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.SIDEBAND_DATAPATH(1), .GAPLESS(0),
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.PIPELINE("NONE")
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) inst_2 (
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.clk(clk), .reset(reset),
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.s_axis_tdata(i_tdata[2]), .s_axis_tkeep(i_tdata[2][WIDTH]), .s_axis_tlast(i_tlast[2]),
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.s_axis_tvalid(i_tvalid[2]), .s_axis_tready(i_tready[2]),
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.m_axis_tdata(o_tdata[2]), .m_axis_tkeep(o_tdata[2][WIDTH]), .m_axis_tlast(o_tlast[2]),
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.m_axis_tvalid(o_tvalid[2]), .m_axis_tready(o_tready[2]),
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.stage_stb(stage_stb[2]), .stage_eop(stage_eop[2]),
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.m_sideband_data(sb_dout), .m_sideband_keep(sb_keep), .s_sideband_data(sb_din)
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);
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axis_shift_register #(
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.WIDTH(WIDTH/8), .NSPC(8), .LATENCY(14),
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.SIDEBAND_DATAPATH(0), .GAPLESS(1),
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.PIPELINE("NONE")
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) inst_3 (
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.clk(clk), .reset(reset),
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.s_axis_tdata(i_tdata[3]), .s_axis_tkeep(i_tdata[3][WIDTH]), .s_axis_tlast(i_tlast[3]),
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.s_axis_tvalid(i_tvalid[3]), .s_axis_tready(i_tready[3]),
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.m_axis_tdata(o_tdata[3]), .m_axis_tkeep(o_tdata[3][WIDTH]), .m_axis_tlast(o_tlast[3]),
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.m_axis_tvalid(o_tvalid[3]), .m_axis_tready(o_tready[3]),
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.stage_stb(stage_stb[3]), .stage_eop(stage_eop[3]),
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.m_sideband_data(), .m_sideband_keep(), .s_sideband_data()
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);
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logic [15:0] prev_stage_stb[0:NUM_INST-1];
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initial begin : tb_main
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string s;
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`TEST_CASE_START("Wait for Reset");
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for (int k = 0; k < NUM_INST; k=k+1) begin
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o_tready[k] = 1'b1;
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i_tvalid[k] = 1'b0;
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prev_stage_stb[k] = 0;
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end
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while (reset) @(posedge clk);
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`TEST_CASE_DONE(~reset);
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`TEST_CASE_START("Check module with LATENCY=2, PIPELINE=NONE");
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`ASSERT_ERROR(o_tvalid[0] == 1'b0, "Output incorrectly active when idle");
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`ASSERT_ERROR(i_tready[0] == 1'b1, "Input was not ready when idle");
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`ASSERT_ERROR(stage_stb[0][1:0] === 0, "Incorrect stage_stb when idle");
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for (int j = 0; j < 2; j=j+1) begin
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i_tdata[0] = j;
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i_tlast[0] = j % 2;
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i_tvalid[0] = 1'b1;
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@(posedge clk);
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i_tvalid[0] = 1'b0;
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prev_stage_stb[0][1:0] = {prev_stage_stb[0][0], 1'b1};
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`ASSERT_ERROR(stage_stb[0][1:0] == prev_stage_stb[0][1:0], "Incorrect stage_stb");
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`ASSERT_ERROR(i_tready[0] == 1'b1, "Input was not ready during fill-up");
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`ASSERT_ERROR(o_tvalid[0] == 1'b0, "Output incorrectly active during fill-up");
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end
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for (int j = 0; j < 2; j=j+1) begin
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@(posedge clk);
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`ASSERT_ERROR(o_tvalid[0] == 1'b1, "Output was not active");
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`ASSERT_ERROR(o_tlast[0] == j % 2, "Incorrect tlast");
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`ASSERT_ERROR(o_tdata[0] == j, "Incorrect tdata");
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end
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`TEST_CASE_DONE(1);
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`TEST_CASE_START("Check module with LATENCY=9, PIPELINE=BOTH");
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prev_stage_stb[1] = 0;
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`ASSERT_ERROR(o_tvalid[1] == 1'b0, "Output incorrectly active when idle");
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`ASSERT_ERROR(i_tready[1] == 1'b1, "Input was not ready when idle");
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`ASSERT_ERROR(stage_stb[1][1:0] === 0, "Incorrect stage_stb when idle");
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for (int j = 0; j < 9; j=j+1) begin
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i_tdata[1] = -j;
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i_tlast[1] = 1'b1;
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i_tvalid[1] = 1'b1;
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@(posedge clk);
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i_tvalid[1] = 1'b0;
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prev_stage_stb[1][8:0] = {prev_stage_stb[1][7:0], 1'b1};
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`ASSERT_ERROR(stage_eop[1][8:0] == prev_stage_stb[1][8:0], "Incorrect stage_eop");
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`ASSERT_ERROR(stage_stb[1][8:0] == prev_stage_stb[1][8:0], "Incorrect stage_stb");
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`ASSERT_ERROR(i_tready[1] == 1'b1, "Input was not ready during fill-up");
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`ASSERT_ERROR(o_tvalid[1] == 1'b0, "Output incorrectly active during fill-up");
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end
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for (int j = 0; j < 9; j=j+1) begin
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@(posedge clk);
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`ASSERT_ERROR(o_tvalid[1] == 1'b1, "Output was not active");
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`ASSERT_ERROR(o_tlast[1] == 1'b1, "Incorrect tlast");
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`ASSERT_ERROR(o_tdata[1] == -j, "Incorrect tdata");
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end
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@(posedge clk);
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`TEST_CASE_DONE(1);
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`TEST_CASE_START("Check module with LATENCY=9, PIPELINE=BOTH (backpressure)");
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prev_stage_stb[1] = 0;
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o_tready[1] = 1'b0;
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`ASSERT_ERROR(o_tvalid[1] == 1'b0, "Output incorrectly active when idle");
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`ASSERT_ERROR(i_tready[1] == 1'b1, "Input was not ready when idle");
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`ASSERT_ERROR(stage_stb[1][1:0] === 0, "Incorrect stage_stb when idle");
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for (int j = 0; j < 9; j=j+1) begin
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i_tdata[1] = -j;
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i_tlast[1] = 1'b1;
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i_tvalid[1] = 1'b1;
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@(posedge clk);
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i_tvalid[1] = 1'b0;
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prev_stage_stb[1][8:0] = {prev_stage_stb[1][7:0], 1'b1};
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`ASSERT_ERROR(stage_stb[1][8:0] == prev_stage_stb[1][8:0], "Incorrect stage_stb");
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`ASSERT_ERROR(stage_eop[1][8:0] == prev_stage_stb[1][8:0], "Incorrect stage_eop");
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`ASSERT_ERROR(i_tready[1] == 1'b1, "Input was not ready during fill-up");
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`ASSERT_ERROR(o_tvalid[1] == 1'b0, "Output incorrectly active during fill-up");
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end
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o_tready[1] = 1'b1;
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for (int j = 0; j < 9; j=j+1) begin
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@(posedge clk);
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`ASSERT_ERROR(o_tvalid[1] == 1'b1, "Output was not active");
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`ASSERT_ERROR(o_tlast[1] == 1'b1, "Incorrect tlast");
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`ASSERT_ERROR(o_tdata[1] == -j, "Incorrect tdata");
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end
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@(posedge clk);
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`TEST_CASE_DONE(1);
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`TEST_CASE_START("Check module with LATENCY=9, PIPELINE=BOTH (steady-state)");
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prev_stage_stb[1] = 0;
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fork
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begin
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for (int j = 0; j < 50; j=j+1) begin
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i_tdata[1] = j;
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i_tlast[1] = j % 2;
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i_tvalid[1] = 1'b1;
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@(posedge clk);
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i_tvalid[1] = 1'b0;
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prev_stage_stb[1][8:0] = {prev_stage_stb[1][7:0], 1'b1};
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`ASSERT_ERROR(stage_stb[1][8:0] == prev_stage_stb[1][8:0], "Incorrect stage_stb");
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end
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end
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begin
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o_tready[1] = 1'b1;
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repeat(9) @(posedge clk);
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for (int j = 0; j < 50; j=j+1) begin
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@(posedge clk);
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`ASSERT_ERROR(o_tvalid[1] == 1'b1, "Output was not active");
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`ASSERT_ERROR(o_tlast[1] == j % 2, "Incorrect tlast");
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`ASSERT_ERROR(o_tdata[1] == j, "Incorrect tdata");
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end
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@(posedge clk);
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end
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join
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`TEST_CASE_DONE(1);
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`TEST_CASE_START("Check module with LATENCY=9, PIPELINE=BOTH (gaps)");
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prev_stage_stb[1] = 0;
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fork
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begin
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for (int j = 0; j < 50; j=j+1) begin
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i_tdata[1] = j;
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i_tlast[1] = j % 2;
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i_tvalid[1] = 1'b1;
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@(posedge clk);
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while (~i_tready[1]) @(posedge clk);
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i_tvalid[1] = 1'b0;
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end
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end
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begin
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o_tready[1] = 1'b1;
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repeat(9) @(posedge clk);
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for (int j = 0; j < 20; j=j+1) begin
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@(posedge clk);
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`ASSERT_ERROR(o_tvalid[1] == 1'b1, "Output was not active");
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`ASSERT_ERROR(o_tlast[1] == j % 2, "Incorrect tlast");
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`ASSERT_ERROR(o_tdata[1] == j, "Incorrect tdata");
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||||
end
|
||||
o_tready[1] = 1'b0;
|
||||
repeat(4) @(posedge clk);
|
||||
o_tready[1] = 1'b1;
|
||||
for (int j = 20; j < 50; j=j+1) begin
|
||||
@(posedge clk);
|
||||
`ASSERT_ERROR(o_tvalid[1] == 1'b1, "Output was not active");
|
||||
`ASSERT_ERROR(o_tlast[1] == j % 2, "Incorrect tlast");
|
||||
`ASSERT_ERROR(o_tdata[1] == j, "Incorrect tdata");
|
||||
end
|
||||
@(posedge clk);
|
||||
end
|
||||
join
|
||||
`TEST_CASE_DONE(1);
|
||||
|
||||
`TEST_CASE_START("Check module with LATENCY=3, SIDEBAND=1 (gaps)");
|
||||
prev_stage_stb[2] = 0;
|
||||
fork
|
||||
begin
|
||||
for (int j = 0; j < 50; j=j+1) begin
|
||||
i_tdata[2] = j;
|
||||
i_tlast[2] = j % 4 == 0;
|
||||
i_tvalid[2] = 1'b1;
|
||||
@(posedge clk);
|
||||
while (~i_tready[2]) @(posedge clk);
|
||||
i_tvalid[2] = 1'b0;
|
||||
end
|
||||
end
|
||||
begin
|
||||
o_tready[2] = 1'b1;
|
||||
repeat(3) @(posedge clk);
|
||||
for (int j = 0; j < 20; j=j+1) begin
|
||||
@(posedge clk);
|
||||
`ASSERT_ERROR(o_tvalid[2] == 1'b1, "Output was not active");
|
||||
`ASSERT_ERROR(o_tlast[2] == j % 4 == 0, "Incorrect tlast");
|
||||
`ASSERT_ERROR(o_tdata[2] == j, "Incorrect tdata");
|
||||
end
|
||||
o_tready[2] = 1'b0;
|
||||
repeat(4) @(posedge clk);
|
||||
o_tready[2] = 1'b1;
|
||||
for (int j = 20; j < 50; j=j+1) begin
|
||||
@(posedge clk);
|
||||
`ASSERT_ERROR(o_tvalid[2] == 1'b1, "Output was not active");
|
||||
`ASSERT_ERROR(o_tlast[2] == j % 4 == 0, "Incorrect tlast");
|
||||
`ASSERT_ERROR(o_tdata[2] == j, "Incorrect tdata");
|
||||
end
|
||||
@(posedge clk);
|
||||
end
|
||||
join
|
||||
`TEST_CASE_DONE(1);
|
||||
|
||||
`TEST_CASE_START("Check module with LATENCY=14, GAPLESS=1");
|
||||
prev_stage_stb[3] = 0;
|
||||
o_tready[3] = 1'b0;
|
||||
fork
|
||||
begin
|
||||
for (int j = 0; j < 50; j=j+1) begin
|
||||
i_tdata[3] = j;
|
||||
i_tlast[3] = j % 4 == 0;
|
||||
i_tvalid[3] = 1'b1;
|
||||
@(posedge clk);
|
||||
prev_stage_stb[3][13:0] = {prev_stage_stb[3][12:0], 1'b1};
|
||||
`ASSERT_ERROR(stage_stb[3][13:0] == prev_stage_stb[3][13:0], "Incorrect stage_stb");
|
||||
while (~i_tready[3]) @(posedge clk);
|
||||
i_tvalid[3] = 1'b0;
|
||||
if (j > 16) repeat($urandom_range(0, 15)) @(posedge clk);
|
||||
`ASSERT_ERROR(stage_stb[3][13:0] == prev_stage_stb[3][13:0] || stage_stb[3][13:0] == 14'd0, "Incorrect stage_stb");
|
||||
end
|
||||
end
|
||||
begin
|
||||
for (int j = 0; j < 50 - 14; j=j+1) begin
|
||||
while (~o_tvalid[3]) @(posedge clk);
|
||||
@(negedge clk);
|
||||
`ASSERT_ERROR(o_tvalid[3] == 1'b1, "Output was not active");
|
||||
`ASSERT_ERROR(o_tlast[3] == j % 4 == 0, "Incorrect tlast");
|
||||
`ASSERT_ERROR(o_tdata[3] == j, "Incorrect tdata");
|
||||
o_tready[3] = 1'b1;
|
||||
@(negedge clk);
|
||||
o_tready[3] = 1'b0;
|
||||
@(posedge clk);
|
||||
end
|
||||
end
|
||||
join
|
||||
`TEST_CASE_DONE(1);
|
||||
`TEST_BENCH_DONE;
|
||||
end
|
||||
endmodule
|
||||
@@ -0,0 +1,35 @@
|
||||
#
|
||||
# Copyright 2018 Ettus Research, A National Instruments Company
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
#-------------------------------------------------
|
||||
# Top-of-Makefile
|
||||
#-------------------------------------------------
|
||||
# Define BASE_DIR to point to the "top" dir
|
||||
BASE_DIR = $(abspath ../../../../top)
|
||||
# Include viv_sim_preamble after defining BASE_DIR
|
||||
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
|
||||
|
||||
#-------------------------------------------------
|
||||
# Testbench Specific
|
||||
#-------------------------------------------------
|
||||
# Define only one toplevel module
|
||||
SIM_TOP = axis_width_conv_tb
|
||||
|
||||
# Add test bench, user design under test, and
|
||||
# additional user created files
|
||||
SIM_SRCS = $(abspath \
|
||||
axis_width_conv_tb.sv \
|
||||
)
|
||||
|
||||
# MODELSIM_USER_DO = $(abspath wave.do)
|
||||
|
||||
#-------------------------------------------------
|
||||
# Bottom-of-Makefile
|
||||
#-------------------------------------------------
|
||||
# Include all simulator specific makefiles here
|
||||
# Each should define a unique target to simulate
|
||||
# e.g. xsim, vsim, etc and a common "clean" target
|
||||
include $(BASE_DIR)/../tools/make/viv_simulator.mak
|
||||
@@ -0,0 +1,322 @@
|
||||
//
|
||||
// Copyright 2018 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
|
||||
`timescale 1ns/1ps
|
||||
`define NS_PER_TICK 1
|
||||
`define NUM_TEST_CASES 13
|
||||
|
||||
`include "sim_exec_report.vh"
|
||||
`include "sim_clks_rsts.vh"
|
||||
`include "sim_axis_lib.svh"
|
||||
|
||||
module axis_width_conv_tb();
|
||||
`TEST_BENCH_INIT("axis_width_conv_tb", `NUM_TEST_CASES, `NS_PER_TICK);
|
||||
|
||||
`DEFINE_CLK(clk50, 20.000, 50);
|
||||
`DEFINE_CLK(clk200, 5.000, 50);
|
||||
`DEFINE_LATE_START_CLK(clk166, 6.000, 50, 0.37, 0.01)
|
||||
`DEFINE_RESET(areset, 0, 100);
|
||||
|
||||
localparam WORD_W = 8;
|
||||
localparam integer NINST = 6;
|
||||
localparam integer IN_WORDS[0:NINST-1] = {1, 4, 4, 8, 8, 17};
|
||||
localparam integer OUT_WORDS[0:NINST-1] = {4, 1, 3, 2, 8, 19};
|
||||
localparam integer MAX_IN_WORDS = 20;
|
||||
localparam integer MAX_OUT_WORDS = 20;
|
||||
localparam integer MAX_SPP = 100;
|
||||
|
||||
axis_master #(.DWIDTH((WORD_W+1)*IN_WORDS[0])) m0 (.clk(clk50));
|
||||
axis_master #(.DWIDTH((WORD_W+1)*IN_WORDS[1])) m1 (.clk(clk50));
|
||||
axis_master #(.DWIDTH((WORD_W+1)*IN_WORDS[2])) m2 (.clk(clk50));
|
||||
axis_master #(.DWIDTH((WORD_W+1)*IN_WORDS[3])) m3 (.clk(clk50));
|
||||
axis_master #(.DWIDTH((WORD_W+1)*IN_WORDS[4])) m4 (.clk(clk50));
|
||||
axis_master #(.DWIDTH((WORD_W+1)*IN_WORDS[5])) m5 (.clk(clk50));
|
||||
|
||||
axis_slave #(.DWIDTH((WORD_W+1)*OUT_WORDS[0])) s0 (.clk(clk50));
|
||||
axis_slave #(.DWIDTH((WORD_W+1)*OUT_WORDS[1])) s1 (.clk(clk50));
|
||||
axis_slave #(.DWIDTH((WORD_W+1)*OUT_WORDS[2])) s2 (.clk(clk200));
|
||||
axis_slave #(.DWIDTH((WORD_W+1)*OUT_WORDS[3])) s3 (.clk(clk166));
|
||||
axis_slave #(.DWIDTH((WORD_W+1)*OUT_WORDS[4])) s4 (.clk(clk166));
|
||||
axis_slave #(.DWIDTH((WORD_W+1)*OUT_WORDS[5])) s5 (.clk(clk50));
|
||||
|
||||
// An integer 1-to-4 upsizer
|
||||
axis_width_conv #(
|
||||
.WORD_W(WORD_W), .IN_WORDS(IN_WORDS[0]), .OUT_WORDS(OUT_WORDS[0]),
|
||||
.SYNC_CLKS(1), .PIPELINE("INOUT")
|
||||
) dut0 (
|
||||
.s_axis_aclk (clk50),
|
||||
.s_axis_rst (areset),
|
||||
.s_axis_tdata (m0.axis.tdata[(IN_WORDS[0]*WORD_W)-1:0]),
|
||||
.s_axis_tkeep (m0.axis.tdata[IN_WORDS[0]*WORD_W+:IN_WORDS[0]]),
|
||||
.s_axis_tlast (m0.axis.tlast),
|
||||
.s_axis_tvalid(m0.axis.tvalid),
|
||||
.s_axis_tready(m0.axis.tready),
|
||||
.m_axis_aclk (clk50),
|
||||
.m_axis_rst (areset),
|
||||
.m_axis_tdata (s0.axis.tdata[(OUT_WORDS[0]*WORD_W)-1:0]),
|
||||
.m_axis_tkeep (s0.axis.tdata[OUT_WORDS[0]*WORD_W+:OUT_WORDS[0]]),
|
||||
.m_axis_tlast (s0.axis.tlast),
|
||||
.m_axis_tvalid(s0.axis.tvalid),
|
||||
.m_axis_tready(s0.axis.tready)
|
||||
);
|
||||
|
||||
// An integer 4-to-1 downsizer
|
||||
axis_width_conv #(
|
||||
.WORD_W(WORD_W), .IN_WORDS(IN_WORDS[1]), .OUT_WORDS(OUT_WORDS[1]),
|
||||
.SYNC_CLKS(1), .PIPELINE("IN")
|
||||
) dut1 (
|
||||
.s_axis_aclk (clk50),
|
||||
.s_axis_rst (areset),
|
||||
.s_axis_tdata (m1.axis.tdata[(IN_WORDS[1]*WORD_W)-1:0]),
|
||||
.s_axis_tkeep (m1.axis.tdata[IN_WORDS[1]*WORD_W+:IN_WORDS[1]]),
|
||||
.s_axis_tlast (m1.axis.tlast),
|
||||
.s_axis_tvalid(m1.axis.tvalid),
|
||||
.s_axis_tready(m1.axis.tready),
|
||||
.m_axis_aclk (clk50),
|
||||
.m_axis_rst (areset),
|
||||
.m_axis_tdata (s1.axis.tdata[(OUT_WORDS[1]*WORD_W)-1:0]),
|
||||
.m_axis_tkeep (s1.axis.tdata[OUT_WORDS[1]*WORD_W+:OUT_WORDS[1]]),
|
||||
.m_axis_tlast (s1.axis.tlast),
|
||||
.m_axis_tvalid(s1.axis.tvalid),
|
||||
.m_axis_tready(s1.axis.tready)
|
||||
);
|
||||
|
||||
// A rational integer 4-to-3 downsizer
|
||||
axis_width_conv #(
|
||||
.WORD_W(WORD_W), .IN_WORDS(IN_WORDS[2]), .OUT_WORDS(OUT_WORDS[2]),
|
||||
.SYNC_CLKS(0), .PIPELINE("OUT")
|
||||
) dut2 (
|
||||
.s_axis_aclk (clk50),
|
||||
.s_axis_rst (areset),
|
||||
.s_axis_tdata (m2.axis.tdata[(IN_WORDS[2]*WORD_W)-1:0]),
|
||||
.s_axis_tkeep (m2.axis.tdata[IN_WORDS[2]*WORD_W+:IN_WORDS[2]]),
|
||||
.s_axis_tlast (m2.axis.tlast),
|
||||
.s_axis_tvalid(m2.axis.tvalid),
|
||||
.s_axis_tready(m2.axis.tready),
|
||||
.m_axis_aclk (clk200),
|
||||
.m_axis_rst (areset),
|
||||
.m_axis_tdata (s2.axis.tdata[(OUT_WORDS[2]*WORD_W)-1:0]),
|
||||
.m_axis_tkeep (s2.axis.tdata[OUT_WORDS[2]*WORD_W+:OUT_WORDS[2]]),
|
||||
.m_axis_tlast (s2.axis.tlast),
|
||||
.m_axis_tvalid(s2.axis.tvalid),
|
||||
.m_axis_tready(s2.axis.tready)
|
||||
);
|
||||
|
||||
// An integer 4-to-1 downsizer but with 2 words per cycle
|
||||
axis_width_conv #(
|
||||
.WORD_W(WORD_W), .IN_WORDS(IN_WORDS[3]), .OUT_WORDS(OUT_WORDS[3]),
|
||||
.SYNC_CLKS(0), .PIPELINE("NONE")
|
||||
) dut3 (
|
||||
.s_axis_aclk (clk50),
|
||||
.s_axis_rst (areset),
|
||||
.s_axis_tdata (m3.axis.tdata[(IN_WORDS[3]*WORD_W)-1:0]),
|
||||
.s_axis_tkeep (m3.axis.tdata[IN_WORDS[3]*WORD_W+:IN_WORDS[3]]),
|
||||
.s_axis_tlast (m3.axis.tlast),
|
||||
.s_axis_tvalid(m3.axis.tvalid),
|
||||
.s_axis_tready(m3.axis.tready),
|
||||
.m_axis_aclk (clk166),
|
||||
.m_axis_rst (areset),
|
||||
.m_axis_tdata (s3.axis.tdata[(OUT_WORDS[3]*WORD_W)-1:0]),
|
||||
.m_axis_tkeep (s3.axis.tdata[OUT_WORDS[3]*WORD_W+:OUT_WORDS[3]]),
|
||||
.m_axis_tlast (s3.axis.tlast),
|
||||
.m_axis_tvalid(s3.axis.tvalid),
|
||||
.m_axis_tready(s3.axis.tready)
|
||||
);
|
||||
|
||||
// A passthrough module (no up/down sizing) but with 8 words per cycle
|
||||
axis_width_conv #(
|
||||
.WORD_W(WORD_W), .IN_WORDS(IN_WORDS[4]), .OUT_WORDS(OUT_WORDS[4]),
|
||||
.SYNC_CLKS(0), .PIPELINE("INOUT")
|
||||
) dut4 (
|
||||
.s_axis_aclk (clk50),
|
||||
.s_axis_rst (areset),
|
||||
.s_axis_tdata (m4.axis.tdata[(IN_WORDS[4]*WORD_W)-1:0]),
|
||||
.s_axis_tkeep (m4.axis.tdata[IN_WORDS[4]*WORD_W+:IN_WORDS[4]]),
|
||||
.s_axis_tlast (m4.axis.tlast),
|
||||
.s_axis_tvalid(m4.axis.tvalid),
|
||||
.s_axis_tready(m4.axis.tready),
|
||||
.m_axis_aclk (clk166),
|
||||
.m_axis_rst (areset),
|
||||
.m_axis_tdata (s4.axis.tdata[(OUT_WORDS[4]*WORD_W)-1:0]),
|
||||
.m_axis_tkeep (s4.axis.tdata[OUT_WORDS[4]*WORD_W+:OUT_WORDS[4]]),
|
||||
.m_axis_tlast (s4.axis.tlast),
|
||||
.m_axis_tvalid(s4.axis.tvalid),
|
||||
.m_axis_tready(s4.axis.tready)
|
||||
);
|
||||
|
||||
// A rational integer 17-to-19 upsizer
|
||||
axis_width_conv #(
|
||||
.WORD_W(WORD_W), .IN_WORDS(IN_WORDS[5]), .OUT_WORDS(OUT_WORDS[5]),
|
||||
.SYNC_CLKS(1), .PIPELINE("INOUT")
|
||||
) dut5 (
|
||||
.s_axis_aclk (clk50),
|
||||
.s_axis_rst (areset),
|
||||
.s_axis_tdata (m5.axis.tdata[(IN_WORDS[5]*WORD_W)-1:0]),
|
||||
.s_axis_tkeep (m5.axis.tdata[IN_WORDS[5]*WORD_W+:IN_WORDS[5]]),
|
||||
.s_axis_tlast (m5.axis.tlast),
|
||||
.s_axis_tvalid(m5.axis.tvalid),
|
||||
.s_axis_tready(m5.axis.tready),
|
||||
.m_axis_aclk (clk50),
|
||||
.m_axis_rst (areset),
|
||||
.m_axis_tdata (s5.axis.tdata[(OUT_WORDS[5]*WORD_W)-1:0]),
|
||||
.m_axis_tkeep (s5.axis.tdata[OUT_WORDS[5]*WORD_W+:OUT_WORDS[5]]),
|
||||
.m_axis_tlast (s5.axis.tlast),
|
||||
.m_axis_tvalid(s5.axis.tvalid),
|
||||
.m_axis_tready(s5.axis.tready)
|
||||
);
|
||||
|
||||
// Push a test ramp packet into the specific instance of the module
|
||||
// - words: The size of the packet in words
|
||||
// - inst: The instance number of the module to send to
|
||||
// - gaps: If 1 then insert bubble cycles randomly in the stream
|
||||
task push_test_pkt(input integer words, input integer inst, input logic gaps);
|
||||
begin
|
||||
logic [(MAX_IN_WORDS*WORD_W)-1:0] data = 0;
|
||||
logic [MAX_IN_WORDS-1:0] keep = 0;
|
||||
logic last = 0;
|
||||
integer nspc = IN_WORDS[inst];
|
||||
integer lines = words/nspc;
|
||||
integer residue = words % nspc;
|
||||
if (residue != 0) begin
|
||||
lines = lines + 1;
|
||||
end
|
||||
for (int l = 0; l < lines; l=l+1) begin
|
||||
last = (l == lines-1);
|
||||
for (int p = 0; p < nspc; p=p+1) begin
|
||||
data[p*WORD_W+:WORD_W] = (l*nspc)+p;
|
||||
end
|
||||
keep = (last && (residue != 0)) ? (1<<residue)-1 : (1<<nspc)-1;
|
||||
if (inst == 0)
|
||||
m0.push_word({keep[IN_WORDS[0]-1:0], data[(IN_WORDS[0]*WORD_W)-1:0]}, last);
|
||||
else if (inst == 1)
|
||||
m1.push_word({keep[IN_WORDS[1]-1:0], data[(IN_WORDS[1]*WORD_W)-1:0]}, last);
|
||||
else if (inst == 2)
|
||||
m2.push_word({keep[IN_WORDS[2]-1:0], data[(IN_WORDS[2]*WORD_W)-1:0]}, last);
|
||||
else if (inst == 3)
|
||||
m3.push_word({keep[IN_WORDS[3]-1:0], data[(IN_WORDS[3]*WORD_W)-1:0]}, last);
|
||||
else if (inst == 4)
|
||||
m4.push_word({keep[IN_WORDS[4]-1:0], data[(IN_WORDS[4]*WORD_W)-1:0]}, last);
|
||||
else
|
||||
m5.push_word({keep[IN_WORDS[5]-1:0], data[(IN_WORDS[5]*WORD_W)-1:0]}, last);
|
||||
|
||||
// Keep tvalid deasserted randomly introduce gaps
|
||||
if (gaps) begin
|
||||
integer r = $urandom_range(0, 100);
|
||||
if (r < 20) repeat(r) @(posedge clk50);
|
||||
end
|
||||
// $display("PUSH(%02d)[%03d]: D{%0x}, K{%0b}, L{%0b}", inst, l, data, keep, last);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
// Pull a test ramp packet from the specific instance of the module
|
||||
// - words: The size of the packet in words
|
||||
// - inst: The instance number of the module to send to
|
||||
// - gaps: If 1 then insert bubble cycles randomly in the stream
|
||||
// - ok: If 1 then all sanity checks have passed
|
||||
task pull_test_pkt(input integer words, input integer inst, input logic gaps, output logic ok);
|
||||
begin
|
||||
logic [(MAX_OUT_WORDS*WORD_W)-1:0] pull_data = 0;
|
||||
logic [MAX_OUT_WORDS-1:0] pull_keep = 0;
|
||||
logic pull_last = 0;
|
||||
|
||||
logic [(MAX_OUT_WORDS*WORD_W)-1:0] data = 0;
|
||||
logic [MAX_OUT_WORDS-1:0] keep = 0;
|
||||
logic last = 0;
|
||||
logic [(MAX_OUT_WORDS*WORD_W)-1:0] mask = 0;
|
||||
integer nspc = OUT_WORDS[inst];
|
||||
integer lines = words/nspc;
|
||||
integer residue = words % nspc;
|
||||
if (residue != 0) begin
|
||||
lines = lines + 1;
|
||||
end
|
||||
for (int l = 0; l < lines; l=l+1) begin
|
||||
last = (l == lines-1);
|
||||
for (int p = 0; p < nspc; p=p+1) begin
|
||||
data[p*WORD_W+:WORD_W] = (l*nspc)+p;
|
||||
end
|
||||
keep = (last && (residue != 0)) ? (1<<residue)-1 : (1<<nspc)-1;
|
||||
mask = (last && (residue != 0)) ? (1<<(residue*WORD_W))-1 : (1<<(nspc*WORD_W))-1;
|
||||
if (inst == 0)
|
||||
s0.pull_word({pull_keep[OUT_WORDS[0]-1:0], pull_data[(OUT_WORDS[0]*WORD_W)-1:0]}, pull_last);
|
||||
else if (inst == 1)
|
||||
s1.pull_word({pull_keep[OUT_WORDS[1]-1:0], pull_data[(OUT_WORDS[1]*WORD_W)-1:0]}, pull_last);
|
||||
else if (inst == 2)
|
||||
s2.pull_word({pull_keep[OUT_WORDS[2]-1:0], pull_data[(OUT_WORDS[2]*WORD_W)-1:0]}, pull_last);
|
||||
else if (inst == 3)
|
||||
s3.pull_word({pull_keep[OUT_WORDS[3]-1:0], pull_data[(OUT_WORDS[3]*WORD_W)-1:0]}, pull_last);
|
||||
else if (inst == 4)
|
||||
s4.pull_word({pull_keep[OUT_WORDS[4]-1:0], pull_data[(OUT_WORDS[4]*WORD_W)-1:0]}, pull_last);
|
||||
else
|
||||
s5.pull_word({pull_keep[OUT_WORDS[5]-1:0], pull_data[(OUT_WORDS[5]*WORD_W)-1:0]}, pull_last);
|
||||
|
||||
// Keep tready deasserted randomly introduce gaps
|
||||
if (gaps) begin
|
||||
integer r = $urandom_range(0, 100);
|
||||
if (r < 20) repeat(r) @(posedge clk50);
|
||||
end
|
||||
// Check data, keep and last
|
||||
ok = ((data&mask) == (pull_data&mask)) && (keep == (pull_keep&((1<<nspc)-1))) && (last == pull_last);
|
||||
// $display("PULL(%02d)[%03d]: D{%0x =? %0x}, K{%0b =? %0b}, L{%0b =? %0b} ... %s",
|
||||
// inst, l, (data&mask), (pull_data&mask), keep, (pull_keep&((1<<nspc)-1)), last, pull_last, (ok?"OK":"FAIL"));
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
initial begin : tb_main
|
||||
string s;
|
||||
|
||||
`TEST_CASE_START("Wait for Reset");
|
||||
m0.reset();
|
||||
m1.reset();
|
||||
m2.reset();
|
||||
m3.reset();
|
||||
m4.reset();
|
||||
m5.reset();
|
||||
s0.reset();
|
||||
s1.reset();
|
||||
s2.reset();
|
||||
s3.reset();
|
||||
s4.reset();
|
||||
s5.reset();
|
||||
while (areset) @(posedge clk50);
|
||||
`TEST_CASE_DONE(~areset);
|
||||
|
||||
// Iterate through two modes:
|
||||
// - g == 0: Gapless send and receive. Transfer as fast as possible
|
||||
// - g == 1: Sender and receiver AXI streams will have random bubbles
|
||||
for (int g = 0; g < 2; g=g+1) begin
|
||||
// Iterate through the various instances of the module
|
||||
for (int i = 0; i < NINST; i=i+1) begin
|
||||
$sformat(s, "Testing Instance %0d (%0s gaps)", i, (g==0?"without":"with"));
|
||||
`TEST_CASE_START(s);
|
||||
fork
|
||||
begin
|
||||
// Send packets of increasing size (up to MAX_SPP) to test all
|
||||
// configurations of tkeep and tlast.
|
||||
for (int n = 1; n <= MAX_SPP; n=n+1) begin
|
||||
push_test_pkt(n, i, g);
|
||||
end
|
||||
end
|
||||
begin
|
||||
logic ok;
|
||||
// Receive packets of increasing size and validate tlast, tkeep and tdata
|
||||
for (int n = 1; n <= MAX_SPP; n=n+1) begin
|
||||
pull_test_pkt(n, i, g, ok);
|
||||
$sformat(s, "Packet Validation Failed! (Size=%0d)", n);
|
||||
`ASSERT_ERROR(ok, s);
|
||||
end
|
||||
end
|
||||
join
|
||||
// Gaps to separate the tests in the wfm viewer
|
||||
repeat (100) @(posedge clk50);
|
||||
`TEST_CASE_DONE(1'b1);
|
||||
end
|
||||
end
|
||||
|
||||
`TEST_BENCH_DONE;
|
||||
end
|
||||
endmodule
|
||||
Reference in New Issue
Block a user