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Merge FPGA repository back into UHD repository

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The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>


Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
2020-01-28 09:35:36 -08:00
co-authored by Alex Williams Andrej Rode Ashish Chaudhari Ben Hilburn Ciro Nishiguchi Daniel Jepson Derek Kozel EJ Kreinar Humberto Jimenez Ian Buckley Jörg Hofrichter Jon Kiser Josh Blum Jonathon Pendlum Matt Ettus Michael West Moritz Fischer Nick Foster Nicolas Cuervo Paul Butler Paul David Ryan Marlow Sugandha Gupta Sylvain Munaut Trung Tran Vidush Vishwanath Wade Fife
parent 74893643ca
commit 6b67702ad7
2157 changed files with 1282567 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/rfnoc/utils/ctrlport_to_settings_bus.v
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//
// Copyright 2019 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: ctrlport_to_settings_bus
//
// Description:
//
// Converts CTRL port interface requests to a user register settings bus
// access. This can be used to connect RFNoC block IP settings registers and
// user read-back registers to a control port.
//
// There are a few key differences between control port and the settings bus
// that need to be accounted for.
//
// * Control port uses byte address whereas the settings bus uses a
// word address.
// * Control port is 32-bit whereas the settings bus supports
// 32-bit writes and 64-bit reads.
// * The settings bus always does both a write and a read for each
// transaction. If the intent is to read a register, then it writes the
// address for the read to SR_RB_ADDR. If the intent is to write a
// register, then the read result is ignored.
//
// This block handles these differences by allocating a 2048-byte address
// space to each settings bus. Each word of the settings bus is treated like
// a 64-bit word on an eight-byte boundary. To write to a settings register
// N, simply write a 32-bit value to address N*8. To read read-back register
// N, simply perform a 32-bit read from address N*8 followed by a 32-bit read
// from address N*8+4 to get the full 64-bits. If only the lower 32-bits are
// needed then it is not necessary to read the upper 32 bits. Note however,
// that software must always read the lower 32-bits before trying to read the
// upper 32-bits and that these reads should be atomic (no intervening reads
// should occur).
//
// Parameters:
//
// NUM_PORTS : The number of settings buses you wish to connect
//
// SR_RB_ADDR : Address to use for the settings register that holds the
// read-back address. Set to 124 to model register access to
// user logic registers. Set to 127 to model access to internal
// NoC shell registers.
//
// USE_TIME : When 0, timestamps are simply passed from ctrlport to
// settings bus and the timestamp input is not used. When 1,
// this block will wait until the indicated time to arrive on
// the timestamp input before issuing the transaction on the
// settings bus. In this case, the time must be provided on the
// timestamp input.
//
module ctrlport_to_settings_bus #(
parameter NUM_PORTS = 1,
parameter SR_RB_ADDR = 124,
parameter USE_TIME = 0
) (
input wire ctrlport_clk,
input wire ctrlport_rst,
//---------------------------------------------------------------------------
// CTRL Port Interface
//---------------------------------------------------------------------------
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
input wire s_ctrlport_req_has_time,
input wire [63:0] s_ctrlport_req_time,
output reg s_ctrlport_resp_ack = 0,
output reg [31:0] s_ctrlport_resp_data,
//---------------------------------------------------------------------------
// Settings Bus Interface
//---------------------------------------------------------------------------
output wire [NUM_PORTS*32-1:0] set_data,
output wire [ NUM_PORTS*8-1:0] set_addr,
output reg [ NUM_PORTS-1:0] set_stb = 0,
output wire [NUM_PORTS*64-1:0] set_time,
output wire [ NUM_PORTS-1:0] set_has_time,
input [NUM_PORTS-1:0] rb_stb,
output [NUM_PORTS*8-1:0] rb_addr,
input [NUM_PORTS*64-1:0] rb_data,
//---------------------------------------------------------------------------
// Timestamp
//---------------------------------------------------------------------------
// Current timestamp, synchronous to ctrlport_clk
input wire [63:0] timestamp
);
localparam PORT_W = (NUM_PORTS > 1) ? $clog2(NUM_PORTS) : 1;
wire [PORT_W-1:0] port_num;
reg [PORT_W-1:0] port_num_reg;
wire msw_access;
reg [31:0] set_data_reg;
reg [ 7:0] set_addr_reg;
reg [63:0] set_time_reg;
reg set_has_time_reg;
reg [ 7:0] rb_addr_reg;
reg [31:0] upper_word;
// Extract the port index from the address (the bits above the lower 11 bits)
assign port_num = (NUM_PORTS > 1) ? s_ctrlport_req_addr[(PORT_W+11)-1:11] : 0;
// Determine if the upper word is being accessed
assign msw_access = s_ctrlport_req_addr[2];
localparam ST_IDLE = 0;
localparam ST_TIME_CHECK = 1;
localparam ST_STROBE_WAIT = 2;
localparam ST_WAIT_RESP = 3;
reg [2:0] state = ST_IDLE;
always @(posedge ctrlport_clk) begin
if (ctrlport_rst) begin
s_ctrlport_resp_ack <= 0;
set_stb <= 0;
state <= ST_IDLE;
s_ctrlport_resp_data <= 32'hX;
set_addr_reg <= 8'hX;
rb_addr_reg <= 8'hX;
port_num_reg <= 8'hX;
upper_word <= 32'hX;
end else begin
// Default assignments
s_ctrlport_resp_ack <= 0;
set_stb <= 0;
case (state)
ST_IDLE : begin
if (s_ctrlport_req_rd && port_num < NUM_PORTS) begin
// Handle register reads (read-back registers)
if (msw_access) begin
// Reading the upper word always returns the cached upper-word value
// from the previous lower-word read.
s_ctrlport_resp_ack <= 1;
s_ctrlport_resp_data <= upper_word;
end else begin
// Handle register reads (read-back registers)
rb_addr_reg <= s_ctrlport_req_addr[10:3];
// Read-back of a user register on settings bus is always
// combined with a write to the SR_RB_ADDR address.
set_addr_reg <= SR_RB_ADDR;
set_data_reg <= 32'bX; // CtrlPort has no data in this case
set_time_reg <= s_ctrlport_req_time;
set_has_time_reg <= s_ctrlport_req_has_time;
// Save which port the read is for so that we only watch for
// acknowledgments from that port.
port_num_reg <= port_num;
if (USE_TIME) begin
state <= ST_TIME_CHECK;
end else begin
set_stb[port_num] <= 1;
state <= ST_STROBE_WAIT;
end
end
end else if (s_ctrlport_req_wr && port_num < NUM_PORTS) begin
// Handle register writes (settings registers)
set_addr_reg <= s_ctrlport_req_addr[10:3];
set_data_reg <= s_ctrlport_req_data;
set_time_reg <= s_ctrlport_req_time;
set_has_time_reg <= s_ctrlport_req_has_time;
// Save which port the write is for so that we only watch for
// acknowledgments from that port.
port_num_reg <= port_num;
if (USE_TIME) begin
state <= ST_TIME_CHECK;
end else begin
set_stb[port_num] <= 1;
state <= ST_STROBE_WAIT;
end
end
end
ST_TIME_CHECK : begin
// If the transaction is timed, wait until the time arrives before
// starting. This state is only reachable if USE_TIME is true.
if (set_has_time_reg) begin
if (timestamp >= set_time_reg) begin
set_stb[port_num_reg] <= 1;
state <= ST_STROBE_WAIT;
end
end else begin
set_stb[port_num_reg] <= 1;
state <= ST_STROBE_WAIT;
end
end
ST_STROBE_WAIT : begin
// Wait a cycle before checking for a response
state <= ST_WAIT_RESP;
end
ST_WAIT_RESP : begin
// Wait for read completion on settings bus, acknowledged by rb_stb.
// The read-back data will be ignored by ctrlport if this is a write.
upper_word <= rb_data[(64*port_num_reg + 32) +: 32];
s_ctrlport_resp_data <= rb_data[(64*port_num_reg + 0) +: 32];
if (rb_stb[port_num_reg] == 1) begin
s_ctrlport_resp_ack <= 1;
state <= ST_IDLE;
end
end
endcase
end
end
genvar i;
generate
for (i = 0; i < NUM_PORTS; i = i+1) begin : gen_settings_bus
// Drive all settings buses with the same values, except the strobe
assign rb_addr [ 8*i +: 8] = rb_addr_reg;
assign set_data [32*i +: 32] = set_data_reg;
assign set_addr [ 8*i +: 8] = set_addr_reg;
assign set_time [64*i +: 64] = set_time_reg;
assign set_has_time [ i] = set_has_time_reg;
end
endgenerate
endmodule