Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
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//
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// Copyright 2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_decoder
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//
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// Description:
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//
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// This block splits a single control port interface into multiple. It is used
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// when you have a single master that needs to access multiple slaves. For
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// example, a NoC block where the registers are implemented in multiple
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// submodules that must be read/written by a single NoC shell.
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//
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// This version also implements address decoding. The request is passed to a
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// slave only if the address falls within that slave's address space. Each
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// slave is given an address space of 2**ADDR_W and the first slave starts at
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// address BASE_ADDR. In other words, the request address is partitioned as
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// shown below.
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//
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// |---------------- 32-bit -----------------|
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// | Base | Port Num | Slave Addr |
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// |-----------------------------------------|
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//
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// When passed to the slave, the base address and port number bits are stripped
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// from the request address and only the SLAVE_ADDR_W-bit address is passed
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// through.
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//
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// Parameters:
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//
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// NUM_SLAVES : Number of slave devices that you want to connect to master.
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// BASE_ADDR : Base address for slave 0. This should be a power-of-2
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// multiple of the combined slave address spaces.
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// SLAVE_ADDR_W : Number of address bits to allocate to each slave.
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//
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module ctrlport_decoder #(
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parameter NUM_SLAVES = 2,
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parameter BASE_ADDR = 0,
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parameter SLAVE_ADDR_W = 8
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) (
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// Slave Interface
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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input wire [ 3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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output reg s_ctrlport_resp_ack = 1'b0,
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output reg [ 1:0] s_ctrlport_resp_status,
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output reg [31:0] s_ctrlport_resp_data,
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// Master Interfaces
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output reg [ NUM_SLAVES-1:0] m_ctrlport_req_wr = 0,
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output reg [ NUM_SLAVES-1:0] m_ctrlport_req_rd = 0,
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output reg [20*NUM_SLAVES-1:0] m_ctrlport_req_addr = 0,
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output reg [32*NUM_SLAVES-1:0] m_ctrlport_req_data,
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output reg [ 4*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
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output reg [ NUM_SLAVES-1:0] m_ctrlport_req_has_time,
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output reg [64*NUM_SLAVES-1:0] m_ctrlport_req_time,
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input wire [ NUM_SLAVES-1:0] m_ctrlport_resp_ack,
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input wire [ 2*NUM_SLAVES-1:0] m_ctrlport_resp_status,
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input wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data
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);
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localparam PORT_NUM_W = $clog2(NUM_SLAVES);
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localparam PORT_NUM_POS = SLAVE_ADDR_W;
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localparam BASE_ADDR_W = 20 - (SLAVE_ADDR_W + PORT_NUM_W);
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localparam BASE_ADDR_POS = SLAVE_ADDR_W + PORT_NUM_W;
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localparam [19:0] BASE_ADDR_MASK = { BASE_ADDR_W {1'b1}} << BASE_ADDR_POS;
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//---------------------------------------------------------------------------
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// Split the requests among the slaves
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//---------------------------------------------------------------------------
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wire [NUM_SLAVES-1:0] decoder;
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genvar i;
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for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split
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// Check if the upper bits of the request address match each slave. If the
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// address matches, set the corresponding decoder[] bit.
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if (PORT_NUM_W == 0) begin
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// Only one port in this case, so there are no port number bits to check
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assign decoder[i] = ((s_ctrlport_req_addr & BASE_ADDR_MASK) == BASE_ADDR);
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end else begin
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assign decoder[i] = ((s_ctrlport_req_addr & BASE_ADDR_MASK) == BASE_ADDR) &&
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(s_ctrlport_req_addr[PORT_NUM_POS +: PORT_NUM_W] == i);
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end
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always @(posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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m_ctrlport_req_wr[i] <= 1'b0;
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m_ctrlport_req_rd[i] <= 1'b0;
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end else begin
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// Mask WR and RD based on address decoding
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m_ctrlport_req_wr[i] <= s_ctrlport_req_wr & decoder[i];
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m_ctrlport_req_rd[i] <= s_ctrlport_req_rd & decoder[i];
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// Other values pass through to all slaves, but should be ignored
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// unless the corresponding WR or RD is not asserted.
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m_ctrlport_req_data [32*i +: 32] <= s_ctrlport_req_data;
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m_ctrlport_req_byte_en [4*i +: 4] <= s_ctrlport_req_byte_en;
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m_ctrlport_req_has_time[i] <= s_ctrlport_req_has_time;
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m_ctrlport_req_time [64*i +: 64] <= s_ctrlport_req_time;
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// Pass through only the relevant slave bits
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m_ctrlport_req_addr[20*i+:20] <= 20'b0;
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m_ctrlport_req_addr[20*i+:SLAVE_ADDR_W] <= s_ctrlport_req_addr[SLAVE_ADDR_W-1:0];
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end
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end
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end
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//---------------------------------------------------------------------------
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// Decode the responses
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//---------------------------------------------------------------------------
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reg [31:0] data;
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reg [ 1:0] status;
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reg ack = 0;
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// Take the responses and mask them with ack, then OR them together
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always @(*) begin : comb_decode
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integer s;
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data = 0;
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status = 0;
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ack = 0;
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for (s = 0; s < NUM_SLAVES; s = s+1) begin
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data = data | (m_ctrlport_resp_data [s*32 +: 32] & {32{m_ctrlport_resp_ack[s]}});
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status = status | (m_ctrlport_resp_status[s* 2 +: 2] & { 2{m_ctrlport_resp_ack[s]}});
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ack = ack | m_ctrlport_resp_ack[s];
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end
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end
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// Register the output to break combinatorial path
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always @(posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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s_ctrlport_resp_ack <= 0;
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end else begin
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s_ctrlport_resp_data <= data;
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s_ctrlport_resp_status <= status;
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s_ctrlport_resp_ack <= ack;
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end
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end
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endmodule
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