Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,45 @@
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#
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# Copyright 2019 Ettus Research, A National Instruments Company
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
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DESIGN_SRCS += $(abspath \
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$(RFNOC_CORE_SRCS) \
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$(RFNOC_XBAR_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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SIM_TOP = axis_pyld_ctxt_converter_tb
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SIM_SRCS = \
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$(abspath axis_pyld_ctxt_converter_tb.sv) \
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# MODELSIM_USER_DO = $(abspath wave.do)
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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@@ -0,0 +1,465 @@
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//
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// Copyright 2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axis_pyld_ctxt_converter_tb
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//
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`default_nettype none
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module axis_pyld_ctxt_converter_tb;
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// ----------------------------------------
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// Global settings
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// ----------------------------------------
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// Include macros and time declarations for use with PkgTestExec
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`include "test_exec.svh"
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import PkgTestExec::*;
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import PkgAxiStreamBfm::*;
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import PkgChdrUtils::*;
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import PkgChdrBfm::*;
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// Parameters
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localparam bit VERBOSE = 0;
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localparam int CHDR_W = 64;
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localparam int MTU = 7;
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localparam int MTU_BITS = (1 << MTU) * CHDR_W;
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localparam int NINST = 6;
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localparam int START_INST = 0;
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localparam int STOP_INST = NINST-1;
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localparam int NUM_PKTS_PER_TEST = 100;
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localparam int FAST_STALL_PROB = 0;
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localparam int SLOW_STALL_PROB = 35;
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localparam realtime CHDR_CLK_PERIOD = 3.0;
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localparam int MAX_PYLD_W = 256;
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typedef struct {
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realtime clk_period;
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int item_w;
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int nipc;
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int ctxt_fifo;
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int pyld_fifo;
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bit prefetch;
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} inst_params_t;
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// Module instances to test
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localparam inst_params_t INST_PARAMS[0:NINST-1] = {
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'{clk_period: 6.0, item_w:64, nipc: 1, ctxt_fifo:5, pyld_fifo:7, prefetch:1},
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'{clk_period:20.0, item_w:32, nipc: 6, ctxt_fifo:5, pyld_fifo:1, prefetch:1},
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'{clk_period: 3.0, item_w:32, nipc: 4, ctxt_fifo:1, pyld_fifo:2, prefetch:0},
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'{clk_period:10.0, item_w:16, nipc: 4, ctxt_fifo:8, pyld_fifo:5, prefetch:1},
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'{clk_period: 3.0, item_w:32, nipc: 2, ctxt_fifo:1, pyld_fifo:7, prefetch:0},
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'{clk_period: 3.0, item_w:8, nipc:13, ctxt_fifo:1, pyld_fifo:7, prefetch:0}
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};
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// ----------------------------------------
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// Interfaces and clocks
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// ----------------------------------------
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// Clocks and resets
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bit rfnoc_chdr_clk, rfnoc_chdr_rst;
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bit [NINST-1:0] rfnoc_data_clk, rfnoc_data_rst;
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// Common CHDR Clock
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sim_clock_gen #(CHDR_CLK_PERIOD) chdr_clk_gen_i (rfnoc_chdr_clk, rfnoc_chdr_rst);
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// Flush interface
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logic [31:0] r2c_framer_errors[0:NINST-1];
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logic [31:0] r2c_flush_timeout[0:NINST-1], c2r_flush_timeout[0:NINST-1];
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logic [0:0] r2c_flush_en [0:NINST-1], c2r_flush_en [0:NINST-1];
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wire [0:0] r2c_flush_active [0:NINST-1], c2r_flush_active [0:NINST-1];
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wire [0:0] r2c_flush_done [0:NINST-1], c2r_flush_done [0:NINST-1];
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// CHDR interface
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wire [CHDR_W-1:0] chdr_tdata [0:NINST-1];
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wire chdr_tlast [0:NINST-1];
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wire chdr_tvalid[0:NINST-1];
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wire chdr_tready[0:NINST-1];
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// AXIS interfaces and BFMs
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AxiStreamIf #(CHDR_W, 4) r2c_ctxt [0:NINST-1] ();
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AxiStreamIf #(CHDR_W, 4) c2r_ctxt [0:NINST-1] ();
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AxiStreamIf #(MAX_PYLD_W) r2c_pyld [0:NINST-1] ();
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AxiStreamIf #(MAX_PYLD_W) c2r_pyld [0:NINST-1] ();
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AxiStreamBfm #(CHDR_W, 4) ctxt_bfm [0:NINST-1] ;
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AxiStreamBfm #(MAX_PYLD_W) pyld_bfm [0:NINST-1] ;
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// Instantiate DUTs
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genvar inst_i;
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generate for (inst_i = 0; inst_i < NINST; inst_i++) begin: inst
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// Assign clocks and resets to ctxt and pyld streams
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assign r2c_ctxt[inst_i].clk = rfnoc_data_clk[inst_i];
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assign r2c_ctxt[inst_i].rst = rfnoc_data_rst[inst_i];
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assign c2r_ctxt[inst_i].clk = rfnoc_data_clk[inst_i];
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assign c2r_ctxt[inst_i].rst = rfnoc_data_rst[inst_i];
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assign r2c_pyld[inst_i].clk = rfnoc_data_clk[inst_i];
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assign r2c_pyld[inst_i].rst = rfnoc_data_rst[inst_i];
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assign c2r_pyld[inst_i].clk = rfnoc_data_clk[inst_i];
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assign c2r_pyld[inst_i].rst = rfnoc_data_rst[inst_i];
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// Instantiate clock generator
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sim_clock_gen #(INST_PARAMS[inst_i].clk_period) dclk_gen (
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rfnoc_data_clk[inst_i], rfnoc_data_rst[inst_i]
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);
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// Instantiate PyldCtxt to Chdr DUT
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axis_pyld_ctxt_to_chdr #(
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.CHDR_W (CHDR_W),
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.ITEM_W (INST_PARAMS[inst_i].item_w),
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.NIPC (INST_PARAMS[inst_i].nipc),
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.SYNC_CLKS (INST_PARAMS[inst_i].clk_period == CHDR_CLK_PERIOD),
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.CONTEXT_FIFO_SIZE (INST_PARAMS[inst_i].ctxt_fifo),
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.PAYLOAD_FIFO_SIZE (INST_PARAMS[inst_i].pyld_fifo),
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.MTU (MTU),
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.CONTEXT_PREFETCH_EN (INST_PARAMS[inst_i].prefetch)
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) r2c_dut (
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.axis_chdr_clk (rfnoc_chdr_clk),
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.axis_chdr_rst (rfnoc_chdr_rst),
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.axis_data_clk (rfnoc_data_clk[inst_i]),
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.axis_data_rst (rfnoc_data_rst[inst_i]),
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.m_axis_chdr_tdata (chdr_tdata[inst_i]),
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.m_axis_chdr_tlast (chdr_tlast[inst_i]),
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.m_axis_chdr_tvalid (chdr_tvalid[inst_i]),
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.m_axis_chdr_tready (chdr_tready[inst_i]),
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.s_axis_payload_tdata (r2c_pyld[inst_i].slave.tdata[(INST_PARAMS[inst_i].item_w*INST_PARAMS[inst_i].nipc)-1:0]),
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.s_axis_payload_tkeep (r2c_pyld[inst_i].slave.tkeep[INST_PARAMS[inst_i].nipc-1:0]),
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.s_axis_payload_tlast (r2c_pyld[inst_i].slave.tlast),
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.s_axis_payload_tvalid(r2c_pyld[inst_i].slave.tvalid),
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.s_axis_payload_tready(r2c_pyld[inst_i].slave.tready),
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.s_axis_context_tdata (r2c_ctxt[inst_i].slave.tdata),
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.s_axis_context_tuser (r2c_ctxt[inst_i].slave.tuser),
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.s_axis_context_tlast (r2c_ctxt[inst_i].slave.tlast),
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.s_axis_context_tvalid(r2c_ctxt[inst_i].slave.tvalid),
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.s_axis_context_tready(r2c_ctxt[inst_i].slave.tready),
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.framer_errors (r2c_framer_errors[inst_i]),
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.flush_en (r2c_flush_en[inst_i]),
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.flush_timeout (r2c_flush_timeout[inst_i]),
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.flush_active (r2c_flush_active[inst_i]),
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.flush_done (r2c_flush_done[inst_i])
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);
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// Instantiate Chdr to PyldCtxt DUT
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chdr_to_axis_pyld_ctxt #(
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.CHDR_W (CHDR_W),
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.ITEM_W (INST_PARAMS[inst_i].item_w),
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.NIPC (INST_PARAMS[inst_i].nipc),
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.SYNC_CLKS (INST_PARAMS[inst_i].clk_period == CHDR_CLK_PERIOD),
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.CONTEXT_FIFO_SIZE (INST_PARAMS[inst_i].ctxt_fifo),
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.PAYLOAD_FIFO_SIZE (INST_PARAMS[inst_i].pyld_fifo),
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.CONTEXT_PREFETCH_EN (INST_PARAMS[inst_i].prefetch)
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) c2r_dut (
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.axis_chdr_clk (rfnoc_chdr_clk),
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.axis_chdr_rst (rfnoc_chdr_rst),
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.axis_data_clk (rfnoc_data_clk[inst_i]),
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.axis_data_rst (rfnoc_data_rst[inst_i]),
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.s_axis_chdr_tdata (chdr_tdata[inst_i]),
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.s_axis_chdr_tlast (chdr_tlast[inst_i]),
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.s_axis_chdr_tvalid (chdr_tvalid[inst_i]),
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.s_axis_chdr_tready (chdr_tready[inst_i]),
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.m_axis_payload_tdata (c2r_pyld[inst_i].master.tdata[(INST_PARAMS[inst_i].item_w*INST_PARAMS[inst_i].nipc)-1:0]),
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.m_axis_payload_tkeep (c2r_pyld[inst_i].master.tkeep[INST_PARAMS[inst_i].nipc-1:0]),
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.m_axis_payload_tlast (c2r_pyld[inst_i].master.tlast),
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.m_axis_payload_tvalid(c2r_pyld[inst_i].master.tvalid),
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.m_axis_payload_tready(c2r_pyld[inst_i].master.tready),
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.m_axis_context_tdata (c2r_ctxt[inst_i].master.tdata),
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.m_axis_context_tuser (c2r_ctxt[inst_i].master.tuser),
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.m_axis_context_tlast (c2r_ctxt[inst_i].master.tlast),
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.m_axis_context_tvalid(c2r_ctxt[inst_i].master.tvalid),
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.m_axis_context_tready(c2r_ctxt[inst_i].master.tready),
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.flush_en (c2r_flush_en[inst_i]),
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.flush_timeout (c2r_flush_timeout[inst_i]),
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.flush_active (c2r_flush_active[inst_i]),
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.flush_done (c2r_flush_done[inst_i])
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);
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// Assert Reset and start BFMs
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initial begin
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dclk_gen.reset();
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r2c_flush_en[inst_i] = 0;
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c2r_flush_en[inst_i] = 0;
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pyld_bfm[inst_i] = new(r2c_pyld[inst_i], c2r_pyld[inst_i]);
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pyld_bfm[inst_i].run();
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ctxt_bfm[inst_i] = new(r2c_ctxt[inst_i], c2r_ctxt[inst_i]);
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ctxt_bfm[inst_i].run();
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end
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end endgenerate
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function automatic bit pyld_pkts_equal(
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ref AxiStreamPacket #(MAX_PYLD_W) exp,
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ref AxiStreamPacket #(MAX_PYLD_W) act,
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input int item_w,
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input int nipc
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);
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if (exp.data.size() != act.data.size()) return 0;
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if (exp.keep.size() != act.keep.size()) return 0;
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for (int i = 0; i < exp.data.size(); i++) begin
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// Convert to bit
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automatic bit [MAX_PYLD_W-1:0] mask = '0;
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automatic bit [MAX_PYLD_W-1:0] data_exp = exp.data[i];
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automatic bit [MAX_PYLD_W-1:0] data_act = act.data[i];
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for (int r = 0; r < nipc; r++) begin
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if (exp.keep[i][r] === 1'b1) begin
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automatic bit [MAX_PYLD_W-1:0] samp_mask = ((1<<item_w)-1);
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mask |= (samp_mask << (r*item_w));
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end
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end
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if (exp.keep[i] !== act.keep[i]) return 0;
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if ((data_exp&mask) !== (data_act&mask)) return 0;
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end
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return 1;
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endfunction
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task automatic send_recv_data_packets(
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input int inst,
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input inst_params_t params, //We pass this separately to work around Vivado bug
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input int num_pkts,
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input int mst_stall_prob,
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input int slv_stall_prob,
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input bit flushing = 0
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);
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int nipc = params.nipc;
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int item_w = params.item_w;
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bit prefetch = params.prefetch;
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AxiStreamPacket #(MAX_PYLD_W) pyld_pkt_arr[$] = {};
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AxiStreamPacket #(CHDR_W, 4) ctxt_pkt_arr[$] = {};
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// Set stall probabilities
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ctxt_bfm[inst].set_master_stall_prob(mst_stall_prob);
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ctxt_bfm[inst].set_slave_stall_prob(slv_stall_prob);
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pyld_bfm[inst].set_master_stall_prob(mst_stall_prob);
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pyld_bfm[inst].set_slave_stall_prob(slv_stall_prob);
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// Generate a stream of data packets
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for (int p = 0; p < num_pkts; p++) begin
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int len_lines = $urandom_range((MTU_BITS/(item_w*nipc))-10, 1);
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int keep_int = $urandom_range(nipc, 1);
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pyld_pkt_arr[p] = new();
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||||
for (int i = 0; i < len_lines; i++) begin
|
||||
logic [MAX_PYLD_W-1:0] rand_samp;
|
||||
logic [(MAX_PYLD_W/8)-1:0] keep_val = 'x;
|
||||
for (int r = 0; r < (((nipc*item_w)+31)/32); r++)
|
||||
rand_samp[r*32 +: 32] = $urandom();
|
||||
pyld_pkt_arr[p].data.push_back(rand_samp);
|
||||
pyld_pkt_arr[p].user.push_back('x);
|
||||
for (int r = 0; r < nipc; r++) begin
|
||||
if (i == len_lines-1)
|
||||
keep_val[r] = (r < keep_int) ? 1'b1 : 1'b0;
|
||||
else
|
||||
keep_val[r] = 1'b1;
|
||||
end
|
||||
pyld_pkt_arr[p].keep.push_back(keep_val);
|
||||
end
|
||||
end
|
||||
|
||||
// Generate context packet for each data packet
|
||||
foreach (pyld_pkt_arr[p]) begin
|
||||
automatic chdr_header_t chdr_hdr;
|
||||
automatic bit has_time = $urandom_range(1);
|
||||
automatic int num_mdata = $urandom_range(5);
|
||||
automatic int num_pyld_lines = pyld_pkt_arr[p].data.size();
|
||||
automatic int invalid_samps = 0;
|
||||
automatic int length;
|
||||
for (int r = 0; r < nipc; r++)
|
||||
if (pyld_pkt_arr[p].keep[num_pyld_lines-1][r] === 1'b0)
|
||||
invalid_samps++;
|
||||
length =
|
||||
(CHDR_W/8) + // header
|
||||
((has_time && (CHDR_W == 64)) ? (CHDR_W/8) : 0) + // timestamp
|
||||
(num_mdata * (CHDR_W/8)) + // metadata
|
||||
(num_pyld_lines * nipc * (item_w/8)) + // payload
|
||||
(-invalid_samps * (item_w/8)); // payload (back out empty slots)
|
||||
|
||||
chdr_hdr = '{
|
||||
vc : $urandom_range(63),
|
||||
eob : $urandom_range(1),
|
||||
eov : $urandom_range(1),
|
||||
pkt_type : has_time ? CHDR_DATA_WITH_TS : CHDR_DATA_NO_TS,
|
||||
num_mdata : num_mdata,
|
||||
seq_num : p,
|
||||
length : length,
|
||||
dst_epid : $urandom()
|
||||
};
|
||||
|
||||
ctxt_pkt_arr[p] = new();
|
||||
ctxt_pkt_arr[p].data.push_back(chdr_hdr);
|
||||
ctxt_pkt_arr[p].user.push_back((has_time && (CHDR_W > 64)) ? CONTEXT_FIELD_HDR_TS : CONTEXT_FIELD_HDR);
|
||||
ctxt_pkt_arr[p].keep.push_back('x);
|
||||
if (has_time && (CHDR_W == 64)) begin
|
||||
ctxt_pkt_arr[p].data.push_back(~p);
|
||||
ctxt_pkt_arr[p].user.push_back(CONTEXT_FIELD_TS);
|
||||
ctxt_pkt_arr[p].keep.push_back('x);
|
||||
end
|
||||
for (int i = 0; i < num_mdata; i++) begin
|
||||
ctxt_pkt_arr[p].data.push_back(i);
|
||||
ctxt_pkt_arr[p].user.push_back(CONTEXT_FIELD_MDATA);
|
||||
ctxt_pkt_arr[p].keep.push_back('x);
|
||||
end
|
||||
end
|
||||
|
||||
// Spin up 4 threads: {RX, TX} x {Context, Payload}
|
||||
fork
|
||||
begin: tx_context
|
||||
timeout_t timeout;
|
||||
for (int p = 0; p < num_pkts; p++) begin
|
||||
test.start_timeout(timeout, 50us, "Waiting to send TX context pkt");
|
||||
ctxt_bfm[inst].put(ctxt_pkt_arr[p].copy());
|
||||
test.end_timeout(timeout);
|
||||
if (VERBOSE) $display("[INST%0d:TxContext:%0d]\n%s", inst, p, ctxt_pkt_arr[p].sprint());
|
||||
end
|
||||
end
|
||||
begin: tx_payload
|
||||
timeout_t timeout;
|
||||
for (int p = 0; p < num_pkts; p++) begin
|
||||
test.start_timeout(timeout, 50us, "Waiting to send TX payload pkt");
|
||||
pyld_bfm[inst].put(pyld_pkt_arr[p].copy());
|
||||
test.end_timeout(timeout);
|
||||
if (VERBOSE) $display("[INST%0d:TxPayload:%0d]\n%s", inst, p, pyld_pkt_arr[p].sprint());
|
||||
end
|
||||
end
|
||||
begin: rx_context
|
||||
if (!flushing) begin
|
||||
timeout_t timeout;
|
||||
automatic AxiStreamPacket #(CHDR_W, 4) rx_ctxt_pkt;
|
||||
for (int p = 0; p < num_pkts; p++) begin
|
||||
test.start_timeout(timeout, 50us, "Waiting to recv RX context pkt");
|
||||
ctxt_bfm[inst].get(rx_ctxt_pkt);
|
||||
test.end_timeout(timeout);
|
||||
if (VERBOSE) $display("[INST%0d:RxContext:%0d]\n%s", inst, p, rx_ctxt_pkt.sprint());
|
||||
if (VERBOSE) $display("[INST%0d:ExpContext:%0d]\n%s", inst, p, ctxt_pkt_arr[p].sprint());
|
||||
`ASSERT_ERROR(ctxt_pkt_arr[p].equal(rx_ctxt_pkt), "RX context packet did not match TX");
|
||||
end
|
||||
end
|
||||
end
|
||||
begin: rx_payload
|
||||
if (!flushing) begin
|
||||
timeout_t timeout;
|
||||
automatic AxiStreamPacket #(MAX_PYLD_W) rx_pyld_pkt;
|
||||
for (int p = 0; p < num_pkts; p++) begin
|
||||
test.start_timeout(timeout, 50us, "Waiting to recv RX payload pkt");
|
||||
pyld_bfm[inst].get(rx_pyld_pkt);
|
||||
test.end_timeout(timeout);
|
||||
if (VERBOSE) $display("[INST%0d:RxPayload:%0d]\n%s", inst, p, rx_pyld_pkt.sprint());
|
||||
if (VERBOSE) $display("[INST%0d:ExpPayload:%0d]\n%s", inst, p, pyld_pkt_arr[p].sprint());
|
||||
`ASSERT_ERROR(pyld_pkts_equal(pyld_pkt_arr[p], rx_pyld_pkt, item_w, nipc), "RX payload packet did not match TX");
|
||||
end
|
||||
end
|
||||
end
|
||||
join
|
||||
endtask
|
||||
|
||||
|
||||
// ----------------------------------------
|
||||
// Test Process
|
||||
// ----------------------------------------
|
||||
initial begin
|
||||
|
||||
// Shared Variables
|
||||
// ----------------------------------------
|
||||
timeout_t timeout;
|
||||
string tc_label;
|
||||
|
||||
// Initialize
|
||||
// ----------------------------------------
|
||||
test.start_tb("axis_pyld_ctxt_converter_tb");
|
||||
|
||||
// Reset
|
||||
// ----------------------------------------
|
||||
chdr_clk_gen_i.reset();
|
||||
|
||||
test.start_test("Wait for reset");
|
||||
test.start_timeout(timeout, 1us, "Waiting for reset");
|
||||
while (rfnoc_chdr_rst) @(posedge rfnoc_chdr_clk);
|
||||
while (|rfnoc_data_rst) @(posedge rfnoc_chdr_clk);
|
||||
repeat (100) @(posedge rfnoc_chdr_clk);
|
||||
test.end_timeout(timeout);
|
||||
`ASSERT_ERROR(!rfnoc_chdr_rst && !(|rfnoc_data_rst), "Reset did not deassert");
|
||||
test.end_test();
|
||||
|
||||
for (int inst_num = START_INST; inst_num <= STOP_INST; inst_num++) begin
|
||||
$display("-----------------------------------------------------------------------------------------------");
|
||||
$display("Testing INST%0d:%p", inst_num, INST_PARAMS[inst_num]);
|
||||
$display("-----------------------------------------------------------------------------------------------");
|
||||
|
||||
// Stream Random Data
|
||||
// ----------------------------------------
|
||||
for (int cfg = 0; cfg < 4; cfg++) begin
|
||||
automatic integer mst_cfg = cfg[0];
|
||||
automatic integer slv_cfg = cfg[1];
|
||||
$sformat(tc_label, "INST%0d: Stream Random Data (%s Mst, %s Slv)",
|
||||
inst_num,(mst_cfg?"Slow":"Fast"), (slv_cfg?"Slow":"Fast"));
|
||||
test.start_test(tc_label);
|
||||
send_recv_data_packets(inst_num, INST_PARAMS[inst_num], NUM_PKTS_PER_TEST,
|
||||
mst_cfg ? SLOW_STALL_PROB : FAST_STALL_PROB,
|
||||
slv_cfg ? SLOW_STALL_PROB : FAST_STALL_PROB
|
||||
);
|
||||
`ASSERT_ERROR(r2c_framer_errors[inst_num] === '0, "Encountered framer errors");
|
||||
test.end_test();
|
||||
end
|
||||
|
||||
// Flush
|
||||
// ----------------------------------------
|
||||
$sformat(tc_label, "INST%0d: Flush PyldCtxt => CHDR (Idle)", inst_num);
|
||||
test.start_test(tc_label);
|
||||
r2c_flush_timeout[inst_num] = $urandom_range(400, 200);
|
||||
r2c_flush_en[inst_num] = 1'b1;
|
||||
repeat (100) @(posedge rfnoc_chdr_clk);
|
||||
`ASSERT_ERROR(r2c_flush_active[inst_num] === 1, "Flushing did not begin on time");
|
||||
`ASSERT_ERROR(r2c_flush_done[inst_num] === 0, "Flushing ended prematurely");
|
||||
repeat (r2c_flush_timeout[inst_num] + 1) @(posedge rfnoc_chdr_clk);
|
||||
`ASSERT_ERROR(r2c_flush_done[inst_num] === 1, "Flushing did not end on time");
|
||||
r2c_flush_en[inst_num] = 1'b0;
|
||||
@(posedge rfnoc_chdr_clk);
|
||||
test.end_test();
|
||||
|
||||
$sformat(tc_label, "INST%0d: Flush CHDR => PyldCtxt (Idle)", inst_num);
|
||||
test.start_test(tc_label);
|
||||
c2r_flush_timeout[inst_num] = $urandom_range(400, 200);
|
||||
c2r_flush_en[inst_num] = 1'b1;
|
||||
repeat (100) @(posedge rfnoc_data_clk[inst_num]);
|
||||
`ASSERT_ERROR(c2r_flush_active[inst_num] === 1, "Flushing did not begin on time");
|
||||
`ASSERT_ERROR(c2r_flush_done[inst_num] === 0, "Flushing ended prematurely");
|
||||
repeat (c2r_flush_timeout[inst_num] + 1) @(posedge rfnoc_data_clk[inst_num]);
|
||||
`ASSERT_ERROR(c2r_flush_done[inst_num] === 1, "Flushing did not end on time");
|
||||
c2r_flush_en[inst_num] = 1'b0;
|
||||
@(posedge rfnoc_data_clk[inst_num]);
|
||||
test.end_test();
|
||||
|
||||
$sformat(tc_label, "INST%0d: Flush PyldCtxt => CHDR (Streaming)", inst_num);
|
||||
test.start_test(tc_label);
|
||||
r2c_flush_timeout[inst_num] = $urandom_range(400, 200);
|
||||
r2c_flush_en[inst_num] = 1'b1;
|
||||
repeat (100) @(posedge rfnoc_chdr_clk);
|
||||
`ASSERT_ERROR(r2c_flush_active[inst_num] === 1, "Flushing did not begin on time");
|
||||
`ASSERT_ERROR(r2c_flush_done[inst_num] === 0, "Flushing ended prematurely");
|
||||
send_recv_data_packets(inst_num, INST_PARAMS[inst_num], NUM_PKTS_PER_TEST/10,
|
||||
FAST_STALL_PROB, FAST_STALL_PROB, 1 /*flushing*/
|
||||
);
|
||||
repeat (NUM_PKTS_PER_TEST/10 * (1<<MTU) * 4) @(posedge rfnoc_chdr_clk);
|
||||
repeat (r2c_flush_timeout[inst_num] + 1) @(posedge rfnoc_chdr_clk);
|
||||
`ASSERT_ERROR(r2c_flush_done[inst_num] === 1, "Flushing did not end on time");
|
||||
r2c_flush_en[inst_num] = 1'b0;
|
||||
@(posedge rfnoc_chdr_clk);
|
||||
test.end_test();
|
||||
|
||||
$sformat(tc_label, "INST%0d: Stream Data After Flush", inst_num);
|
||||
test.start_test(tc_label);
|
||||
send_recv_data_packets(inst_num, INST_PARAMS[inst_num], NUM_PKTS_PER_TEST/10,
|
||||
FAST_STALL_PROB, FAST_STALL_PROB
|
||||
);
|
||||
`ASSERT_ERROR(r2c_framer_errors[inst_num] === '0, "Encountered framer errors");
|
||||
test.end_test();
|
||||
end
|
||||
|
||||
// Finish Up
|
||||
// ----------------------------------------
|
||||
// Display final statistics and results
|
||||
test.end_tb();
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user