Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,45 @@
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#
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# Copyright 2019 Ettus Research, A National Instruments Company
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
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DESIGN_SRCS += $(abspath \
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$(RFNOC_CORE_SRCS) \
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$(RFNOC_XBAR_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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SIM_TOP = axis_pyld_ctxt_converter_tb
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SIM_SRCS = \
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$(abspath axis_pyld_ctxt_converter_tb.sv) \
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# MODELSIM_USER_DO = $(abspath wave.do)
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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@@ -0,0 +1,465 @@
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//
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// Copyright 2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axis_pyld_ctxt_converter_tb
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//
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`default_nettype none
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module axis_pyld_ctxt_converter_tb;
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// ----------------------------------------
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// Global settings
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// ----------------------------------------
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// Include macros and time declarations for use with PkgTestExec
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`include "test_exec.svh"
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import PkgTestExec::*;
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import PkgAxiStreamBfm::*;
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import PkgChdrUtils::*;
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import PkgChdrBfm::*;
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// Parameters
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localparam bit VERBOSE = 0;
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localparam int CHDR_W = 64;
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localparam int MTU = 7;
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localparam int MTU_BITS = (1 << MTU) * CHDR_W;
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localparam int NINST = 6;
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localparam int START_INST = 0;
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localparam int STOP_INST = NINST-1;
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localparam int NUM_PKTS_PER_TEST = 100;
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localparam int FAST_STALL_PROB = 0;
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localparam int SLOW_STALL_PROB = 35;
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localparam realtime CHDR_CLK_PERIOD = 3.0;
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localparam int MAX_PYLD_W = 256;
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typedef struct {
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realtime clk_period;
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int item_w;
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int nipc;
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int ctxt_fifo;
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int pyld_fifo;
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bit prefetch;
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} inst_params_t;
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// Module instances to test
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localparam inst_params_t INST_PARAMS[0:NINST-1] = {
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'{clk_period: 6.0, item_w:64, nipc: 1, ctxt_fifo:5, pyld_fifo:7, prefetch:1},
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'{clk_period:20.0, item_w:32, nipc: 6, ctxt_fifo:5, pyld_fifo:1, prefetch:1},
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'{clk_period: 3.0, item_w:32, nipc: 4, ctxt_fifo:1, pyld_fifo:2, prefetch:0},
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'{clk_period:10.0, item_w:16, nipc: 4, ctxt_fifo:8, pyld_fifo:5, prefetch:1},
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'{clk_period: 3.0, item_w:32, nipc: 2, ctxt_fifo:1, pyld_fifo:7, prefetch:0},
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'{clk_period: 3.0, item_w:8, nipc:13, ctxt_fifo:1, pyld_fifo:7, prefetch:0}
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};
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// ----------------------------------------
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// Interfaces and clocks
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// ----------------------------------------
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// Clocks and resets
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bit rfnoc_chdr_clk, rfnoc_chdr_rst;
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bit [NINST-1:0] rfnoc_data_clk, rfnoc_data_rst;
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// Common CHDR Clock
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sim_clock_gen #(CHDR_CLK_PERIOD) chdr_clk_gen_i (rfnoc_chdr_clk, rfnoc_chdr_rst);
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// Flush interface
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logic [31:0] r2c_framer_errors[0:NINST-1];
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logic [31:0] r2c_flush_timeout[0:NINST-1], c2r_flush_timeout[0:NINST-1];
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logic [0:0] r2c_flush_en [0:NINST-1], c2r_flush_en [0:NINST-1];
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wire [0:0] r2c_flush_active [0:NINST-1], c2r_flush_active [0:NINST-1];
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wire [0:0] r2c_flush_done [0:NINST-1], c2r_flush_done [0:NINST-1];
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// CHDR interface
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wire [CHDR_W-1:0] chdr_tdata [0:NINST-1];
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wire chdr_tlast [0:NINST-1];
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wire chdr_tvalid[0:NINST-1];
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wire chdr_tready[0:NINST-1];
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// AXIS interfaces and BFMs
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AxiStreamIf #(CHDR_W, 4) r2c_ctxt [0:NINST-1] ();
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AxiStreamIf #(CHDR_W, 4) c2r_ctxt [0:NINST-1] ();
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AxiStreamIf #(MAX_PYLD_W) r2c_pyld [0:NINST-1] ();
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AxiStreamIf #(MAX_PYLD_W) c2r_pyld [0:NINST-1] ();
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AxiStreamBfm #(CHDR_W, 4) ctxt_bfm [0:NINST-1] ;
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AxiStreamBfm #(MAX_PYLD_W) pyld_bfm [0:NINST-1] ;
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// Instantiate DUTs
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genvar inst_i;
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generate for (inst_i = 0; inst_i < NINST; inst_i++) begin: inst
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// Assign clocks and resets to ctxt and pyld streams
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assign r2c_ctxt[inst_i].clk = rfnoc_data_clk[inst_i];
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assign r2c_ctxt[inst_i].rst = rfnoc_data_rst[inst_i];
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assign c2r_ctxt[inst_i].clk = rfnoc_data_clk[inst_i];
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assign c2r_ctxt[inst_i].rst = rfnoc_data_rst[inst_i];
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assign r2c_pyld[inst_i].clk = rfnoc_data_clk[inst_i];
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assign r2c_pyld[inst_i].rst = rfnoc_data_rst[inst_i];
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assign c2r_pyld[inst_i].clk = rfnoc_data_clk[inst_i];
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assign c2r_pyld[inst_i].rst = rfnoc_data_rst[inst_i];
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// Instantiate clock generator
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sim_clock_gen #(INST_PARAMS[inst_i].clk_period) dclk_gen (
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rfnoc_data_clk[inst_i], rfnoc_data_rst[inst_i]
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);
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// Instantiate PyldCtxt to Chdr DUT
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axis_pyld_ctxt_to_chdr #(
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.CHDR_W (CHDR_W),
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.ITEM_W (INST_PARAMS[inst_i].item_w),
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.NIPC (INST_PARAMS[inst_i].nipc),
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.SYNC_CLKS (INST_PARAMS[inst_i].clk_period == CHDR_CLK_PERIOD),
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.CONTEXT_FIFO_SIZE (INST_PARAMS[inst_i].ctxt_fifo),
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.PAYLOAD_FIFO_SIZE (INST_PARAMS[inst_i].pyld_fifo),
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.MTU (MTU),
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.CONTEXT_PREFETCH_EN (INST_PARAMS[inst_i].prefetch)
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) r2c_dut (
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.axis_chdr_clk (rfnoc_chdr_clk),
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.axis_chdr_rst (rfnoc_chdr_rst),
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.axis_data_clk (rfnoc_data_clk[inst_i]),
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.axis_data_rst (rfnoc_data_rst[inst_i]),
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.m_axis_chdr_tdata (chdr_tdata[inst_i]),
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.m_axis_chdr_tlast (chdr_tlast[inst_i]),
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.m_axis_chdr_tvalid (chdr_tvalid[inst_i]),
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.m_axis_chdr_tready (chdr_tready[inst_i]),
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.s_axis_payload_tdata (r2c_pyld[inst_i].slave.tdata[(INST_PARAMS[inst_i].item_w*INST_PARAMS[inst_i].nipc)-1:0]),
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.s_axis_payload_tkeep (r2c_pyld[inst_i].slave.tkeep[INST_PARAMS[inst_i].nipc-1:0]),
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.s_axis_payload_tlast (r2c_pyld[inst_i].slave.tlast),
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.s_axis_payload_tvalid(r2c_pyld[inst_i].slave.tvalid),
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.s_axis_payload_tready(r2c_pyld[inst_i].slave.tready),
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.s_axis_context_tdata (r2c_ctxt[inst_i].slave.tdata),
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.s_axis_context_tuser (r2c_ctxt[inst_i].slave.tuser),
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.s_axis_context_tlast (r2c_ctxt[inst_i].slave.tlast),
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.s_axis_context_tvalid(r2c_ctxt[inst_i].slave.tvalid),
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.s_axis_context_tready(r2c_ctxt[inst_i].slave.tready),
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.framer_errors (r2c_framer_errors[inst_i]),
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.flush_en (r2c_flush_en[inst_i]),
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.flush_timeout (r2c_flush_timeout[inst_i]),
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.flush_active (r2c_flush_active[inst_i]),
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.flush_done (r2c_flush_done[inst_i])
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);
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// Instantiate Chdr to PyldCtxt DUT
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chdr_to_axis_pyld_ctxt #(
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.CHDR_W (CHDR_W),
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.ITEM_W (INST_PARAMS[inst_i].item_w),
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.NIPC (INST_PARAMS[inst_i].nipc),
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.SYNC_CLKS (INST_PARAMS[inst_i].clk_period == CHDR_CLK_PERIOD),
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.CONTEXT_FIFO_SIZE (INST_PARAMS[inst_i].ctxt_fifo),
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.PAYLOAD_FIFO_SIZE (INST_PARAMS[inst_i].pyld_fifo),
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.CONTEXT_PREFETCH_EN (INST_PARAMS[inst_i].prefetch)
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) c2r_dut (
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.axis_chdr_clk (rfnoc_chdr_clk),
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.axis_chdr_rst (rfnoc_chdr_rst),
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.axis_data_clk (rfnoc_data_clk[inst_i]),
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.axis_data_rst (rfnoc_data_rst[inst_i]),
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.s_axis_chdr_tdata (chdr_tdata[inst_i]),
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.s_axis_chdr_tlast (chdr_tlast[inst_i]),
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.s_axis_chdr_tvalid (chdr_tvalid[inst_i]),
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.s_axis_chdr_tready (chdr_tready[inst_i]),
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.m_axis_payload_tdata (c2r_pyld[inst_i].master.tdata[(INST_PARAMS[inst_i].item_w*INST_PARAMS[inst_i].nipc)-1:0]),
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.m_axis_payload_tkeep (c2r_pyld[inst_i].master.tkeep[INST_PARAMS[inst_i].nipc-1:0]),
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.m_axis_payload_tlast (c2r_pyld[inst_i].master.tlast),
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.m_axis_payload_tvalid(c2r_pyld[inst_i].master.tvalid),
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.m_axis_payload_tready(c2r_pyld[inst_i].master.tready),
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.m_axis_context_tdata (c2r_ctxt[inst_i].master.tdata),
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.m_axis_context_tuser (c2r_ctxt[inst_i].master.tuser),
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.m_axis_context_tlast (c2r_ctxt[inst_i].master.tlast),
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.m_axis_context_tvalid(c2r_ctxt[inst_i].master.tvalid),
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.m_axis_context_tready(c2r_ctxt[inst_i].master.tready),
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.flush_en (c2r_flush_en[inst_i]),
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.flush_timeout (c2r_flush_timeout[inst_i]),
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.flush_active (c2r_flush_active[inst_i]),
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.flush_done (c2r_flush_done[inst_i])
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);
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// Assert Reset and start BFMs
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initial begin
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dclk_gen.reset();
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r2c_flush_en[inst_i] = 0;
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c2r_flush_en[inst_i] = 0;
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pyld_bfm[inst_i] = new(r2c_pyld[inst_i], c2r_pyld[inst_i]);
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pyld_bfm[inst_i].run();
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ctxt_bfm[inst_i] = new(r2c_ctxt[inst_i], c2r_ctxt[inst_i]);
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ctxt_bfm[inst_i].run();
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end
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end endgenerate
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function automatic bit pyld_pkts_equal(
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ref AxiStreamPacket #(MAX_PYLD_W) exp,
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ref AxiStreamPacket #(MAX_PYLD_W) act,
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input int item_w,
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input int nipc
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);
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if (exp.data.size() != act.data.size()) return 0;
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if (exp.keep.size() != act.keep.size()) return 0;
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for (int i = 0; i < exp.data.size(); i++) begin
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// Convert to bit
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automatic bit [MAX_PYLD_W-1:0] mask = '0;
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automatic bit [MAX_PYLD_W-1:0] data_exp = exp.data[i];
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automatic bit [MAX_PYLD_W-1:0] data_act = act.data[i];
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for (int r = 0; r < nipc; r++) begin
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if (exp.keep[i][r] === 1'b1) begin
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automatic bit [MAX_PYLD_W-1:0] samp_mask = ((1<<item_w)-1);
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mask |= (samp_mask << (r*item_w));
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end
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end
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if (exp.keep[i] !== act.keep[i]) return 0;
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if ((data_exp&mask) !== (data_act&mask)) return 0;
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end
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return 1;
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endfunction
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task automatic send_recv_data_packets(
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input int inst,
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input inst_params_t params, //We pass this separately to work around Vivado bug
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input int num_pkts,
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input int mst_stall_prob,
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input int slv_stall_prob,
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input bit flushing = 0
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);
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int nipc = params.nipc;
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int item_w = params.item_w;
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bit prefetch = params.prefetch;
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AxiStreamPacket #(MAX_PYLD_W) pyld_pkt_arr[$] = {};
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AxiStreamPacket #(CHDR_W, 4) ctxt_pkt_arr[$] = {};
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// Set stall probabilities
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ctxt_bfm[inst].set_master_stall_prob(mst_stall_prob);
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ctxt_bfm[inst].set_slave_stall_prob(slv_stall_prob);
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pyld_bfm[inst].set_master_stall_prob(mst_stall_prob);
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pyld_bfm[inst].set_slave_stall_prob(slv_stall_prob);
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// Generate a stream of data packets
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for (int p = 0; p < num_pkts; p++) begin
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int len_lines = $urandom_range((MTU_BITS/(item_w*nipc))-10, 1);
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int keep_int = $urandom_range(nipc, 1);
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pyld_pkt_arr[p] = new();
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||||
for (int i = 0; i < len_lines; i++) begin
|
||||
logic [MAX_PYLD_W-1:0] rand_samp;
|
||||
logic [(MAX_PYLD_W/8)-1:0] keep_val = 'x;
|
||||
for (int r = 0; r < (((nipc*item_w)+31)/32); r++)
|
||||
rand_samp[r*32 +: 32] = $urandom();
|
||||
pyld_pkt_arr[p].data.push_back(rand_samp);
|
||||
pyld_pkt_arr[p].user.push_back('x);
|
||||
for (int r = 0; r < nipc; r++) begin
|
||||
if (i == len_lines-1)
|
||||
keep_val[r] = (r < keep_int) ? 1'b1 : 1'b0;
|
||||
else
|
||||
keep_val[r] = 1'b1;
|
||||
end
|
||||
pyld_pkt_arr[p].keep.push_back(keep_val);
|
||||
end
|
||||
end
|
||||
|
||||
// Generate context packet for each data packet
|
||||
foreach (pyld_pkt_arr[p]) begin
|
||||
automatic chdr_header_t chdr_hdr;
|
||||
automatic bit has_time = $urandom_range(1);
|
||||
automatic int num_mdata = $urandom_range(5);
|
||||
automatic int num_pyld_lines = pyld_pkt_arr[p].data.size();
|
||||
automatic int invalid_samps = 0;
|
||||
automatic int length;
|
||||
for (int r = 0; r < nipc; r++)
|
||||
if (pyld_pkt_arr[p].keep[num_pyld_lines-1][r] === 1'b0)
|
||||
invalid_samps++;
|
||||
length =
|
||||
(CHDR_W/8) + // header
|
||||
((has_time && (CHDR_W == 64)) ? (CHDR_W/8) : 0) + // timestamp
|
||||
(num_mdata * (CHDR_W/8)) + // metadata
|
||||
(num_pyld_lines * nipc * (item_w/8)) + // payload
|
||||
(-invalid_samps * (item_w/8)); // payload (back out empty slots)
|
||||
|
||||
chdr_hdr = '{
|
||||
vc : $urandom_range(63),
|
||||
eob : $urandom_range(1),
|
||||
eov : $urandom_range(1),
|
||||
pkt_type : has_time ? CHDR_DATA_WITH_TS : CHDR_DATA_NO_TS,
|
||||
num_mdata : num_mdata,
|
||||
seq_num : p,
|
||||
length : length,
|
||||
dst_epid : $urandom()
|
||||
};
|
||||
|
||||
ctxt_pkt_arr[p] = new();
|
||||
ctxt_pkt_arr[p].data.push_back(chdr_hdr);
|
||||
ctxt_pkt_arr[p].user.push_back((has_time && (CHDR_W > 64)) ? CONTEXT_FIELD_HDR_TS : CONTEXT_FIELD_HDR);
|
||||
ctxt_pkt_arr[p].keep.push_back('x);
|
||||
if (has_time && (CHDR_W == 64)) begin
|
||||
ctxt_pkt_arr[p].data.push_back(~p);
|
||||
ctxt_pkt_arr[p].user.push_back(CONTEXT_FIELD_TS);
|
||||
ctxt_pkt_arr[p].keep.push_back('x);
|
||||
end
|
||||
for (int i = 0; i < num_mdata; i++) begin
|
||||
ctxt_pkt_arr[p].data.push_back(i);
|
||||
ctxt_pkt_arr[p].user.push_back(CONTEXT_FIELD_MDATA);
|
||||
ctxt_pkt_arr[p].keep.push_back('x);
|
||||
end
|
||||
end
|
||||
|
||||
// Spin up 4 threads: {RX, TX} x {Context, Payload}
|
||||
fork
|
||||
begin: tx_context
|
||||
timeout_t timeout;
|
||||
for (int p = 0; p < num_pkts; p++) begin
|
||||
test.start_timeout(timeout, 50us, "Waiting to send TX context pkt");
|
||||
ctxt_bfm[inst].put(ctxt_pkt_arr[p].copy());
|
||||
test.end_timeout(timeout);
|
||||
if (VERBOSE) $display("[INST%0d:TxContext:%0d]\n%s", inst, p, ctxt_pkt_arr[p].sprint());
|
||||
end
|
||||
end
|
||||
begin: tx_payload
|
||||
timeout_t timeout;
|
||||
for (int p = 0; p < num_pkts; p++) begin
|
||||
test.start_timeout(timeout, 50us, "Waiting to send TX payload pkt");
|
||||
pyld_bfm[inst].put(pyld_pkt_arr[p].copy());
|
||||
test.end_timeout(timeout);
|
||||
if (VERBOSE) $display("[INST%0d:TxPayload:%0d]\n%s", inst, p, pyld_pkt_arr[p].sprint());
|
||||
end
|
||||
end
|
||||
begin: rx_context
|
||||
if (!flushing) begin
|
||||
timeout_t timeout;
|
||||
automatic AxiStreamPacket #(CHDR_W, 4) rx_ctxt_pkt;
|
||||
for (int p = 0; p < num_pkts; p++) begin
|
||||
test.start_timeout(timeout, 50us, "Waiting to recv RX context pkt");
|
||||
ctxt_bfm[inst].get(rx_ctxt_pkt);
|
||||
test.end_timeout(timeout);
|
||||
if (VERBOSE) $display("[INST%0d:RxContext:%0d]\n%s", inst, p, rx_ctxt_pkt.sprint());
|
||||
if (VERBOSE) $display("[INST%0d:ExpContext:%0d]\n%s", inst, p, ctxt_pkt_arr[p].sprint());
|
||||
`ASSERT_ERROR(ctxt_pkt_arr[p].equal(rx_ctxt_pkt), "RX context packet did not match TX");
|
||||
end
|
||||
end
|
||||
end
|
||||
begin: rx_payload
|
||||
if (!flushing) begin
|
||||
timeout_t timeout;
|
||||
automatic AxiStreamPacket #(MAX_PYLD_W) rx_pyld_pkt;
|
||||
for (int p = 0; p < num_pkts; p++) begin
|
||||
test.start_timeout(timeout, 50us, "Waiting to recv RX payload pkt");
|
||||
pyld_bfm[inst].get(rx_pyld_pkt);
|
||||
test.end_timeout(timeout);
|
||||
if (VERBOSE) $display("[INST%0d:RxPayload:%0d]\n%s", inst, p, rx_pyld_pkt.sprint());
|
||||
if (VERBOSE) $display("[INST%0d:ExpPayload:%0d]\n%s", inst, p, pyld_pkt_arr[p].sprint());
|
||||
`ASSERT_ERROR(pyld_pkts_equal(pyld_pkt_arr[p], rx_pyld_pkt, item_w, nipc), "RX payload packet did not match TX");
|
||||
end
|
||||
end
|
||||
end
|
||||
join
|
||||
endtask
|
||||
|
||||
|
||||
// ----------------------------------------
|
||||
// Test Process
|
||||
// ----------------------------------------
|
||||
initial begin
|
||||
|
||||
// Shared Variables
|
||||
// ----------------------------------------
|
||||
timeout_t timeout;
|
||||
string tc_label;
|
||||
|
||||
// Initialize
|
||||
// ----------------------------------------
|
||||
test.start_tb("axis_pyld_ctxt_converter_tb");
|
||||
|
||||
// Reset
|
||||
// ----------------------------------------
|
||||
chdr_clk_gen_i.reset();
|
||||
|
||||
test.start_test("Wait for reset");
|
||||
test.start_timeout(timeout, 1us, "Waiting for reset");
|
||||
while (rfnoc_chdr_rst) @(posedge rfnoc_chdr_clk);
|
||||
while (|rfnoc_data_rst) @(posedge rfnoc_chdr_clk);
|
||||
repeat (100) @(posedge rfnoc_chdr_clk);
|
||||
test.end_timeout(timeout);
|
||||
`ASSERT_ERROR(!rfnoc_chdr_rst && !(|rfnoc_data_rst), "Reset did not deassert");
|
||||
test.end_test();
|
||||
|
||||
for (int inst_num = START_INST; inst_num <= STOP_INST; inst_num++) begin
|
||||
$display("-----------------------------------------------------------------------------------------------");
|
||||
$display("Testing INST%0d:%p", inst_num, INST_PARAMS[inst_num]);
|
||||
$display("-----------------------------------------------------------------------------------------------");
|
||||
|
||||
// Stream Random Data
|
||||
// ----------------------------------------
|
||||
for (int cfg = 0; cfg < 4; cfg++) begin
|
||||
automatic integer mst_cfg = cfg[0];
|
||||
automatic integer slv_cfg = cfg[1];
|
||||
$sformat(tc_label, "INST%0d: Stream Random Data (%s Mst, %s Slv)",
|
||||
inst_num,(mst_cfg?"Slow":"Fast"), (slv_cfg?"Slow":"Fast"));
|
||||
test.start_test(tc_label);
|
||||
send_recv_data_packets(inst_num, INST_PARAMS[inst_num], NUM_PKTS_PER_TEST,
|
||||
mst_cfg ? SLOW_STALL_PROB : FAST_STALL_PROB,
|
||||
slv_cfg ? SLOW_STALL_PROB : FAST_STALL_PROB
|
||||
);
|
||||
`ASSERT_ERROR(r2c_framer_errors[inst_num] === '0, "Encountered framer errors");
|
||||
test.end_test();
|
||||
end
|
||||
|
||||
// Flush
|
||||
// ----------------------------------------
|
||||
$sformat(tc_label, "INST%0d: Flush PyldCtxt => CHDR (Idle)", inst_num);
|
||||
test.start_test(tc_label);
|
||||
r2c_flush_timeout[inst_num] = $urandom_range(400, 200);
|
||||
r2c_flush_en[inst_num] = 1'b1;
|
||||
repeat (100) @(posedge rfnoc_chdr_clk);
|
||||
`ASSERT_ERROR(r2c_flush_active[inst_num] === 1, "Flushing did not begin on time");
|
||||
`ASSERT_ERROR(r2c_flush_done[inst_num] === 0, "Flushing ended prematurely");
|
||||
repeat (r2c_flush_timeout[inst_num] + 1) @(posedge rfnoc_chdr_clk);
|
||||
`ASSERT_ERROR(r2c_flush_done[inst_num] === 1, "Flushing did not end on time");
|
||||
r2c_flush_en[inst_num] = 1'b0;
|
||||
@(posedge rfnoc_chdr_clk);
|
||||
test.end_test();
|
||||
|
||||
$sformat(tc_label, "INST%0d: Flush CHDR => PyldCtxt (Idle)", inst_num);
|
||||
test.start_test(tc_label);
|
||||
c2r_flush_timeout[inst_num] = $urandom_range(400, 200);
|
||||
c2r_flush_en[inst_num] = 1'b1;
|
||||
repeat (100) @(posedge rfnoc_data_clk[inst_num]);
|
||||
`ASSERT_ERROR(c2r_flush_active[inst_num] === 1, "Flushing did not begin on time");
|
||||
`ASSERT_ERROR(c2r_flush_done[inst_num] === 0, "Flushing ended prematurely");
|
||||
repeat (c2r_flush_timeout[inst_num] + 1) @(posedge rfnoc_data_clk[inst_num]);
|
||||
`ASSERT_ERROR(c2r_flush_done[inst_num] === 1, "Flushing did not end on time");
|
||||
c2r_flush_en[inst_num] = 1'b0;
|
||||
@(posedge rfnoc_data_clk[inst_num]);
|
||||
test.end_test();
|
||||
|
||||
$sformat(tc_label, "INST%0d: Flush PyldCtxt => CHDR (Streaming)", inst_num);
|
||||
test.start_test(tc_label);
|
||||
r2c_flush_timeout[inst_num] = $urandom_range(400, 200);
|
||||
r2c_flush_en[inst_num] = 1'b1;
|
||||
repeat (100) @(posedge rfnoc_chdr_clk);
|
||||
`ASSERT_ERROR(r2c_flush_active[inst_num] === 1, "Flushing did not begin on time");
|
||||
`ASSERT_ERROR(r2c_flush_done[inst_num] === 0, "Flushing ended prematurely");
|
||||
send_recv_data_packets(inst_num, INST_PARAMS[inst_num], NUM_PKTS_PER_TEST/10,
|
||||
FAST_STALL_PROB, FAST_STALL_PROB, 1 /*flushing*/
|
||||
);
|
||||
repeat (NUM_PKTS_PER_TEST/10 * (1<<MTU) * 4) @(posedge rfnoc_chdr_clk);
|
||||
repeat (r2c_flush_timeout[inst_num] + 1) @(posedge rfnoc_chdr_clk);
|
||||
`ASSERT_ERROR(r2c_flush_done[inst_num] === 1, "Flushing did not end on time");
|
||||
r2c_flush_en[inst_num] = 1'b0;
|
||||
@(posedge rfnoc_chdr_clk);
|
||||
test.end_test();
|
||||
|
||||
$sformat(tc_label, "INST%0d: Stream Data After Flush", inst_num);
|
||||
test.start_test(tc_label);
|
||||
send_recv_data_packets(inst_num, INST_PARAMS[inst_num], NUM_PKTS_PER_TEST/10,
|
||||
FAST_STALL_PROB, FAST_STALL_PROB
|
||||
);
|
||||
`ASSERT_ERROR(r2c_framer_errors[inst_num] === '0, "Encountered framer errors");
|
||||
test.end_test();
|
||||
end
|
||||
|
||||
// Finish Up
|
||||
// ----------------------------------------
|
||||
// Display final statistics and results
|
||||
test.end_tb();
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,44 @@
|
||||
#
|
||||
# Copyright 2019 Ettus Research, A National Instruments Company
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
#-------------------------------------------------
|
||||
# Top-of-Makefile
|
||||
#-------------------------------------------------
|
||||
# Define BASE_DIR to point to the "top" dir
|
||||
BASE_DIR = $(abspath ../../../../top)
|
||||
# Include viv_sim_preamble after defining BASE_DIR
|
||||
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
|
||||
|
||||
#-------------------------------------------------
|
||||
# Design Specific
|
||||
#-------------------------------------------------
|
||||
# Include makefiles and sources for the DUT and its dependencies
|
||||
include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
|
||||
|
||||
include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
|
||||
include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
|
||||
|
||||
DESIGN_SRCS += $(abspath \
|
||||
$(RFNOC_CORE_SRCS) \
|
||||
$(RFNOC_XBAR_SRCS) \
|
||||
)
|
||||
|
||||
#-------------------------------------------------
|
||||
# Testbench Specific
|
||||
#-------------------------------------------------
|
||||
SIM_TOP = chdr_stream_endpoint_tb
|
||||
|
||||
SIM_SRCS = \
|
||||
$(abspath lossy_xport_model.v) \
|
||||
$(abspath chdr_stream_endpoint_tb.sv) \
|
||||
|
||||
#-------------------------------------------------
|
||||
# Bottom-of-Makefile
|
||||
#-------------------------------------------------
|
||||
# Include all simulator specific makefiles here
|
||||
# Each should define a unique target to simulate
|
||||
# e.g. xsim, vsim, etc and a common "clean" target
|
||||
include $(BASE_DIR)/../tools/make/viv_simulator.mak
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,66 @@
|
||||
//
|
||||
// Copyright 2019 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: lossy_xport_model
|
||||
//
|
||||
|
||||
module lossy_xport_model #(
|
||||
parameter CHDR_W = 256
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire [CHDR_W-1:0] s_axis_tdata,
|
||||
input wire s_axis_tlast,
|
||||
input wire s_axis_tvalid,
|
||||
output wire s_axis_tready,
|
||||
output wire [CHDR_W-1:0] m_axis_tdata,
|
||||
output wire m_axis_tlast,
|
||||
output wire m_axis_tvalid,
|
||||
input wire m_axis_tready,
|
||||
input wire [7:0] seqerr_prob,
|
||||
input wire [7:0] rterr_prob,
|
||||
input wire lossy
|
||||
);
|
||||
wire [CHDR_W-1:0] tmp_tdata;
|
||||
wire tmp_tlast;
|
||||
wire tmp_tvalid;
|
||||
wire tmp_tready;
|
||||
|
||||
reg pkt_header = 1'b1;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
pkt_header <= 1'b1;
|
||||
end else if (s_axis_tvalid && s_axis_tready) begin
|
||||
pkt_header <= s_axis_tlast;
|
||||
end
|
||||
end
|
||||
wire pkt_stb = (s_axis_tvalid && s_axis_tready && s_axis_tlast);
|
||||
|
||||
reg force_seq_err, force_route_err;
|
||||
always @(pkt_stb or seqerr_prob) begin
|
||||
force_seq_err = ($urandom_range(99) < seqerr_prob);
|
||||
end
|
||||
always @(pkt_stb or rterr_prob) begin
|
||||
force_route_err = ($urandom_range(99) < rterr_prob);
|
||||
end
|
||||
|
||||
wire [15:0] new_seq_num = s_axis_tdata[47:32] + 16'd1; //Increment SeqNum
|
||||
wire [15:0] new_dst_epid = ~s_axis_tdata[15:0]; //Invert DstEPID
|
||||
|
||||
assign tmp_tdata = !pkt_header ? s_axis_tdata : (
|
||||
force_seq_err ? {s_axis_tdata[CHDR_W-1:48], new_seq_num, s_axis_tdata[31:0]} : (
|
||||
force_route_err ? {s_axis_tdata[CHDR_W-1:16], new_dst_epid} : s_axis_tdata));
|
||||
assign tmp_tlast = s_axis_tlast;
|
||||
assign tmp_tvalid = s_axis_tvalid;
|
||||
assign s_axis_tready = lossy || tmp_tready;
|
||||
|
||||
axi_fifo #(.WIDTH(CHDR_W+1), .SIZE(1)) out_fifo (
|
||||
.clk(clk), .reset(rst), .clear(1'b0),
|
||||
.i_tdata({tmp_tlast, tmp_tdata}), .i_tvalid(tmp_tvalid), .i_tready(tmp_tready),
|
||||
.o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready),
|
||||
.space(), .occupied()
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,39 @@
|
||||
#
|
||||
# Copyright 2019 Ettus Research, A National Instruments Company
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
#-------------------------------------------------
|
||||
# Top-of-Makefile
|
||||
#-------------------------------------------------
|
||||
# Define BASE_DIR to point to the "top" dir
|
||||
BASE_DIR = $(abspath ../../../../top)
|
||||
# Include viv_sim_preamble after defining BASE_DIR
|
||||
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
|
||||
|
||||
#-------------------------------------------------
|
||||
# Design Specific
|
||||
#-------------------------------------------------
|
||||
# Include makefiles and sources for the DUT and its dependencies
|
||||
include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
|
||||
|
||||
DESIGN_SRCS += $(abspath \
|
||||
$(RFNOC_CORE_SRCS) \
|
||||
)
|
||||
|
||||
#-------------------------------------------------
|
||||
# Testbench Specific
|
||||
#-------------------------------------------------
|
||||
SIM_TOP = ctrlport_endpoint_tb
|
||||
|
||||
SIM_SRCS = \
|
||||
$(abspath ctrlport_endpoint_tb.sv) \
|
||||
|
||||
#-------------------------------------------------
|
||||
# Bottom-of-Makefile
|
||||
#-------------------------------------------------
|
||||
# Include all simulator specific makefiles here
|
||||
# Each should define a unique target to simulate
|
||||
# e.g. xsim, vsim, etc and a common "clean" target
|
||||
include $(BASE_DIR)/../tools/make/viv_simulator.mak
|
||||
@@ -0,0 +1,502 @@
|
||||
//
|
||||
// Copyright 2019 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: ctrlport_endpoint_tb
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
|
||||
module ctrlport_endpoint_tb;
|
||||
|
||||
// Include macros and time declarations for use with PkgTestExec
|
||||
`include "test_exec.svh"
|
||||
|
||||
import PkgTestExec::*;
|
||||
import PkgChdrUtils::*;
|
||||
import PkgAxisCtrlBfm::*;
|
||||
|
||||
// Parameters
|
||||
localparam [9:0] THIS_PORTID = 10'h17;
|
||||
localparam [15:0] THIS_EPID = 16'hDEAD;
|
||||
|
||||
localparam integer NUM_XACT_PER_TEST = 300;
|
||||
localparam integer FAST_STALL_PROB = 0;
|
||||
localparam integer SLOW_STALL_PROB = 50;
|
||||
localparam bit VERBOSE = 0;
|
||||
|
||||
// Clock and Reset Definition
|
||||
bit rfnoc_ctrl_clk, rfnoc_ctrl_rst;
|
||||
bit ctrlport_clk, ctrlport_rst;
|
||||
|
||||
sim_clock_gen #(6.0) rfnoc_ctrl_clk_gen (rfnoc_ctrl_clk, rfnoc_ctrl_rst); // 166.6 MHz
|
||||
sim_clock_gen #(20.0) ctrlport_clk_gen (ctrlport_clk, ctrlport_rst); // 50 MHz
|
||||
|
||||
// ----------------------------------------
|
||||
// Instantiate DUT
|
||||
// ----------------------------------------
|
||||
AxiStreamIf #(32) m_ctrl (rfnoc_ctrl_clk, rfnoc_ctrl_rst);
|
||||
AxiStreamIf #(32) s_ctrl (rfnoc_ctrl_clk, rfnoc_ctrl_rst);
|
||||
AxisCtrlBfm axis_ctrl_bfm;
|
||||
|
||||
wire [31:0] axis_mst_tdata, axis_slv_tdata , axis_req_tdata , axis_resp_tdata ;
|
||||
wire axis_mst_tlast, axis_slv_tlast , axis_req_tlast , axis_resp_tlast ;
|
||||
wire axis_mst_tvalid, axis_slv_tvalid, axis_req_tvalid, axis_resp_tvalid;
|
||||
wire axis_mst_tready, axis_slv_tready, axis_req_tready, axis_resp_tready;
|
||||
|
||||
wire cp_slv_req_wr;
|
||||
wire cp_slv_req_rd;
|
||||
wire [19:0] cp_slv_req_addr;
|
||||
wire [31:0] cp_slv_req_data;
|
||||
wire [3:0] cp_slv_req_byte_en;
|
||||
wire cp_slv_req_has_time;
|
||||
wire [63:0] cp_slv_req_time;
|
||||
reg cp_slv_resp_ack;
|
||||
reg [1:0] cp_slv_resp_status;
|
||||
reg [31:0] cp_slv_resp_data;
|
||||
|
||||
logic cp_mst_req_wr;
|
||||
logic cp_mst_req_rd;
|
||||
logic [19:0] cp_mst_req_addr;
|
||||
logic [9:0] cp_mst_req_portid;
|
||||
logic [15:0] cp_mst_req_rem_epid;
|
||||
logic [9:0] cp_mst_req_rem_portid;
|
||||
logic [31:0] cp_mst_req_data;
|
||||
logic [3:0] cp_mst_req_byte_en;
|
||||
logic cp_mst_req_has_time;
|
||||
logic [63:0] cp_mst_req_time;
|
||||
wire cp_mst_resp_ack;
|
||||
wire [1:0] cp_mst_resp_status;
|
||||
wire [31:0] cp_mst_resp_data;
|
||||
|
||||
ctrlport_endpoint #(
|
||||
.THIS_PORTID (THIS_PORTID),
|
||||
.SYNC_CLKS (0),
|
||||
.AXIS_CTRL_MST_EN (1),
|
||||
.AXIS_CTRL_SLV_EN (1),
|
||||
.SLAVE_FIFO_SIZE (5)
|
||||
) dut (
|
||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
|
||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
|
||||
.ctrlport_clk (ctrlport_clk ),
|
||||
.ctrlport_rst (ctrlport_rst ),
|
||||
.s_rfnoc_ctrl_tdata (axis_mst_tdata ),
|
||||
.s_rfnoc_ctrl_tlast (axis_mst_tlast ),
|
||||
.s_rfnoc_ctrl_tvalid (axis_mst_tvalid ),
|
||||
.s_rfnoc_ctrl_tready (axis_mst_tready ),
|
||||
.m_rfnoc_ctrl_tdata (axis_slv_tdata ),
|
||||
.m_rfnoc_ctrl_tlast (axis_slv_tlast ),
|
||||
.m_rfnoc_ctrl_tvalid (axis_slv_tvalid ),
|
||||
.m_rfnoc_ctrl_tready (axis_slv_tready ),
|
||||
.m_ctrlport_req_wr (cp_slv_req_wr ),
|
||||
.m_ctrlport_req_rd (cp_slv_req_rd ),
|
||||
.m_ctrlport_req_addr (cp_slv_req_addr ),
|
||||
.m_ctrlport_req_data (cp_slv_req_data ),
|
||||
.m_ctrlport_req_byte_en (cp_slv_req_byte_en ),
|
||||
.m_ctrlport_req_has_time (cp_slv_req_has_time ),
|
||||
.m_ctrlport_req_time (cp_slv_req_time ),
|
||||
.m_ctrlport_resp_ack (cp_slv_resp_ack ),
|
||||
.m_ctrlport_resp_status (cp_slv_resp_status ),
|
||||
.m_ctrlport_resp_data (cp_slv_resp_data ),
|
||||
.s_ctrlport_req_wr (cp_mst_req_wr ),
|
||||
.s_ctrlport_req_rd (cp_mst_req_rd ),
|
||||
.s_ctrlport_req_addr (cp_mst_req_addr ),
|
||||
.s_ctrlport_req_portid (cp_mst_req_portid ),
|
||||
.s_ctrlport_req_rem_epid (cp_mst_req_rem_epid ),
|
||||
.s_ctrlport_req_rem_portid(cp_mst_req_rem_portid),
|
||||
.s_ctrlport_req_data (cp_mst_req_data ),
|
||||
.s_ctrlport_req_byte_en (cp_mst_req_byte_en ),
|
||||
.s_ctrlport_req_has_time (cp_mst_req_has_time ),
|
||||
.s_ctrlport_req_time (cp_mst_req_time ),
|
||||
.s_ctrlport_resp_ack (cp_mst_resp_ack ),
|
||||
.s_ctrlport_resp_status (cp_mst_resp_status ),
|
||||
.s_ctrlport_resp_data (cp_mst_resp_data )
|
||||
);
|
||||
|
||||
// ----------------------------------------
|
||||
// Test Helpers
|
||||
// ----------------------------------------
|
||||
|
||||
// Add a MUX and DEMUX on the ctrlport logic to loop responses
|
||||
// back into the endpoint and to allow external access from the
|
||||
// master and slave BFM.
|
||||
axi_mux #(
|
||||
.WIDTH(32), .SIZE(2), .PRIO(0), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(0)
|
||||
) mux_i (
|
||||
.clk(rfnoc_ctrl_clk), .reset(rfnoc_ctrl_rst), .clear(1'b0),
|
||||
.i_tdata ({m_ctrl.slave.tdata , axis_resp_tdata }),
|
||||
.i_tlast ({m_ctrl.slave.tlast , axis_resp_tlast }),
|
||||
.i_tvalid({m_ctrl.slave.tvalid, axis_resp_tvalid}),
|
||||
.i_tready({m_ctrl.slave.tready, axis_resp_tready}),
|
||||
.o_tdata (axis_mst_tdata ),
|
||||
.o_tlast (axis_mst_tlast ),
|
||||
.o_tvalid(axis_mst_tvalid),
|
||||
.o_tready(axis_mst_tready)
|
||||
);
|
||||
|
||||
wire [31:0] in_hdr;
|
||||
axi_demux #(
|
||||
.WIDTH(32), .SIZE(2), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(0)
|
||||
) demux_i (
|
||||
.clk(rfnoc_ctrl_clk), .reset(rfnoc_ctrl_rst), .clear(1'b0),
|
||||
.header(in_hdr), .dest(in_hdr[31]),
|
||||
.i_tdata (axis_slv_tdata ),
|
||||
.i_tlast (axis_slv_tlast ),
|
||||
.i_tvalid(axis_slv_tvalid),
|
||||
.i_tready(axis_slv_tready),
|
||||
.o_tdata ({s_ctrl.master.tdata , axis_req_tdata }),
|
||||
.o_tlast ({s_ctrl.master.tlast , axis_req_tlast }),
|
||||
.o_tvalid({s_ctrl.master.tvalid, axis_req_tvalid}),
|
||||
.o_tready({s_ctrl.master.tready, axis_req_tready})
|
||||
);
|
||||
|
||||
// --------------------------
|
||||
// [Dummy Control Port Slave]
|
||||
// Slave Model:
|
||||
// - Respond in 1 clock cycle
|
||||
// - Status = Upper 2 bits of the address
|
||||
// - Response Data = 0xFEED and Negated bottom 16 bits of addr
|
||||
always @(posedge ctrlport_clk) begin
|
||||
if (ctrlport_rst) begin
|
||||
cp_slv_resp_ack <= 1'b0;
|
||||
end else begin
|
||||
cp_slv_resp_ack <= cp_slv_req_wr | cp_slv_req_rd;
|
||||
cp_slv_resp_status <= cp_slv_req_addr[19:18];
|
||||
cp_slv_resp_data <= {16'hFEED, ~cp_slv_req_addr[15:0]};
|
||||
end
|
||||
end
|
||||
// --------------------------
|
||||
|
||||
// ----------------------------
|
||||
// [Dummy AXIS-Ctrl Port Slave]
|
||||
// Slave Model:
|
||||
// - Response = Request but with the ACK bit set
|
||||
// - Status = Upper 2 bits of the address
|
||||
// - Response Data = Request Data
|
||||
reg [4:0] line_num = 5'd0;
|
||||
reg pkt_has_time = 1'b0;
|
||||
wire pkt_hdr_line = (line_num == 5'd0);
|
||||
wire pkt_op_line = pkt_has_time ? (line_num == 5'd4) : (line_num == 5'd2);
|
||||
always @(posedge rfnoc_ctrl_clk) begin
|
||||
if (rfnoc_ctrl_rst) begin
|
||||
line_num <= 5'd0;
|
||||
pkt_has_time <= 1'b0;
|
||||
end else if (axis_req_tvalid & axis_resp_tready) begin
|
||||
if (pkt_hdr_line)
|
||||
pkt_has_time <= axis_req_tdata[30];
|
||||
line_num <= axis_req_tlast ? 5'd0 : (line_num + 1);
|
||||
end
|
||||
end
|
||||
assign axis_resp_tdata =
|
||||
pkt_hdr_line ? {1'b1, axis_req_tdata[30:0]} : (
|
||||
pkt_op_line ? {axis_req_tdata[19:18], axis_req_tdata[29:0]} :
|
||||
axis_req_tdata);
|
||||
assign axis_resp_tlast = axis_req_tlast;
|
||||
assign axis_resp_tvalid = axis_req_tvalid;
|
||||
assign axis_req_tready = axis_resp_tready;
|
||||
// ----------------------------
|
||||
|
||||
// Task to send a ctrlport request and receive a response
|
||||
task ctrlport_transact(
|
||||
input wr,
|
||||
input rd,
|
||||
input [19:0] addr,
|
||||
input [9:0] portid,
|
||||
input [15:0] rem_epid,
|
||||
input [9:0] rem_portid,
|
||||
input [31:0] data,
|
||||
input [3:0] byte_en,
|
||||
input has_time,
|
||||
input [63:0] timestamp,
|
||||
output [1:0] resp_status,
|
||||
output [31:0] resp_data
|
||||
);
|
||||
if (rd | wr) begin
|
||||
cp_mst_req_wr <= wr;
|
||||
cp_mst_req_rd <= rd;
|
||||
cp_mst_req_addr <= addr;
|
||||
cp_mst_req_portid <= portid;
|
||||
cp_mst_req_rem_epid <= rem_epid;
|
||||
cp_mst_req_rem_portid <= rem_portid;
|
||||
cp_mst_req_data <= data;
|
||||
cp_mst_req_byte_en <= byte_en;
|
||||
cp_mst_req_has_time <= has_time;
|
||||
cp_mst_req_time <= timestamp;
|
||||
@(posedge ctrlport_clk);
|
||||
cp_mst_req_wr <= 0;
|
||||
cp_mst_req_rd <= 0;
|
||||
while (~cp_mst_resp_ack) @(posedge ctrlport_clk);
|
||||
resp_status = cp_mst_resp_status;
|
||||
resp_data = cp_mst_resp_data;
|
||||
|
||||
// Validate contents
|
||||
if (VERBOSE) begin
|
||||
$display("%s(addr=%0x, data=%0x, portid=%0x, has_time=%0b) = %0x (Status = %0d)",
|
||||
(rd&wr)?"WRRD":(rd?"RD":"WR"), addr, data, portid, has_time, resp_data, resp_status);
|
||||
end
|
||||
`ASSERT_ERROR(cp_mst_resp_status == addr[19:18],
|
||||
"Received Ctrlport response had the wrong status");
|
||||
`ASSERT_ERROR(cp_mst_resp_data == data,
|
||||
"Received Ctrlport response had the wrong data");
|
||||
end
|
||||
endtask
|
||||
|
||||
// Task to send a AxisCtrl request and receive a response
|
||||
logic [5:0] cached_seq_num = 0;
|
||||
task axis_ctrl_transact(
|
||||
input [3:0] opcode,
|
||||
input [19:0] addr,
|
||||
input [9:0] portid,
|
||||
input [15:0] rem_epid,
|
||||
input [9:0] rem_portid,
|
||||
input [31:0] data[$],
|
||||
input [3:0] byte_en,
|
||||
input has_time,
|
||||
input [63:0] timestamp,
|
||||
output [1:0] resp_status,
|
||||
output [31:0] resp_data
|
||||
);
|
||||
automatic AxisCtrlPacket tx_pkt, rx_pkt = null, exp_pkt = null;
|
||||
automatic axis_ctrl_header_t header;
|
||||
automatic ctrl_op_word_t op_word;
|
||||
automatic ctrl_status_t exp_status;
|
||||
automatic ctrl_word_t exp_data0;
|
||||
|
||||
// Opcode specific logic
|
||||
case (ctrl_opcode_t'(opcode))
|
||||
CTRL_OP_SLEEP: begin
|
||||
// data[0] = cycles of sleep so limit its value
|
||||
if (data.size() > 0) data[0][31:5] = 0;
|
||||
exp_status = CTRL_STS_OKAY;
|
||||
exp_data0 = data[0];
|
||||
end
|
||||
CTRL_OP_WRITE_READ: begin
|
||||
exp_status = ctrl_status_t'(addr[19:18]);
|
||||
exp_data0 = {16'hFEED, ~addr[15:0]};
|
||||
end
|
||||
CTRL_OP_WRITE: begin
|
||||
exp_status = ctrl_status_t'(addr[19:18]);
|
||||
exp_data0 = data[0];
|
||||
end
|
||||
CTRL_OP_READ: begin
|
||||
exp_status = ctrl_status_t'(addr[19:18]);
|
||||
exp_data0 = {16'hFEED, ~addr[15:0]};
|
||||
end
|
||||
default: begin
|
||||
exp_status = CTRL_STS_CMDERR;
|
||||
exp_data0 = data[0];
|
||||
end
|
||||
endcase
|
||||
|
||||
// Build TX packet
|
||||
tx_pkt = new();
|
||||
header = '{
|
||||
default : '0,
|
||||
rem_dst_port : rem_portid,
|
||||
rem_dst_epid : rem_epid,
|
||||
is_ack : 1'b0,
|
||||
has_time : has_time,
|
||||
seq_num : cached_seq_num,
|
||||
num_data : data.size(),
|
||||
src_port : THIS_PORTID,
|
||||
dst_port : portid
|
||||
};
|
||||
op_word = '{
|
||||
default : '0,
|
||||
op_code : ctrl_opcode_t'(opcode),
|
||||
byte_enable : byte_en,
|
||||
address : addr
|
||||
};
|
||||
tx_pkt.write_ctrl(header, op_word, data, timestamp);
|
||||
|
||||
// Build expected packet (NULL if data vector is empty)
|
||||
if (data.size() > 0) begin
|
||||
exp_pkt = tx_pkt.copy();
|
||||
exp_pkt.header.is_ack = 1'b1;
|
||||
exp_pkt.op_word.status = exp_status;
|
||||
exp_pkt.data[0] = exp_data0;
|
||||
end
|
||||
|
||||
if (VERBOSE) $display("*******************");
|
||||
fork
|
||||
// Send the packet
|
||||
begin
|
||||
axis_ctrl_bfm.put_ctrl(tx_pkt.copy());
|
||||
if (VERBOSE) begin $display("[TRANSMITTED]"); tx_pkt.print(); end
|
||||
end
|
||||
// Wait for response only if we are expecting one
|
||||
if (exp_pkt != null) begin
|
||||
axis_ctrl_bfm.get_ctrl(rx_pkt);
|
||||
if (VERBOSE) begin $display("[RECEIVED]"); rx_pkt.print(); end
|
||||
end
|
||||
join
|
||||
cached_seq_num = cached_seq_num + 1;
|
||||
|
||||
// Validate contents
|
||||
if (exp_pkt != null) begin
|
||||
if (VERBOSE) begin $display("[EXPECTED]"); exp_pkt.print(); end
|
||||
`ASSERT_ERROR(exp_pkt.equal(rx_pkt),
|
||||
"Received AXIS-Ctrl packet was incorrect");
|
||||
end
|
||||
endtask
|
||||
|
||||
// ----------------------------------------
|
||||
// Test Process
|
||||
// ----------------------------------------
|
||||
initial begin
|
||||
// Shared Variables
|
||||
// ----------------------------------------
|
||||
timeout_t timeout;
|
||||
string tc_label;
|
||||
logic [31:0] data_vtr[$];
|
||||
logic [1:0] resp_status;
|
||||
logic [31:0] resp_data;
|
||||
|
||||
// Initialize
|
||||
// ----------------------------------------
|
||||
test.start_tb("ctrlport_endpoint_tb");
|
||||
|
||||
// Start the BFMs
|
||||
axis_ctrl_bfm = new(m_ctrl, s_ctrl);
|
||||
axis_ctrl_bfm.run();
|
||||
|
||||
// Reset
|
||||
// ----------------------------------------
|
||||
rfnoc_ctrl_clk_gen.reset();
|
||||
ctrlport_clk_gen.reset();
|
||||
|
||||
test.start_test("Wait for reset");
|
||||
test.start_timeout(timeout, 1us, "Waiting for reset");
|
||||
while (rfnoc_ctrl_rst) @(posedge rfnoc_ctrl_clk);
|
||||
while (ctrlport_rst) @(posedge ctrlport_clk);
|
||||
test.end_timeout(timeout);
|
||||
`ASSERT_ERROR(!ctrlport_rst && !rfnoc_ctrl_rst, "Reset did not deassert");
|
||||
test.end_test();
|
||||
|
||||
// AXIS-Ctrl Slave Test
|
||||
// ----------------------------------------
|
||||
// Send AXIS-Ctrl packets to the DUT and expect AXIS-Ctrl
|
||||
// responses. There is a ctrlport slave implemented above
|
||||
for (int cfg = 0; cfg < 4; cfg++) begin
|
||||
automatic logic mst_cfg = cfg[0];
|
||||
automatic logic slv_cfg = cfg[1];
|
||||
$sformat(tc_label,
|
||||
"AXIS-Ctrl Slave (%s Master, %s Slave)",
|
||||
(mst_cfg?"Slow":"Fast"), (slv_cfg?"Slow":"Fast"));
|
||||
test.start_test(tc_label);
|
||||
begin
|
||||
// Set bus stall probabilities based on configuration
|
||||
axis_ctrl_bfm.set_master_stall_prob(mst_cfg?SLOW_STALL_PROB:FAST_STALL_PROB);
|
||||
axis_ctrl_bfm.set_slave_stall_prob(slv_cfg?SLOW_STALL_PROB:FAST_STALL_PROB);
|
||||
// Test multiple transactions
|
||||
for (int n = 0; n < NUM_XACT_PER_TEST; n++) begin
|
||||
// Generate random data for the payload
|
||||
// It is illegal in the protocol to have a zero
|
||||
// data length but we test it here to ensure no lockups
|
||||
data_vtr.delete();
|
||||
for (int i = 0; i < $urandom_range(15); i++)
|
||||
data_vtr[i] = $urandom();
|
||||
// Perform transaction
|
||||
test.start_timeout(timeout, 10us, "Waiting for AXIS-Ctrl transaction");
|
||||
axis_ctrl_transact(
|
||||
$urandom_range(5), // opcode
|
||||
$urandom(), // addr
|
||||
THIS_PORTID, // portid
|
||||
$urandom(), $urandom(), // rem_epid, rem_portid
|
||||
data_vtr,
|
||||
$urandom_range(15), // byte_en
|
||||
$urandom_range(1), // has_time
|
||||
{$urandom(), $urandom()}, // timestamp
|
||||
resp_status,
|
||||
resp_data
|
||||
);
|
||||
test.end_timeout(timeout);
|
||||
end
|
||||
end
|
||||
test.end_test();
|
||||
end
|
||||
|
||||
// AXIS-Ctrl Master Test
|
||||
// ----------------------------------------
|
||||
// Send Ctrlport packets to the DUT and expect Ctrlport
|
||||
// responses. There is a AXIS-Ctrl slave implemented above
|
||||
test.start_test("AXIS-Ctrl Master");
|
||||
begin
|
||||
// Test multiple transactions
|
||||
for (int n = 0; n < NUM_XACT_PER_TEST * 4; n++) begin
|
||||
test.start_timeout(timeout, 10us, "Waiting for Ctrlport transaction");
|
||||
ctrlport_transact(
|
||||
$urandom_range(1), $urandom_range(1), // wr and rd
|
||||
$urandom(), // addr
|
||||
THIS_PORTID, // portid
|
||||
$urandom(), $urandom(), // rem_epid, rem_portid
|
||||
$urandom(), // data
|
||||
$urandom_range(15), // byte_en
|
||||
$urandom_range(1), // has_time
|
||||
{$urandom(), $urandom()}, // timestamp
|
||||
resp_status,
|
||||
resp_data
|
||||
);
|
||||
|
||||
test.end_timeout(timeout);
|
||||
end
|
||||
end
|
||||
test.end_test();
|
||||
|
||||
// AXIS-Ctrl Master+Slave Test
|
||||
// ----------------------------------------
|
||||
test.start_test("AXIS-Ctrl Master + Slave Simultaneously");
|
||||
begin
|
||||
axis_ctrl_bfm.set_master_stall_prob(FAST_STALL_PROB);
|
||||
axis_ctrl_bfm.set_slave_stall_prob(FAST_STALL_PROB);
|
||||
test.start_timeout(timeout, 10us * NUM_XACT_PER_TEST, "Waiting for test case");
|
||||
fork
|
||||
for (int n = 0; n < NUM_XACT_PER_TEST; n++) begin
|
||||
// Generate random data for the payload
|
||||
// It is illegal in the protocol to have a zero
|
||||
// data length but we test it here to ensure no lockups
|
||||
data_vtr.delete();
|
||||
for (int i = 0; i < $urandom_range(15); i++)
|
||||
data_vtr[i] = $urandom();
|
||||
// Perform transaction
|
||||
axis_ctrl_transact(
|
||||
$urandom_range(5), // opcode
|
||||
$urandom(), // addr
|
||||
THIS_PORTID, // portid
|
||||
$urandom(), $urandom(), // rem_epid, rem_portid
|
||||
data_vtr,
|
||||
$urandom_range(15), // byte_en
|
||||
$urandom_range(1), // has_time
|
||||
{$urandom(), $urandom()}, // timestamp
|
||||
resp_status,
|
||||
resp_data
|
||||
);
|
||||
end
|
||||
for (int n = 0; n < NUM_XACT_PER_TEST; n++) begin
|
||||
ctrlport_transact(
|
||||
$urandom_range(1), $urandom_range(1), // wr and rd
|
||||
$urandom(), // addr
|
||||
THIS_PORTID, // portid
|
||||
$urandom(), $urandom(), // rem_epid, rem_portid
|
||||
$urandom(), // data
|
||||
$urandom_range(15), // byte_en
|
||||
$urandom_range(1), // has_time
|
||||
{$urandom(), $urandom()}, // timestamp
|
||||
resp_status,
|
||||
resp_data
|
||||
);
|
||||
end
|
||||
join
|
||||
test.end_timeout(timeout);
|
||||
end
|
||||
test.end_test();
|
||||
|
||||
// Finish Up
|
||||
// ----------------------------------------
|
||||
// Display final statistics and results
|
||||
test.end_tb();
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user