Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,47 @@
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#
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# Copyright 2019 Ettus Research, A National Instruments Company
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
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include Makefile.srcs
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DESIGN_SRCS += $(abspath \
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$(RFNOC_CORE_SRCS) \
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$(RFNOC_UTIL_SRCS) \
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$(RFNOC_BLOCK_RADIO_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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SIM_TOP = rfnoc_block_radio_all_tb
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SIM_SRCS = \
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$(abspath sim_radio_gen.sv) \
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$(abspath rfnoc_block_radio_tb.sv) \
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$(abspath rfnoc_block_radio_all_tb.sv)
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# MODELSIM_USER_DO = $(abspath wave.do)
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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@@ -0,0 +1,20 @@
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#
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# Copyright 2018 Ettus Research, A National Instruments Company
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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##################################################
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# RFNoC Utility Sources
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##################################################
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RFNOC_BLOCK_RADIO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_radio/, \
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rfnoc_block_radio_regs.vh \
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radio_rx_core.v \
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radio_tx_core.v \
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radio_core.v \
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noc_shell_radio.v \
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rfnoc_block_radio.v \
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rx_frontend_gen3.v \
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tx_frontend_gen3.v \
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quarter_rate_downconverter.v \
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))
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@@ -0,0 +1,290 @@
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//
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// Copyright 2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: noc_shell_radio
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//
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// Description: A NoC Shell for RFNoC. This should eventually be replaced
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// by an auto-generated NoC Shell.
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//
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module noc_shell_radio #(
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parameter [31:0] NOC_ID = 32'h0,
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parameter [ 9:0] THIS_PORTID = 10'd0,
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parameter CHDR_W = 64,
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parameter [ 0:0] CTRLPORT_SLV_EN = 1,
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parameter [ 0:0] CTRLPORT_MST_EN = 1,
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parameter [ 5:0] CTRL_FIFO_SIZE = 9,
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parameter [ 5:0] NUM_DATA_I = 1,
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parameter [ 5:0] NUM_DATA_O = 1,
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parameter ITEM_W = 32,
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parameter NIPC = 2,
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parameter PYLD_FIFO_SIZE = 10,
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parameter MTU = 10
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)(
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//---------------------------------------------------------------------------
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// Framework Interface
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//---------------------------------------------------------------------------
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// RFNoC Framework Clocks and Resets
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input wire rfnoc_chdr_clk,
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output wire rfnoc_chdr_rst,
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input wire rfnoc_ctrl_clk,
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output wire rfnoc_ctrl_rst,
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// RFNoC Backend Interface
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input wire [ 511:0] rfnoc_core_config,
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output wire [ 511:0] rfnoc_core_status,
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// CHDR Input Ports (from framework)
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input wire [(CHDR_W*NUM_DATA_I)-1:0] s_rfnoc_chdr_tdata,
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input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tlast,
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input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tvalid,
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output wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tready,
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// CHDR Output Ports (to framework)
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output wire [(CHDR_W*NUM_DATA_O)-1:0] m_rfnoc_chdr_tdata,
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output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tlast,
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output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tvalid,
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input wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tready,
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// AXIS-Ctrl Input Port (from framework)
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input wire [ 31:0] s_rfnoc_ctrl_tdata,
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input wire s_rfnoc_ctrl_tlast,
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input wire s_rfnoc_ctrl_tvalid,
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output wire s_rfnoc_ctrl_tready,
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// AXIS-Ctrl Output Port (to framework)
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output wire [ 31:0] m_rfnoc_ctrl_tdata,
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output wire m_rfnoc_ctrl_tlast,
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output wire m_rfnoc_ctrl_tvalid,
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input wire m_rfnoc_ctrl_tready,
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//---------------------------------------------------------------------------
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// Client Control Port Interface
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//---------------------------------------------------------------------------
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// Clock
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// Master
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output wire m_ctrlport_req_wr,
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output wire m_ctrlport_req_rd,
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output wire [19:0] m_ctrlport_req_addr,
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output wire [31:0] m_ctrlport_req_data,
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output wire [ 3:0] m_ctrlport_req_byte_en,
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output wire m_ctrlport_req_has_time,
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output wire [63:0] m_ctrlport_req_time,
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input wire m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [31:0] m_ctrlport_resp_data,
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// Slave
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [ 9:0] s_ctrlport_req_portid,
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input wire [15:0] s_ctrlport_req_rem_epid,
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input wire [ 9:0] s_ctrlport_req_rem_portid,
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input wire [31:0] s_ctrlport_req_data,
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input wire [ 3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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output wire s_ctrlport_resp_ack,
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output wire [ 1:0] s_ctrlport_resp_status,
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output wire [31:0] s_ctrlport_resp_data,
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//---------------------------------------------------------------------------
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// Client Data Interface
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//---------------------------------------------------------------------------
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// Clock
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input wire axis_data_clk,
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input wire axis_data_rst,
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// Output data stream (to user logic)
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output wire [(NUM_DATA_I*ITEM_W*NIPC)-1:0] m_axis_tdata,
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output wire [ (NUM_DATA_I*NIPC)-1:0] m_axis_tkeep,
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output wire [ NUM_DATA_I-1:0] m_axis_tlast,
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output wire [ NUM_DATA_I-1:0] m_axis_tvalid,
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input wire [ NUM_DATA_I-1:0] m_axis_tready,
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// Sideband information
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output wire [ (NUM_DATA_I*64)-1:0] m_axis_ttimestamp,
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output wire [ NUM_DATA_I-1:0] m_axis_thas_time,
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output wire [ NUM_DATA_I-1:0] m_axis_teov,
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output wire [ NUM_DATA_I-1:0] m_axis_teob,
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// Input data stream (from user logic)
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input wire [(NUM_DATA_O*ITEM_W*NIPC)-1:0] s_axis_tdata,
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input wire [ (NUM_DATA_O*NIPC)-1:0] s_axis_tkeep,
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input wire [ NUM_DATA_O-1:0] s_axis_tlast,
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input wire [ NUM_DATA_O-1:0] s_axis_tvalid,
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output wire [ NUM_DATA_O-1:0] s_axis_tready,
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// Sideband info (sampled on the first cycle of the packet)
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input wire [ (NUM_DATA_O*64)-1:0] s_axis_ttimestamp,
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input wire [ NUM_DATA_O-1:0] s_axis_thas_time,
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input wire [ NUM_DATA_O-1:0] s_axis_teov,
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input wire [ NUM_DATA_O-1:0] s_axis_teob
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);
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localparam SNK_INFO_FIFO_SIZE = 4;
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localparam SNK_PYLD_FIFO_SIZE = PYLD_FIFO_SIZE;
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localparam SRC_INFO_FIFO_SIZE = 4;
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localparam SRC_PYLD_FIFO_SIZE = MTU;
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//---------------------------------------------------------------------------
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// Backend Interface
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//---------------------------------------------------------------------------
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wire data_i_flush_en;
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wire [31:0] data_i_flush_timeout;
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wire [63:0] data_i_flush_active;
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wire [63:0] data_i_flush_done;
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wire data_o_flush_en;
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wire [31:0] data_o_flush_timeout;
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wire [63:0] data_o_flush_active;
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wire [63:0] data_o_flush_done;
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backend_iface #(
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.NOC_ID (NOC_ID),
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.NUM_DATA_I (NUM_DATA_I),
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.NUM_DATA_O (NUM_DATA_O),
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.CTRL_FIFOSIZE (CTRL_FIFO_SIZE),
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.MTU (MTU)
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) backend_iface_i (
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.rfnoc_core_config (rfnoc_core_config),
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.rfnoc_core_status (rfnoc_core_status),
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.rfnoc_chdr_rst (rfnoc_chdr_rst),
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.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
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.data_i_flush_en (data_i_flush_en),
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.data_i_flush_timeout (data_i_flush_timeout),
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.data_i_flush_active (data_i_flush_active),
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.data_i_flush_done (data_i_flush_done),
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.data_o_flush_en (data_o_flush_en),
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.data_o_flush_timeout (data_o_flush_timeout),
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.data_o_flush_active (data_o_flush_active),
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.data_o_flush_done (data_o_flush_done)
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);
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//---------------------------------------------------------------------------
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// Control Path
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//---------------------------------------------------------------------------
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ctrlport_endpoint #(
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.THIS_PORTID (THIS_PORTID ),
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.SYNC_CLKS (0 ),
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.AXIS_CTRL_MST_EN (CTRLPORT_SLV_EN),
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.AXIS_CTRL_SLV_EN (CTRLPORT_MST_EN),
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.SLAVE_FIFO_SIZE (CTRL_FIFO_SIZE )
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) ctrlport_ep_i (
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
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.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
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.ctrlport_clk (ctrlport_clk ),
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.ctrlport_rst (ctrlport_rst ),
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.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata ),
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.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast ),
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.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid ),
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.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready ),
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.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata ),
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.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast ),
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.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid ),
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.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready ),
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.m_ctrlport_req_wr (m_ctrlport_req_wr ),
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.m_ctrlport_req_rd (m_ctrlport_req_rd ),
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.m_ctrlport_req_addr (m_ctrlport_req_addr ),
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.m_ctrlport_req_data (m_ctrlport_req_data ),
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.m_ctrlport_req_byte_en (m_ctrlport_req_byte_en ),
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.m_ctrlport_req_has_time (m_ctrlport_req_has_time ),
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.m_ctrlport_req_time (m_ctrlport_req_time ),
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.m_ctrlport_resp_ack (m_ctrlport_resp_ack ),
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.m_ctrlport_resp_status (m_ctrlport_resp_status ),
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.m_ctrlport_resp_data (m_ctrlport_resp_data ),
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.s_ctrlport_req_wr (s_ctrlport_req_wr ),
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.s_ctrlport_req_rd (s_ctrlport_req_rd ),
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.s_ctrlport_req_addr (s_ctrlport_req_addr ),
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.s_ctrlport_req_portid (s_ctrlport_req_portid ),
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.s_ctrlport_req_rem_epid (s_ctrlport_req_rem_epid ),
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.s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
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.s_ctrlport_req_data (s_ctrlport_req_data ),
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.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en ),
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.s_ctrlport_req_has_time (s_ctrlport_req_has_time ),
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.s_ctrlport_req_time (s_ctrlport_req_time ),
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.s_ctrlport_resp_ack (s_ctrlport_resp_ack ),
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.s_ctrlport_resp_status (s_ctrlport_resp_status ),
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.s_ctrlport_resp_data (s_ctrlport_resp_data )
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);
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//---------------------------------------------------------------------------
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// Data Path
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//---------------------------------------------------------------------------
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genvar i;
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generate
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for (i = 0; i < NUM_DATA_I; i = i + 1) begin: chdr_to_data
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chdr_to_axis_data #(
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.CHDR_W (CHDR_W),
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.ITEM_W (ITEM_W),
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.NIPC (NIPC),
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.SYNC_CLKS (0),
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.INFO_FIFO_SIZE (SNK_INFO_FIFO_SIZE),
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.PYLD_FIFO_SIZE (SNK_PYLD_FIFO_SIZE)
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) chdr_to_axis_data_i (
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.axis_chdr_clk (rfnoc_chdr_clk),
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.axis_chdr_rst (rfnoc_chdr_rst),
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.axis_data_clk (axis_data_clk),
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.axis_data_rst (axis_data_rst),
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.s_axis_chdr_tdata (s_rfnoc_chdr_tdata [(i*CHDR_W)+:CHDR_W]),
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.s_axis_chdr_tlast (s_rfnoc_chdr_tlast [i]),
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.s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid [i]),
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.s_axis_chdr_tready (s_rfnoc_chdr_tready [i]),
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.m_axis_tdata (m_axis_tdata [i*ITEM_W*NIPC +: ITEM_W*NIPC]),
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.m_axis_tkeep (m_axis_tkeep [i*NIPC +: NIPC]),
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.m_axis_tlast (m_axis_tlast [i]),
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.m_axis_tvalid (m_axis_tvalid [i]),
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.m_axis_tready (m_axis_tready [i]),
|
||||
.m_axis_ttimestamp (m_axis_ttimestamp [i*64 +: 64]),
|
||||
.m_axis_thas_time (m_axis_thas_time [i]),
|
||||
.m_axis_tlength (),
|
||||
.m_axis_teov (m_axis_teov [i]),
|
||||
.m_axis_teob (m_axis_teob [i]),
|
||||
.flush_en (data_i_flush_en),
|
||||
.flush_timeout (data_i_flush_timeout),
|
||||
.flush_active (data_i_flush_active [i]),
|
||||
.flush_done (data_i_flush_done [i])
|
||||
);
|
||||
end
|
||||
|
||||
for (i = 0; i < NUM_DATA_O; i = i + 1) begin: data_to_chdr
|
||||
axis_data_to_chdr #(
|
||||
.CHDR_W (CHDR_W),
|
||||
.ITEM_W (ITEM_W),
|
||||
.NIPC (NIPC),
|
||||
.SYNC_CLKS (0),
|
||||
.INFO_FIFO_SIZE (4),
|
||||
.PYLD_FIFO_SIZE (SRC_INFO_FIFO_SIZE),
|
||||
.MTU (SRC_PYLD_FIFO_SIZE)
|
||||
) axis_data_to_chdr_i (
|
||||
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||
.axis_data_clk (axis_data_clk),
|
||||
.axis_data_rst (axis_data_rst),
|
||||
.m_axis_chdr_tdata (m_rfnoc_chdr_tdata [i*CHDR_W +: CHDR_W]),
|
||||
.m_axis_chdr_tlast (m_rfnoc_chdr_tlast [i]),
|
||||
.m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid [i]),
|
||||
.m_axis_chdr_tready (m_rfnoc_chdr_tready [i]),
|
||||
.s_axis_tdata (s_axis_tdata [i*ITEM_W*NIPC +: ITEM_W*NIPC]),
|
||||
.s_axis_tkeep (s_axis_tkeep [i*NIPC +: NIPC]),
|
||||
.s_axis_tlast (s_axis_tlast [i]),
|
||||
.s_axis_tvalid (s_axis_tvalid [i]),
|
||||
.s_axis_tready (s_axis_tready [i]),
|
||||
.s_axis_ttimestamp (s_axis_ttimestamp [i*64 +: 64]),
|
||||
.s_axis_thas_time (s_axis_thas_time [i]),
|
||||
.s_axis_teov (s_axis_teov [i]),
|
||||
.s_axis_teob (s_axis_teob [i]),
|
||||
.flush_en (data_o_flush_en),
|
||||
.flush_timeout (data_o_flush_timeout),
|
||||
.flush_active (data_o_flush_active [i]),
|
||||
.flush_done (data_o_flush_done [i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,138 @@
|
||||
//
|
||||
// Copyright 2018 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
|
||||
// mixer with 90 degree angles, i.e., multiplying the input signal with 1, i, -1, -i:
|
||||
|
||||
// Let S(t) = I(t) + i*Q(t) be the input signal based on inputs i_in and q_in
|
||||
// Multiplying with (1,i,-1,-i) then becomes:
|
||||
// S(t) * 1 = I(t) + i*Q(t)
|
||||
// S(t) * i = -Q(t) + i*I(t)
|
||||
// S(t) * -1 = -I(t) - i*Q(t)
|
||||
// S(t) * -i = Q(t) - i*I(t)
|
||||
|
||||
// To control the direction of rotation, the dirctn input is used
|
||||
// When set to 0, the phase is increased with pi/2 every sample, i.e., rotating counter clock wise
|
||||
// When set to 1, the phase is increased with -pi/2 every sample, i.e., rotating clock wise
|
||||
|
||||
// the input is the concatenation of the i and q signal: {i_in, q_in}
|
||||
|
||||
module quarter_rate_downconverter #(
|
||||
parameter WIDTH=24
|
||||
)(
|
||||
input clk,
|
||||
input reset,
|
||||
input phase_sync,
|
||||
|
||||
input [2*WIDTH-1:0] i_tdata,
|
||||
input i_tlast,
|
||||
input i_tvalid,
|
||||
output i_tready,
|
||||
|
||||
output [2*WIDTH-1:0] o_tdata,
|
||||
output o_tlast,
|
||||
output o_tvalid,
|
||||
input o_tready,
|
||||
|
||||
input dirctn
|
||||
);
|
||||
|
||||
// temporary signals for i and q after rotation
|
||||
reg [WIDTH-1:0] tmp_i = {WIDTH{1'b0}};
|
||||
reg [WIDTH-1:0] tmp_q = {WIDTH{1'b0}};
|
||||
|
||||
// State machine types and reg
|
||||
localparam S0=0, S1=1, S2=2, S3=3;
|
||||
reg[1:0] cur_state;
|
||||
|
||||
// split input into i and q signal
|
||||
wire[WIDTH-1:0] i_in, q_in;
|
||||
assign i_in = i_tdata[2*WIDTH-1:WIDTH];
|
||||
assign q_in = i_tdata[WIDTH-1:0];
|
||||
|
||||
// The state machine doing the rotations among states
|
||||
always @(posedge clk) begin
|
||||
if(reset || phase_sync) begin
|
||||
cur_state <= S0;
|
||||
end else begin
|
||||
case (cur_state)
|
||||
S0: begin
|
||||
if(i_tvalid == 1'b1 && i_tready == 1'b1)
|
||||
if(dirctn == 1'b0)
|
||||
cur_state <= S1;
|
||||
else
|
||||
cur_state <= S3;
|
||||
else
|
||||
cur_state <= S0;
|
||||
end
|
||||
S1: begin
|
||||
if(i_tvalid == 1'b1 && i_tready == 1'b1)
|
||||
if(dirctn == 1'b0)
|
||||
cur_state <= S2;
|
||||
else
|
||||
cur_state <= S0;
|
||||
else
|
||||
cur_state <= S1;
|
||||
end
|
||||
S2: begin
|
||||
if(i_tvalid == 1'b1 && i_tready == 1'b1)
|
||||
if(dirctn == 1'b0)
|
||||
cur_state <= S3;
|
||||
else
|
||||
cur_state <= S1;
|
||||
else
|
||||
cur_state <= S2;
|
||||
end
|
||||
S3: begin
|
||||
if(i_tvalid == 1'b1 && i_tready == 1'b1)
|
||||
if(dirctn == 1'b0)
|
||||
cur_state <= S0;
|
||||
else
|
||||
cur_state <= S2;
|
||||
else
|
||||
cur_state <= S3;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// Multiplication of input IQ signal with (1,i,-1,-i):
|
||||
always @(*) begin
|
||||
case (cur_state)
|
||||
S0: begin
|
||||
// S(t) * 1 = I(t) + iQ(t):
|
||||
tmp_i = i_in;
|
||||
tmp_q = q_in;
|
||||
end
|
||||
S1: begin
|
||||
// S(t) * i = -Q(t) + iI(t):
|
||||
tmp_i = -q_in;
|
||||
tmp_q = i_in;
|
||||
end
|
||||
S2: begin
|
||||
// S(t) * -1 = -I(t) - iQ(t):
|
||||
tmp_i = -i_in;
|
||||
tmp_q = -q_in;
|
||||
end
|
||||
S3: begin
|
||||
// S(t) * -i = Q(t) - iI(t):
|
||||
tmp_i = q_in;
|
||||
tmp_q = -i_in;
|
||||
end
|
||||
default: begin
|
||||
tmp_i = i_in;
|
||||
tmp_q = q_in;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// Flop for valid and ready signals and shortening of comb. paths.
|
||||
axi_fifo #(.WIDTH(2*WIDTH + 1), .SIZE(1)) flop (
|
||||
.clk(clk), .reset(reset), .clear(1'b0),
|
||||
.i_tdata({i_tlast, tmp_i, tmp_q}), .i_tvalid(i_tvalid), .i_tready(i_tready),
|
||||
.o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
|
||||
.occupied(), .space());
|
||||
|
||||
endmodule // quarter_rate_downconverter
|
||||
@@ -0,0 +1,370 @@
|
||||
//
|
||||
// Copyright 2019 Ettus Research, a National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: radio_core
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// A radio core for RFNoC. This core contains all logic in the radio clock
|
||||
// domain for interfacing to a single RX/TX radio. It includes registers shared
|
||||
// by both Rx and Tx logic and instantiates Rx and Tx interface cores.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// BASE_ADDR : Base address for this radio block instance
|
||||
// SAMP_W : Width of a radio sample
|
||||
// NSPC : Number of radio samples per radio clock cycle
|
||||
//
|
||||
|
||||
|
||||
module radio_core #(
|
||||
parameter SAMP_W = 32,
|
||||
parameter NSPC = 1
|
||||
) (
|
||||
input wire radio_clk,
|
||||
input wire radio_rst,
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Control Interface
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// Slave
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
output wire s_ctrlport_resp_ack,
|
||||
output wire [31:0] s_ctrlport_resp_data,
|
||||
|
||||
// Master
|
||||
output wire m_ctrlport_req_wr,
|
||||
output wire [19:0] m_ctrlport_req_addr,
|
||||
output wire [ 9:0] m_ctrlport_req_portid,
|
||||
output wire [15:0] m_ctrlport_req_rem_epid,
|
||||
output wire [ 9:0] m_ctrlport_req_rem_portid,
|
||||
output wire [31:0] m_ctrlport_req_data,
|
||||
output wire m_ctrlport_req_has_time,
|
||||
output wire [63:0] m_ctrlport_req_time,
|
||||
input wire m_ctrlport_resp_ack,
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Data Interface
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// Tx Radio Data Stream
|
||||
input wire [(SAMP_W*NSPC)-1:0] s_axis_tdata,
|
||||
input wire s_axis_tlast,
|
||||
input wire s_axis_tvalid,
|
||||
output wire s_axis_tready,
|
||||
// Sideband info
|
||||
input wire [ 63:0] s_axis_ttimestamp,
|
||||
input wire s_axis_thas_time,
|
||||
input wire s_axis_teob,
|
||||
|
||||
// Rx Radio Data Stream
|
||||
output wire [(SAMP_W*NSPC)-1:0] m_axis_tdata,
|
||||
output wire m_axis_tlast,
|
||||
output wire m_axis_tvalid,
|
||||
input wire m_axis_tready,
|
||||
// Sideband info
|
||||
output wire [ 63:0] m_axis_ttimestamp,
|
||||
output wire m_axis_thas_time,
|
||||
output wire m_axis_teob,
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Radio Interface
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
input wire [63:0] radio_time,
|
||||
|
||||
// Radio Rx Interface
|
||||
input wire [SAMP_W*NSPC-1:0] radio_rx_data,
|
||||
input wire radio_rx_stb,
|
||||
output wire radio_rx_running,
|
||||
|
||||
// Radio Tx Interface
|
||||
output wire [SAMP_W*NSPC-1:0] radio_tx_data,
|
||||
input wire radio_tx_stb,
|
||||
output wire radio_tx_running
|
||||
);
|
||||
|
||||
`include "rfnoc_block_radio_regs.vh"
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Split Control Port Interface
|
||||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// This block splits the single slave interface of the radio core into
|
||||
// multiple interfaces, one for each subcomponent. The responses from each
|
||||
// subcomponent are merged into a single response and sent back out the slave
|
||||
// interface.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// Registers shared by Rx and Tx
|
||||
wire ctrlport_general_req_wr;
|
||||
wire ctrlport_general_req_rd;
|
||||
wire [19:0] ctrlport_general_req_addr;
|
||||
wire [31:0] ctrlport_general_req_data;
|
||||
reg ctrlport_general_resp_ack = 1'b0;
|
||||
reg [31:0] ctrlport_general_resp_data = 0;
|
||||
|
||||
// Tx core registers
|
||||
wire ctrlport_tx_req_wr;
|
||||
wire ctrlport_tx_req_rd;
|
||||
wire [19:0] ctrlport_tx_req_addr;
|
||||
wire [31:0] ctrlport_tx_req_data;
|
||||
wire ctrlport_tx_resp_ack;
|
||||
wire [31:0] ctrlport_tx_resp_data;
|
||||
|
||||
// Rx core registers
|
||||
wire ctrlport_rx_req_wr;
|
||||
wire ctrlport_rx_req_rd;
|
||||
wire [19:0] ctrlport_rx_req_addr;
|
||||
wire [31:0] ctrlport_rx_req_data;
|
||||
wire ctrlport_rx_resp_ack;
|
||||
wire [31:0] ctrlport_rx_resp_data;
|
||||
|
||||
ctrlport_splitter #(
|
||||
.NUM_SLAVES (3)
|
||||
) ctrlport_decoder_i (
|
||||
.ctrlport_clk (radio_clk),
|
||||
.ctrlport_rst (radio_rst),
|
||||
.s_ctrlport_req_wr (s_ctrlport_req_wr),
|
||||
.s_ctrlport_req_rd (s_ctrlport_req_rd),
|
||||
.s_ctrlport_req_addr (s_ctrlport_req_addr),
|
||||
.s_ctrlport_req_data (s_ctrlport_req_data),
|
||||
.s_ctrlport_req_byte_en (4'b0),
|
||||
.s_ctrlport_req_has_time (1'b0),
|
||||
.s_ctrlport_req_time (64'b0),
|
||||
.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
|
||||
.s_ctrlport_resp_status (),
|
||||
.s_ctrlport_resp_data (s_ctrlport_resp_data),
|
||||
.m_ctrlport_req_wr ({ctrlport_general_req_wr,
|
||||
ctrlport_tx_req_wr,
|
||||
ctrlport_rx_req_wr}),
|
||||
.m_ctrlport_req_rd ({ctrlport_general_req_rd,
|
||||
ctrlport_tx_req_rd,
|
||||
ctrlport_rx_req_rd}),
|
||||
.m_ctrlport_req_addr ({ctrlport_general_req_addr,
|
||||
ctrlport_tx_req_addr,
|
||||
ctrlport_rx_req_addr}),
|
||||
.m_ctrlport_req_data ({ctrlport_general_req_data,
|
||||
ctrlport_tx_req_data,
|
||||
ctrlport_rx_req_data}),
|
||||
.m_ctrlport_req_byte_en (),
|
||||
.m_ctrlport_req_has_time (),
|
||||
.m_ctrlport_req_time (),
|
||||
.m_ctrlport_resp_ack ({ctrlport_general_resp_ack,
|
||||
ctrlport_tx_resp_ack,
|
||||
ctrlport_rx_resp_ack}),
|
||||
.m_ctrlport_resp_status (6'b0),
|
||||
.m_ctrlport_resp_data ({ctrlport_general_resp_data,
|
||||
ctrlport_tx_resp_data,
|
||||
ctrlport_rx_resp_data})
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Merge Control Port Interfaces
|
||||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// This block merges the master control port interfaces of the Rx and Tx
|
||||
// cores into a single master control port interface. Both the Rx and Tx
|
||||
// cores support error reporting by writing to a control port interface. This
|
||||
// block arbitrates the requests between the Rx and Tx cores. Rx and Tx only
|
||||
// support writes for error reporting, not reads. Time and byte enables are
|
||||
// also not needed. Hence, several ports are unconnected.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// Tx and Rx error reporting signals
|
||||
wire ctrlport_err_tx_req_wr, ctrlport_err_rx_req_wr;
|
||||
wire [19:0] ctrlport_err_tx_req_addr, ctrlport_err_rx_req_addr;
|
||||
wire [31:0] ctrlport_err_tx_req_data, ctrlport_err_rx_req_data;
|
||||
wire ctrlport_err_tx_req_has_time, ctrlport_err_rx_req_has_time;
|
||||
wire [63:0] ctrlport_err_tx_req_time, ctrlport_err_rx_req_time;
|
||||
wire [ 9:0] ctrlport_err_tx_req_portid, ctrlport_err_rx_req_portid;
|
||||
wire [15:0] ctrlport_err_tx_req_rem_epid, ctrlport_err_rx_req_rem_epid;
|
||||
wire [ 9:0] ctrlport_err_tx_req_rem_portid, ctrlport_err_rx_req_rem_portid;
|
||||
wire ctrlport_err_tx_resp_ack, ctrlport_err_rx_resp_ack;
|
||||
|
||||
|
||||
ctrlport_combiner #(
|
||||
.NUM_MASTERS (2),
|
||||
.PRIORITY (0)
|
||||
) ctrlport_req_combine_i (
|
||||
.ctrlport_clk (radio_clk),
|
||||
.ctrlport_rst (radio_rst),
|
||||
.s_ctrlport_req_wr ({ctrlport_err_tx_req_wr, ctrlport_err_rx_req_wr}),
|
||||
.s_ctrlport_req_rd (2'b0),
|
||||
.s_ctrlport_req_addr ({ctrlport_err_tx_req_addr, ctrlport_err_rx_req_addr}),
|
||||
.s_ctrlport_req_portid ({ctrlport_err_tx_req_portid, ctrlport_err_rx_req_portid}),
|
||||
.s_ctrlport_req_rem_epid ({ctrlport_err_tx_req_rem_epid, ctrlport_err_rx_req_rem_epid}),
|
||||
.s_ctrlport_req_rem_portid ({ctrlport_err_tx_req_rem_portid, ctrlport_err_rx_req_rem_portid}),
|
||||
.s_ctrlport_req_data ({ctrlport_err_tx_req_data, ctrlport_err_rx_req_data}),
|
||||
.s_ctrlport_req_byte_en (8'hFF),
|
||||
.s_ctrlport_req_has_time ({ctrlport_err_tx_req_has_time, ctrlport_err_rx_req_has_time}),
|
||||
.s_ctrlport_req_time ({ctrlport_err_tx_req_time, ctrlport_err_rx_req_time}),
|
||||
.s_ctrlport_resp_ack ({ctrlport_err_tx_resp_ack, ctrlport_err_rx_resp_ack}),
|
||||
.s_ctrlport_resp_status (),
|
||||
.s_ctrlport_resp_data (),
|
||||
.m_ctrlport_req_wr (m_ctrlport_req_wr),
|
||||
.m_ctrlport_req_rd (),
|
||||
.m_ctrlport_req_addr (m_ctrlport_req_addr),
|
||||
.m_ctrlport_req_portid (m_ctrlport_req_portid),
|
||||
.m_ctrlport_req_rem_epid (m_ctrlport_req_rem_epid),
|
||||
.m_ctrlport_req_rem_portid (m_ctrlport_req_rem_portid),
|
||||
.m_ctrlport_req_data (m_ctrlport_req_data),
|
||||
.m_ctrlport_req_byte_en (),
|
||||
.m_ctrlport_req_has_time (m_ctrlport_req_has_time),
|
||||
.m_ctrlport_req_time (m_ctrlport_req_time),
|
||||
.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
|
||||
.m_ctrlport_resp_status (2'b0),
|
||||
.m_ctrlport_resp_data (0)
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// General Registers
|
||||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// These are registers that apply to both Rx and Tx and are shared by both.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
reg reg_loopback_en = 1'b0;
|
||||
|
||||
always @(posedge radio_clk) begin
|
||||
if (radio_rst) begin
|
||||
ctrlport_general_resp_ack <= 0;
|
||||
ctrlport_general_resp_data <= 0;
|
||||
reg_loopback_en <= 0;
|
||||
end else begin
|
||||
// Default assignments
|
||||
ctrlport_general_resp_ack <= 0;
|
||||
ctrlport_general_resp_data <= 0;
|
||||
|
||||
// Handle register writes
|
||||
if (ctrlport_general_req_wr) begin
|
||||
case (ctrlport_general_req_addr)
|
||||
REG_LOOPBACK_EN: begin
|
||||
reg_loopback_en <= ctrlport_general_req_data[0];
|
||||
ctrlport_general_resp_ack <= 1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// Handle register reads
|
||||
if (ctrlport_general_req_rd) begin
|
||||
case (ctrlport_general_req_addr)
|
||||
REG_LOOPBACK_EN: begin
|
||||
ctrlport_general_resp_data <= 0;
|
||||
ctrlport_general_resp_data[0] <= reg_loopback_en;
|
||||
ctrlport_general_resp_ack <= 1;
|
||||
end
|
||||
REG_RADIO_WIDTH: begin
|
||||
ctrlport_general_resp_data <= { SAMP_W[15:0], NSPC[15:0] };
|
||||
ctrlport_general_resp_ack <= 1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Tx to Rx Loopback
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
wire [SAMP_W*NSPC-1:0] radio_rx_data_mux;
|
||||
wire radio_rx_stb_mux;
|
||||
|
||||
assign radio_rx_data_mux = reg_loopback_en ? radio_tx_data : radio_rx_data;
|
||||
assign radio_rx_stb_mux = reg_loopback_en ? radio_tx_stb : radio_rx_stb;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Tx Core
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
radio_tx_core #(
|
||||
.SAMP_W (SAMP_W),
|
||||
.NSPC (NSPC)
|
||||
) radio_tx_core_i (
|
||||
.radio_clk (radio_clk),
|
||||
.radio_rst (radio_rst),
|
||||
.s_ctrlport_req_wr (ctrlport_tx_req_wr),
|
||||
.s_ctrlport_req_rd (ctrlport_tx_req_rd),
|
||||
.s_ctrlport_req_addr (ctrlport_tx_req_addr),
|
||||
.s_ctrlport_req_data (ctrlport_tx_req_data),
|
||||
.s_ctrlport_resp_ack (ctrlport_tx_resp_ack),
|
||||
.s_ctrlport_resp_data (ctrlport_tx_resp_data),
|
||||
.m_ctrlport_req_wr (ctrlport_err_tx_req_wr),
|
||||
.m_ctrlport_req_addr (ctrlport_err_tx_req_addr),
|
||||
.m_ctrlport_req_data (ctrlport_err_tx_req_data),
|
||||
.m_ctrlport_req_has_time (ctrlport_err_tx_req_has_time),
|
||||
.m_ctrlport_req_time (ctrlport_err_tx_req_time),
|
||||
.m_ctrlport_req_portid (ctrlport_err_tx_req_portid),
|
||||
.m_ctrlport_req_rem_epid (ctrlport_err_tx_req_rem_epid),
|
||||
.m_ctrlport_req_rem_portid (ctrlport_err_tx_req_rem_portid),
|
||||
.m_ctrlport_resp_ack (ctrlport_err_tx_resp_ack),
|
||||
.radio_time (radio_time),
|
||||
.radio_tx_data (radio_tx_data),
|
||||
.radio_tx_stb (radio_tx_stb),
|
||||
.radio_tx_running (radio_tx_running),
|
||||
.s_axis_tdata (s_axis_tdata),
|
||||
.s_axis_tlast (s_axis_tlast),
|
||||
.s_axis_tvalid (s_axis_tvalid),
|
||||
.s_axis_tready (s_axis_tready),
|
||||
.s_axis_ttimestamp (s_axis_ttimestamp),
|
||||
.s_axis_thas_time (s_axis_thas_time),
|
||||
.s_axis_teob (s_axis_teob)
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Rx Core
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
radio_rx_core #(
|
||||
.SAMP_W (SAMP_W),
|
||||
.NSPC (NSPC)
|
||||
) radio_rx_core_i (
|
||||
.radio_clk (radio_clk),
|
||||
.radio_rst (radio_rst),
|
||||
.s_ctrlport_req_wr (ctrlport_rx_req_wr),
|
||||
.s_ctrlport_req_rd (ctrlport_rx_req_rd),
|
||||
.s_ctrlport_req_addr (ctrlport_rx_req_addr),
|
||||
.s_ctrlport_req_data (ctrlport_rx_req_data),
|
||||
.s_ctrlport_resp_ack (ctrlport_rx_resp_ack),
|
||||
.s_ctrlport_resp_data (ctrlport_rx_resp_data),
|
||||
.m_ctrlport_req_wr (ctrlport_err_rx_req_wr),
|
||||
.m_ctrlport_req_addr (ctrlport_err_rx_req_addr),
|
||||
.m_ctrlport_req_data (ctrlport_err_rx_req_data),
|
||||
.m_ctrlport_req_has_time (ctrlport_err_rx_req_has_time),
|
||||
.m_ctrlport_req_time (ctrlport_err_rx_req_time),
|
||||
.m_ctrlport_req_portid (ctrlport_err_rx_req_portid),
|
||||
.m_ctrlport_req_rem_epid (ctrlport_err_rx_req_rem_epid),
|
||||
.m_ctrlport_req_rem_portid (ctrlport_err_rx_req_rem_portid),
|
||||
.m_ctrlport_resp_ack (ctrlport_err_rx_resp_ack),
|
||||
.radio_time (radio_time),
|
||||
.radio_rx_data (radio_rx_data_mux),
|
||||
.radio_rx_stb (radio_rx_stb_mux),
|
||||
.radio_rx_running (radio_rx_running),
|
||||
.m_axis_tdata (m_axis_tdata),
|
||||
.m_axis_tlast (m_axis_tlast),
|
||||
.m_axis_tvalid (m_axis_tvalid),
|
||||
.m_axis_tready (m_axis_tready),
|
||||
.m_axis_ttimestamp (m_axis_ttimestamp),
|
||||
.m_axis_thas_time (m_axis_thas_time),
|
||||
.m_axis_teob (m_axis_teob)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,521 @@
|
||||
//
|
||||
// Copyright 2019 Ettus Research, a National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: radio_rx_core
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This module contains the core Rx radio acquisition logic. It retrieves
|
||||
// sample data from the radio interface, as indicated by the radio's strobe
|
||||
// signal, and outputs the data via AXI-Stream.
|
||||
//
|
||||
// The receiver is operated by writing a time (optionally) to the
|
||||
// REG_RX_CMD_TIME_* registers and a number of words (optionally) to
|
||||
// REG_RX_CMD_NUM_WORDS_* registers followed by writing a command word to
|
||||
// REG_RX_CMD. The command word indicates whether it is a finite ("num samps
|
||||
// and done") or continuous acquisition and whether or not the acquisition
|
||||
// should start at the time indicated byREG_RX_CMD_TIME_*. A stop command will
|
||||
// stop any acquisition that's waiting to start or is in progress.
|
||||
//
|
||||
// The REG_RX_MAX_WORDS_PER_PKT and REG_RX_ERR_* registers should be
|
||||
// initialized prior to the first acquisition.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// SAMP_W : Width of a radio sample
|
||||
// NSPC : Number of radio samples per radio clock cycle
|
||||
//
|
||||
`default_nettype none
|
||||
|
||||
|
||||
module radio_rx_core #(
|
||||
parameter SAMP_W = 32,
|
||||
parameter NSPC = 1
|
||||
) (
|
||||
input wire radio_clk,
|
||||
input wire radio_rst,
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Control Interface
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// Slave (Register Reads and Writes)
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
output reg s_ctrlport_resp_ack = 1'b0,
|
||||
output reg [31:0] s_ctrlport_resp_data,
|
||||
|
||||
// Master (Error Reporting)
|
||||
output reg m_ctrlport_req_wr = 1'b0,
|
||||
output reg [19:0] m_ctrlport_req_addr,
|
||||
output reg [31:0] m_ctrlport_req_data,
|
||||
output wire m_ctrlport_req_has_time,
|
||||
output reg [63:0] m_ctrlport_req_time,
|
||||
output wire [ 9:0] m_ctrlport_req_portid,
|
||||
output wire [15:0] m_ctrlport_req_rem_epid,
|
||||
output wire [ 9:0] m_ctrlport_req_rem_portid,
|
||||
input wire m_ctrlport_resp_ack,
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Radio Interface
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
input wire [63:0] radio_time,
|
||||
|
||||
input wire [SAMP_W*NSPC-1:0] radio_rx_data,
|
||||
input wire radio_rx_stb,
|
||||
|
||||
// Status indicator (true when receiving)
|
||||
output wire radio_rx_running,
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// AXI-Stream Data Output
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
output wire [SAMP_W*NSPC-1:0] m_axis_tdata,
|
||||
output wire m_axis_tlast,
|
||||
output wire m_axis_tvalid,
|
||||
input wire m_axis_tready,
|
||||
// Sideband info
|
||||
output wire [ 63:0] m_axis_ttimestamp,
|
||||
output wire m_axis_thas_time,
|
||||
output wire m_axis_teob
|
||||
);
|
||||
|
||||
`include "rfnoc_block_radio_regs.vh"
|
||||
`include "../../core/rfnoc_chdr_utils.vh"
|
||||
|
||||
localparam NUM_WORDS_LEN = RX_CMD_NUM_WORDS_LEN;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Register Read/Write Logic
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
reg reg_cmd_valid = 0; // Indicates when the CMD_FIFO has been written
|
||||
reg [ RX_CMD_LEN-1:0] reg_cmd_word = 0; // Command to execute
|
||||
reg [NUM_WORDS_LEN-1:0] reg_cmd_num_words = 0; // Number of words for the command
|
||||
reg [ 63:0] reg_cmd_time = 0; // Time for the command
|
||||
reg reg_cmd_timed = 0; // Indicates if this is a timed command
|
||||
reg [ 31:0] reg_max_pkt_len = 64; // Maximum words per packet
|
||||
reg [ 9:0] reg_error_portid = 0; // Port ID to use for error reporting
|
||||
reg [ 15:0] reg_error_rem_epid = 0; // Remote EPID to use for error reporting
|
||||
reg [ 9:0] reg_error_rem_portid = 0; // Remote port ID to use for error reporting
|
||||
reg [ 19:0] reg_error_addr = 0; // Address to use for error reporting
|
||||
reg reg_has_time = 1; // Whether or not to use timestamps on data
|
||||
|
||||
wire [15:0] cmd_fifo_space; // Empty space in the command FIFO
|
||||
reg cmd_stop = 0; // Indicates a full stop request
|
||||
wire cmd_stop_ack; // Acknowledgment that a stop has completed
|
||||
reg clear_fifo = 0; // Signal to clear the command FIFO
|
||||
|
||||
assign m_axis_thas_time = reg_has_time;
|
||||
|
||||
always @(posedge radio_clk) begin
|
||||
if (radio_rst) begin
|
||||
s_ctrlport_resp_ack <= 0;
|
||||
reg_cmd_valid <= 0;
|
||||
reg_cmd_word <= 0;
|
||||
reg_cmd_num_words <= 0;
|
||||
reg_cmd_time <= 0;
|
||||
reg_cmd_timed <= 0;
|
||||
reg_max_pkt_len <= 64;
|
||||
reg_error_portid <= 0;
|
||||
reg_error_rem_epid <= 0;
|
||||
reg_error_rem_portid <= 0;
|
||||
reg_error_addr <= 0;
|
||||
reg_has_time <= 1;
|
||||
clear_fifo <= 0;
|
||||
cmd_stop <= 0;
|
||||
end else begin
|
||||
// Default assignments
|
||||
s_ctrlport_resp_ack <= 0;
|
||||
s_ctrlport_resp_data <= 0;
|
||||
reg_cmd_valid <= 0;
|
||||
clear_fifo <= 0;
|
||||
|
||||
// Clear stop register when we enter the STOP state
|
||||
if (cmd_stop_ack) cmd_stop <= 1'b0;
|
||||
|
||||
// Handle register writes
|
||||
if (s_ctrlport_req_wr) begin
|
||||
case (s_ctrlport_req_addr)
|
||||
REG_RX_CMD: begin
|
||||
// All commands go into the command FIFO except STOP
|
||||
reg_cmd_valid <= (s_ctrlport_req_data[RX_CMD_LEN-1:0] != RX_CMD_STOP);
|
||||
reg_cmd_word <= s_ctrlport_req_data[RX_CMD_LEN-1:0];
|
||||
reg_cmd_timed <= s_ctrlport_req_data[RX_CMD_TIMED_POS];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
|
||||
// cmd_stop must remain asserted until it has completed
|
||||
if (!cmd_stop || cmd_stop_ack) begin
|
||||
cmd_stop <= (s_ctrlport_req_data[RX_CMD_LEN-1:0] == RX_CMD_STOP);
|
||||
end
|
||||
clear_fifo <= (s_ctrlport_req_data[RX_CMD_LEN-1:0] == RX_CMD_STOP);
|
||||
end
|
||||
REG_RX_CMD_NUM_WORDS_LO: begin
|
||||
reg_cmd_num_words[31:0] <= s_ctrlport_req_data;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_CMD_NUM_WORDS_HI: begin
|
||||
reg_cmd_num_words[NUM_WORDS_LEN-1:32] <= s_ctrlport_req_data[NUM_WORDS_LEN-32-1:0];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_CMD_TIME_LO: begin
|
||||
reg_cmd_time[31:0] <= s_ctrlport_req_data;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_CMD_TIME_HI: begin
|
||||
reg_cmd_time[63:32] <= s_ctrlport_req_data;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_MAX_WORDS_PER_PKT: begin
|
||||
reg_max_pkt_len <= s_ctrlport_req_data;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_ERR_PORT: begin
|
||||
reg_error_portid <= s_ctrlport_req_data[9:0];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_ERR_REM_PORT: begin
|
||||
reg_error_rem_portid <= s_ctrlport_req_data[9:0];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_ERR_REM_EPID: begin
|
||||
reg_error_rem_epid <= s_ctrlport_req_data[15:0];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_ERR_ADDR: begin
|
||||
reg_error_addr <= s_ctrlport_req_data[19:0];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_HAS_TIME: begin
|
||||
reg_has_time <= s_ctrlport_req_data[0:0];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// Handle register reads
|
||||
if (s_ctrlport_req_rd) begin
|
||||
case (s_ctrlport_req_addr)
|
||||
REG_RX_STATUS: begin
|
||||
s_ctrlport_resp_data[CMD_FIFO_SPACE_POS+:CMD_FIFO_SPACE_LEN]
|
||||
<= cmd_fifo_space[CMD_FIFO_SPACE_LEN-1:0];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_CMD: begin
|
||||
s_ctrlport_resp_data[RX_CMD_LEN-1:0] <= reg_cmd_word;
|
||||
s_ctrlport_resp_data[RX_CMD_TIMED_POS] <= reg_cmd_timed;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_CMD_NUM_WORDS_LO: begin
|
||||
s_ctrlport_resp_data <= reg_cmd_num_words[31:0];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_CMD_NUM_WORDS_HI: begin
|
||||
s_ctrlport_resp_data[NUM_WORDS_LEN-32-1:0] <= reg_cmd_num_words[NUM_WORDS_LEN-1:32];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_CMD_TIME_LO: begin
|
||||
s_ctrlport_resp_data <= reg_cmd_time[31:0];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_CMD_TIME_HI: begin
|
||||
s_ctrlport_resp_data <= reg_cmd_time[63:32];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_MAX_WORDS_PER_PKT: begin
|
||||
s_ctrlport_resp_data <= reg_max_pkt_len;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_ERR_PORT: begin
|
||||
s_ctrlport_resp_data[9:0] <= reg_error_portid;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_ERR_REM_PORT: begin
|
||||
s_ctrlport_resp_data[9:0] <= reg_error_rem_portid;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_ERR_REM_EPID: begin
|
||||
s_ctrlport_resp_data[15:0] <= reg_error_rem_epid;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_ERR_ADDR: begin
|
||||
s_ctrlport_resp_data[19:0] <= reg_error_addr;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_DATA: begin
|
||||
s_ctrlport_resp_data <= radio_rx_data;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_RX_HAS_TIME: begin
|
||||
s_ctrlport_resp_data[0] <= reg_has_time;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Command Queue
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
wire [ 63:0] cmd_time; // Time for next start of command
|
||||
wire cmd_timed; // Command is timed (use cmd_time)
|
||||
wire [NUM_WORDS_LEN-1:0] cmd_num_words; // Number of words for next command
|
||||
wire cmd_continuous; // Command is continuous (ignore cmd_num_words)
|
||||
wire cmd_valid; // cmd_* is a valid command
|
||||
wire cmd_done; // Command has completed and can be popped from FIFO
|
||||
|
||||
axi_fifo #(
|
||||
.WIDTH (64 + 1 + NUM_WORDS_LEN + 1),
|
||||
.SIZE (5) // Ideally, this size will lead to an SRL-based FIFO
|
||||
) cmd_fifo (
|
||||
.clk (radio_clk),
|
||||
.reset (radio_rst),
|
||||
.clear (clear_fifo),
|
||||
.i_tdata ({ reg_cmd_time, reg_cmd_timed, reg_cmd_num_words, (reg_cmd_word == RX_CMD_CONTINUOUS) }),
|
||||
.i_tvalid (reg_cmd_valid),
|
||||
.i_tready (),
|
||||
.o_tdata ({ cmd_time, cmd_timed, cmd_num_words, cmd_continuous }),
|
||||
.o_tvalid (cmd_valid),
|
||||
.o_tready (cmd_done),
|
||||
.space (cmd_fifo_space),
|
||||
.occupied ()
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Receiver State Machine
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// FSM state values
|
||||
localparam ST_IDLE = 0;
|
||||
localparam ST_TIME_CHECK = 1;
|
||||
localparam ST_RUNNING = 2;
|
||||
localparam ST_STOP = 3;
|
||||
localparam ST_REPORT_ERR = 4;
|
||||
localparam ST_REPORT_ERR_WAIT = 5;
|
||||
|
||||
reg [ 2:0] state = ST_IDLE; // Current state
|
||||
reg [NUM_WORDS_LEN-1:0] words_left; // Words left in current command
|
||||
reg [ 31:0] words_left_pkt; // Words left in current packet
|
||||
reg first_word = 1'b1; // Next word is first in packet
|
||||
reg [ 15:0] seq_num = 0; // Sequence number (packet count)
|
||||
reg [ 63:0] error_time; // Time at which overflow occurred
|
||||
reg [ERR_RX_CODE_W-1:0] error_code; // Error code register
|
||||
|
||||
// Output FIFO signals
|
||||
wire [ 15:0] out_fifo_space;
|
||||
reg [SAMP_W*NSPC-1:0] out_fifo_tdata;
|
||||
reg out_fifo_tlast;
|
||||
reg out_fifo_tvalid = 1'b0;
|
||||
reg [ 63:0] out_fifo_timestamp;
|
||||
reg out_fifo_teob;
|
||||
reg out_fifo_almost_full;
|
||||
|
||||
reg [63:0] radio_time_low_samp, radio_time_hi_samp;
|
||||
reg time_now, time_past;
|
||||
|
||||
// All ctrlport requests have a time
|
||||
assign m_ctrlport_req_has_time = 1'b1;
|
||||
|
||||
// Acknowledge STOP requests and pop the command FIFO in the STOP state
|
||||
assign cmd_stop_ack = (state == ST_STOP);
|
||||
assign cmd_done = (state == ST_STOP);
|
||||
|
||||
always @(posedge radio_clk) begin
|
||||
if (radio_rst) begin
|
||||
state <= ST_IDLE;
|
||||
out_fifo_tvalid <= 1'b0;
|
||||
seq_num <= 'd0;
|
||||
m_ctrlport_req_wr <= 1'b0;
|
||||
first_word <= 1'b1;
|
||||
end else begin
|
||||
// Default assignments
|
||||
out_fifo_tvalid <= 1'b0;
|
||||
out_fifo_tlast <= 1'b0;
|
||||
out_fifo_teob <= 1'b0;
|
||||
m_ctrlport_req_wr <= 1'b0;
|
||||
|
||||
if (radio_rx_stb) begin
|
||||
// Get the time for the low sample and the high sample of the radio
|
||||
// word (needed when NISPC > 1). Compensate for the delay required to
|
||||
// check the time by adding 3 clock cycles worth of samples.
|
||||
radio_time_low_samp <= (radio_time + 3*NSPC);
|
||||
radio_time_hi_samp <= (radio_time + 3*NSPC + (NSPC-1));
|
||||
|
||||
// Register the time comparisons so they don't become the critical path
|
||||
time_now <= (cmd_time >= radio_time_low_samp &&
|
||||
cmd_time <= radio_time_hi_samp);
|
||||
time_past <= (cmd_time < radio_time_low_samp);
|
||||
end
|
||||
|
||||
case (state)
|
||||
ST_IDLE : begin
|
||||
// Wait for a new command to arrive and allow a cycle for the time
|
||||
// comparisons to update.
|
||||
if (cmd_valid && radio_rx_stb) begin
|
||||
state <= ST_TIME_CHECK;
|
||||
end else if (cmd_stop) begin
|
||||
state <= ST_STOP;
|
||||
end
|
||||
first_word <= 1'b1;
|
||||
end
|
||||
|
||||
ST_TIME_CHECK : begin
|
||||
if (cmd_stop) begin
|
||||
// Nothing to do but stop (timed STOP commands are not supported)
|
||||
state <= ST_STOP;
|
||||
end else if (cmd_timed && time_past && radio_rx_stb) begin
|
||||
// Got this command later than its execution time
|
||||
//synthesis translate_off
|
||||
$display("WARNING: radio_rx_core: Late command error");
|
||||
//synthesis translate_on
|
||||
error_code <= ERR_RX_LATE_CMD;
|
||||
error_time <= radio_time;
|
||||
state <= ST_REPORT_ERR;
|
||||
end else if (!cmd_timed || (time_now && radio_rx_stb)) begin
|
||||
// Either it's time to run this command or it should run
|
||||
// immediately.
|
||||
words_left <= cmd_num_words;
|
||||
words_left_pkt <= reg_max_pkt_len;
|
||||
state <= ST_RUNNING;
|
||||
end
|
||||
end
|
||||
|
||||
ST_RUNNING : begin
|
||||
if (radio_rx_stb) begin
|
||||
// Output the next word
|
||||
out_fifo_tvalid <= 1'b1;
|
||||
out_fifo_tdata <= radio_rx_data;
|
||||
if (first_word) begin
|
||||
out_fifo_timestamp <= radio_time;
|
||||
first_word <= 1'b0;
|
||||
end
|
||||
|
||||
// Update word counters
|
||||
words_left <= words_left - 1;
|
||||
words_left_pkt <= words_left_pkt - 1;
|
||||
|
||||
if ((words_left == 1 && !cmd_continuous) || cmd_stop) begin
|
||||
// This command has finished, or we've been asked to stop.
|
||||
state <= ST_STOP;
|
||||
out_fifo_tlast <= 1'b1;
|
||||
out_fifo_teob <= 1'b1;
|
||||
first_word <= 1'b1;
|
||||
end else if (words_left_pkt == 1) begin
|
||||
// We've finished building a packet
|
||||
seq_num <= seq_num + 1;
|
||||
words_left_pkt <= reg_max_pkt_len;
|
||||
out_fifo_tlast <= 1'b1;
|
||||
first_word <= 1'b1;
|
||||
end
|
||||
|
||||
// Check for overflow. Note that we've left enough room in the
|
||||
// output FIFO so that we can end the packet cleanly.
|
||||
if (out_fifo_almost_full) begin
|
||||
// End the command and terminate packet early
|
||||
//synthesis translate_off
|
||||
$display("WARNING: radio_rx_core: Overrun error");
|
||||
//synthesis translate_on
|
||||
out_fifo_tlast <= 1'b1;
|
||||
out_fifo_teob <= 1'b1;
|
||||
seq_num <= seq_num + 1;
|
||||
error_time <= radio_time;
|
||||
error_code <= ERR_RX_OVERRUN;
|
||||
state <= ST_REPORT_ERR;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
ST_STOP : begin
|
||||
// This single-cycle state allows time for STOP to be acknowledged
|
||||
// and for the command FIFO to be popped.
|
||||
state <= ST_IDLE;
|
||||
end
|
||||
|
||||
ST_REPORT_ERR : begin
|
||||
// Setup write of error code
|
||||
m_ctrlport_req_wr <= 1'b1;
|
||||
m_ctrlport_req_data <= 0;
|
||||
m_ctrlport_req_data[ERR_RX_CODE_W-1:0] <= error_code;
|
||||
m_ctrlport_req_addr <= reg_error_addr;
|
||||
m_ctrlport_req_time <= error_time;
|
||||
state <= ST_REPORT_ERR_WAIT;
|
||||
end
|
||||
|
||||
ST_REPORT_ERR_WAIT : begin
|
||||
// Wait for write of error code and timestamp to complete
|
||||
if (m_ctrlport_resp_ack) begin
|
||||
state <= ST_STOP;
|
||||
end
|
||||
end
|
||||
|
||||
default : state <= ST_IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign radio_rx_running = (state == ST_RUNNING); // We're actively acquiring
|
||||
|
||||
// Directly connect the port ID, remote port ID, and remote EPID since they
|
||||
// are only used for error reporting.
|
||||
assign m_ctrlport_req_portid = reg_error_portid;
|
||||
assign m_ctrlport_req_rem_epid = reg_error_rem_epid;
|
||||
assign m_ctrlport_req_rem_portid = reg_error_rem_portid;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Output FIFO
|
||||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// Here we buffer output samples and monitor FIFO fullness to be able to
|
||||
// detect overflows.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
axi_fifo #(
|
||||
.WIDTH (1+64+1+SAMP_W*NSPC),
|
||||
.SIZE (5) // Ideally, this size will lead to an SRL-based FIFO
|
||||
) output_fifo (
|
||||
.clk (radio_clk),
|
||||
.reset (radio_rst),
|
||||
.clear (1'b0),
|
||||
.i_tdata ({out_fifo_teob, out_fifo_timestamp, out_fifo_tlast, out_fifo_tdata}),
|
||||
.i_tvalid (out_fifo_tvalid),
|
||||
.i_tready (),
|
||||
.o_tdata ({m_axis_teob, m_axis_ttimestamp, m_axis_tlast, m_axis_tdata}),
|
||||
.o_tvalid (m_axis_tvalid),
|
||||
.o_tready (m_axis_tready),
|
||||
.space (out_fifo_space),
|
||||
.occupied ()
|
||||
);
|
||||
|
||||
// Create a register to indicate if the output FIFO is about to overflow
|
||||
always @(posedge radio_clk) begin
|
||||
if (radio_rst) begin
|
||||
out_fifo_almost_full <= 1'b0;
|
||||
end else begin
|
||||
out_fifo_almost_full <= (out_fifo_space < 5);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`default_nettype wire
|
||||
@@ -0,0 +1,417 @@
|
||||
//
|
||||
// Copyright 2019 Ettus Research, a National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: radio_tx_core
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This module contains the core Tx radio data-path logic. It receives samples
|
||||
// over AXI-Stream that it then sends to the radio interface coincident with a
|
||||
// strobe signal that must be provided by the radio interface.
|
||||
//
|
||||
// There are no registers for starting or stopping the transmitter. It is
|
||||
// operated simply by providing data packets via its AXI-Stream data interface.
|
||||
// The end-of-burst (EOB) signal is used to indicate when the transmitter is
|
||||
// allowed to stop transmitting. Packet timestamps can be used to indicate when
|
||||
// transmission should start.
|
||||
//
|
||||
// Care must be taken to provide data to the transmitter at a rate that is
|
||||
// faster than the radio needs it so that underflows do not occur. Similarly,
|
||||
// timed packets must be delivered before the timestamp expires. If a packet
|
||||
// arrives late, then it will be dropped and the error will be reported via the
|
||||
// CTRL port interface.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// SAMP_W : Width of a radio sample
|
||||
// NSPC : Number of radio samples per radio clock cycle
|
||||
//
|
||||
|
||||
|
||||
module radio_tx_core #(
|
||||
parameter SAMP_W = 32,
|
||||
parameter NSPC = 1
|
||||
) (
|
||||
input wire radio_clk,
|
||||
input wire radio_rst,
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Control Interface
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// Slave (Register Reads and Writes)
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
output reg s_ctrlport_resp_ack = 1'b0,
|
||||
output reg [31:0] s_ctrlport_resp_data,
|
||||
|
||||
// Master (Error Reporting)
|
||||
output reg m_ctrlport_req_wr = 1'b0,
|
||||
output reg [19:0] m_ctrlport_req_addr,
|
||||
output reg [31:0] m_ctrlport_req_data,
|
||||
output wire m_ctrlport_req_has_time,
|
||||
output reg [63:0] m_ctrlport_req_time,
|
||||
output wire [ 9:0] m_ctrlport_req_portid,
|
||||
output wire [15:0] m_ctrlport_req_rem_epid,
|
||||
output wire [ 9:0] m_ctrlport_req_rem_portid,
|
||||
input wire m_ctrlport_resp_ack,
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Radio Interface
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
input wire [63:0] radio_time,
|
||||
|
||||
output wire [SAMP_W*NSPC-1:0] radio_tx_data,
|
||||
input wire radio_tx_stb,
|
||||
|
||||
// Status indicator (true when transmitting)
|
||||
output wire radio_tx_running,
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// AXI-Stream Data Input
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
input wire [SAMP_W*NSPC-1:0] s_axis_tdata,
|
||||
input wire s_axis_tlast,
|
||||
input wire s_axis_tvalid,
|
||||
output wire s_axis_tready,
|
||||
// Sideband info
|
||||
input wire [ 63:0] s_axis_ttimestamp,
|
||||
input wire s_axis_thas_time,
|
||||
input wire s_axis_teob
|
||||
);
|
||||
|
||||
`include "rfnoc_block_radio_regs.vh"
|
||||
`include "../../core/rfnoc_chdr_utils.vh"
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Register Read/Write Logic
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
reg [SAMP_W-1:0] reg_idle_value = 0; // Value to output when transmitter is idle
|
||||
reg [ 9:0] reg_error_portid = 0; // Port ID to use for error reporting
|
||||
reg [ 15:0] reg_error_rem_epid = 0; // Remote EPID to use for error reporting
|
||||
reg [ 9:0] reg_error_rem_portid = 0; // Remote port ID to use for error reporting
|
||||
reg [ 19:0] reg_error_addr = 0; // Address to use for error reporting
|
||||
|
||||
reg [TX_ERR_POLICY_LEN-1:0] reg_policy = TX_ERR_POLICY_PACKET;
|
||||
|
||||
always @(posedge radio_clk) begin
|
||||
if (radio_rst) begin
|
||||
s_ctrlport_resp_ack <= 0;
|
||||
reg_idle_value <= 0;
|
||||
reg_error_portid <= 0;
|
||||
reg_error_rem_epid <= 0;
|
||||
reg_error_rem_portid <= 0;
|
||||
reg_error_addr <= 0;
|
||||
reg_policy <= TX_ERR_POLICY_PACKET;
|
||||
end else begin
|
||||
// Default assignments
|
||||
s_ctrlport_resp_ack <= 0;
|
||||
s_ctrlport_resp_data <= 0;
|
||||
|
||||
// Handle register writes
|
||||
if (s_ctrlport_req_wr) begin
|
||||
case (s_ctrlport_req_addr)
|
||||
REG_TX_IDLE_VALUE: begin
|
||||
reg_idle_value <= s_ctrlport_req_data[SAMP_W-1:0];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_TX_ERROR_POLICY: begin
|
||||
// Only allow valid configurations
|
||||
case (s_ctrlport_req_data[TX_ERR_POLICY_LEN-1:0])
|
||||
TX_ERR_POLICY_PACKET : reg_policy <= TX_ERR_POLICY_PACKET;
|
||||
TX_ERR_POLICY_BURST : reg_policy <= TX_ERR_POLICY_BURST;
|
||||
default : reg_policy <= TX_ERR_POLICY_PACKET;
|
||||
endcase
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_TX_ERR_PORT: begin
|
||||
reg_error_portid <= s_ctrlport_req_data[9:0];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_TX_ERR_REM_PORT: begin
|
||||
reg_error_rem_portid <= s_ctrlport_req_data[9:0];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_TX_ERR_REM_EPID: begin
|
||||
reg_error_rem_epid <= s_ctrlport_req_data[15:0];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_TX_ERR_ADDR: begin
|
||||
reg_error_addr <= s_ctrlport_req_data[19:0];
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// Handle register reads
|
||||
if (s_ctrlport_req_rd) begin
|
||||
case (s_ctrlport_req_addr)
|
||||
REG_TX_IDLE_VALUE: begin
|
||||
s_ctrlport_resp_data[SAMP_W-1:0] <= reg_idle_value;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_TX_ERROR_POLICY: begin
|
||||
s_ctrlport_resp_data[TX_ERR_POLICY_LEN-1:0] <= reg_policy;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_TX_ERR_PORT: begin
|
||||
s_ctrlport_resp_data[9:0] <= reg_error_portid;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_TX_ERR_REM_PORT: begin
|
||||
s_ctrlport_resp_data[9:0] <= reg_error_rem_portid;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_TX_ERR_REM_EPID: begin
|
||||
s_ctrlport_resp_data[15:0] <= reg_error_rem_epid;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
REG_TX_ERR_ADDR: begin
|
||||
s_ctrlport_resp_data[19:0] <= reg_error_addr;
|
||||
s_ctrlport_resp_ack <= 1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Transmitter State Machine
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// FSM state values
|
||||
localparam ST_IDLE = 0;
|
||||
localparam ST_TIME_CHECK = 1;
|
||||
localparam ST_TRANSMIT = 2;
|
||||
localparam ST_POLICY_WAIT = 3;
|
||||
|
||||
reg [1:0] state = ST_IDLE;
|
||||
|
||||
reg sop = 1'b1; // Start of packet
|
||||
|
||||
reg [ERR_TX_CODE_W-1:0] new_error_code;
|
||||
reg [ 63:0] new_error_time;
|
||||
reg new_error_valid = 1'b0;
|
||||
|
||||
reg time_now, time_past;
|
||||
|
||||
|
||||
always @(posedge radio_clk) begin
|
||||
if (radio_rst) begin
|
||||
state <= ST_IDLE;
|
||||
sop <= 1'b1;
|
||||
new_error_valid <= 1'b0;
|
||||
end else begin
|
||||
new_error_valid <= 1'b0;
|
||||
|
||||
// Register time comparisons so they don't become the critical path
|
||||
time_now <= (radio_time == s_axis_ttimestamp);
|
||||
time_past <= (radio_time > s_axis_ttimestamp);
|
||||
|
||||
// Track if the next word will be the start of a packet (sop)
|
||||
if (s_axis_tvalid && s_axis_tready) begin
|
||||
sop <= s_axis_tlast;
|
||||
end
|
||||
|
||||
case (state)
|
||||
ST_IDLE : begin
|
||||
// Wait for a new packet to arrive and allow a cycle for the time
|
||||
// comparisons to update.
|
||||
if (s_axis_tvalid) begin
|
||||
state <= ST_TIME_CHECK;
|
||||
end
|
||||
end
|
||||
|
||||
ST_TIME_CHECK : begin
|
||||
if (!s_axis_thas_time || time_now) begin
|
||||
// We have a new packet without a timestamp, or a new packet
|
||||
// whose time has arrived.
|
||||
state <= ST_TRANSMIT;
|
||||
end else if (time_past) begin
|
||||
// We have a new packet with a timestamp, but the time has passed.
|
||||
//synthesis translate off
|
||||
$display("WARNING: radio_tx_core: Late data error");
|
||||
//synthesis translate_on
|
||||
new_error_code <= ERR_TX_LATE_DATA;
|
||||
new_error_time <= radio_time;
|
||||
new_error_valid <= 1'b1;
|
||||
state <= ST_POLICY_WAIT;
|
||||
end
|
||||
end
|
||||
|
||||
ST_TRANSMIT : begin
|
||||
if (radio_tx_stb) begin
|
||||
if (!s_axis_tvalid) begin
|
||||
// The radio strobed for new data but we don't have any to give
|
||||
//synthesis translate off
|
||||
$display("WARNING: radio_tx_core: Underrun error");
|
||||
//synthesis translate_on
|
||||
new_error_code <= ERR_TX_UNDERRUN;
|
||||
new_error_time <= radio_time;
|
||||
new_error_valid <= 1'b1;
|
||||
state <= ST_POLICY_WAIT;
|
||||
end else if (s_axis_tlast && s_axis_teob) begin
|
||||
// We're done with this burst of packets, so acknowledge EOB and
|
||||
// go back to idle.
|
||||
new_error_code <= ERR_TX_EOB_ACK;
|
||||
new_error_time <= radio_time;
|
||||
new_error_valid <= 1'b1;
|
||||
state <= ST_IDLE;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
ST_POLICY_WAIT : begin
|
||||
// If we came here from ST_TIME_CHECK or ST_TRANSMIT and we're in the
|
||||
// middle of a packet then we just wait until we reach the end of the
|
||||
// packet.
|
||||
if (s_axis_tvalid && s_axis_tlast) begin
|
||||
// We're either at the end of a packet or between packets
|
||||
if (reg_policy == TX_ERR_POLICY_PACKET ||
|
||||
(reg_policy == TX_ERR_POLICY_BURST && s_axis_teob)) begin
|
||||
state <= ST_IDLE;
|
||||
end
|
||||
|
||||
// If we came from ST_TRANSMIT and we happen to already be between
|
||||
// packets (i.e., we underflowed while waiting for the next packet).
|
||||
end else if (!s_axis_tvalid && sop) begin
|
||||
if (reg_policy == TX_ERR_POLICY_PACKET) state <= ST_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
default : state <= ST_IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// Output the current sample whenever we're transmitting and the sample is
|
||||
// valid. Otherwise, output the idle value.
|
||||
assign radio_tx_data = (s_axis_tvalid && state == ST_TRANSMIT) ?
|
||||
s_axis_tdata :
|
||||
{NSPC{reg_idle_value[SAMP_W-1:0]}};
|
||||
|
||||
// Read packet in the transmit state or dump it in the error state
|
||||
assign s_axis_tready = (radio_tx_stb && (state == ST_TRANSMIT)) ||
|
||||
(state == ST_POLICY_WAIT);
|
||||
|
||||
// Indicate whether Tx interface is actively transmitting
|
||||
assign radio_tx_running = (state == ST_TRANSMIT);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Error FIFO
|
||||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// This FIFO queues up errors in case we get multiple errors in a row faster
|
||||
// than they can be reported. If the FIFO fills then new errors will be
|
||||
// ignored.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// Error information
|
||||
wire [ERR_TX_CODE_W-1:0] next_error_code;
|
||||
wire [ 63:0] next_error_time;
|
||||
wire next_error_valid;
|
||||
reg next_error_ready = 1'b0;
|
||||
|
||||
wire new_error_ready;
|
||||
|
||||
axi_fifo_short #(
|
||||
.WIDTH (64 + ERR_TX_CODE_W)
|
||||
) error_fifo (
|
||||
.clk (radio_clk),
|
||||
.reset (radio_rst),
|
||||
.clear (1'b0),
|
||||
.i_tdata ({new_error_time, new_error_code}),
|
||||
.i_tvalid (new_error_valid & new_error_ready), // Mask with ready to prevent FIFO corruption
|
||||
.i_tready (new_error_ready),
|
||||
.o_tdata ({next_error_time, next_error_code}),
|
||||
.o_tvalid (next_error_valid),
|
||||
.o_tready (next_error_ready),
|
||||
.space (),
|
||||
.occupied ()
|
||||
);
|
||||
|
||||
//synthesis translate_off
|
||||
// Output a message if the error FIFO overflows
|
||||
always @(posedge radio_clk) begin
|
||||
if (new_error_valid && !new_error_ready) begin
|
||||
$display("WARNING: Tx error report dropped!");
|
||||
end
|
||||
end
|
||||
//synthesis translate_on
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Error Reporting State Machine
|
||||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// This state machine reports errors that have been queued up in the error
|
||||
// FIFO.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
localparam ST_ERR_IDLE = 0;
|
||||
localparam ST_ERR_CODE = 1;
|
||||
|
||||
reg [0:0] err_state = ST_ERR_IDLE;
|
||||
|
||||
// All ctrlport requests have a time
|
||||
assign m_ctrlport_req_has_time = 1'b1;
|
||||
|
||||
always @(posedge radio_clk) begin
|
||||
if (radio_rst) begin
|
||||
m_ctrlport_req_wr <= 1'b0;
|
||||
err_state <= ST_ERR_IDLE;
|
||||
next_error_ready <= 1'b0;
|
||||
end else begin
|
||||
m_ctrlport_req_wr <= 1'b0;
|
||||
next_error_ready <= 1'b0;
|
||||
|
||||
case (err_state)
|
||||
ST_ERR_IDLE : begin
|
||||
if (next_error_valid) begin
|
||||
// Setup write of error code
|
||||
m_ctrlport_req_wr <= 1'b1;
|
||||
m_ctrlport_req_addr <= reg_error_addr;
|
||||
m_ctrlport_req_data <= {{(32-ERR_TX_CODE_W){1'b0}}, next_error_code};
|
||||
m_ctrlport_req_time <= next_error_time;
|
||||
next_error_ready <= 1'b1;
|
||||
err_state <= ST_ERR_CODE;
|
||||
end
|
||||
end
|
||||
|
||||
ST_ERR_CODE : begin
|
||||
// Wait for write of error code and timestamp
|
||||
if (m_ctrlport_resp_ack) begin
|
||||
err_state <= ST_ERR_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
default : err_state <= ST_ERR_IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// Directly connect the port ID, remote port ID, remote EPID since they are
|
||||
// only used for error reporting.
|
||||
assign m_ctrlport_req_portid = reg_error_portid;
|
||||
assign m_ctrlport_req_rem_epid = reg_error_rem_epid;
|
||||
assign m_ctrlport_req_rem_portid = reg_error_rem_portid;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,546 @@
|
||||
//
|
||||
// Copyright 2019 Ettus Research, a National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: rfnoc_block_radio
|
||||
//
|
||||
// Description: This is the top-level file for the RFNoC radio block.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// THIS_PORTID : CTRL port ID to which this block is connected
|
||||
// CHDR_W : CHDR AXI-Stream data bus width
|
||||
// NIPC : Number of radio samples per radio clock cycle
|
||||
// ITEM_W : Radio sample width
|
||||
// NUM_PORTS : Number of radio channels (RX/TX pairs)
|
||||
// MTU : Maximum transmission unit (i.e., maximum packet size)
|
||||
// in CHDR words is 2**MTU.
|
||||
// CTRL_FIFO_SIZE : Size of the Control Port slave FIFO. This affects the
|
||||
// number of outstanding commands that can be pending.
|
||||
// PERIPH_BASE_ADDR : CTRL port peripheral window base address
|
||||
// PERIPH_ADDR_W : CTRL port peripheral address space = 2**PERIPH_ADDR_W
|
||||
//
|
||||
|
||||
|
||||
module rfnoc_block_radio #(
|
||||
parameter THIS_PORTID = 0,
|
||||
parameter CHDR_W = 64,
|
||||
parameter NIPC = 1,
|
||||
parameter ITEM_W = 32,
|
||||
parameter NUM_PORTS = 2,
|
||||
parameter MTU = 10,
|
||||
parameter CTRL_FIFO_SIZE = 9,
|
||||
parameter PERIPH_BASE_ADDR = 20'h80000,
|
||||
parameter PERIPH_ADDR_W = 19
|
||||
) (
|
||||
//---------------------------------------------------------------------------
|
||||
// AXIS CHDR Port
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
input wire rfnoc_chdr_clk,
|
||||
|
||||
// CHDR inputs from framework
|
||||
input wire [CHDR_W*NUM_PORTS-1:0] s_rfnoc_chdr_tdata,
|
||||
input wire [ NUM_PORTS-1:0] s_rfnoc_chdr_tlast,
|
||||
input wire [ NUM_PORTS-1:0] s_rfnoc_chdr_tvalid,
|
||||
output wire [ NUM_PORTS-1:0] s_rfnoc_chdr_tready,
|
||||
|
||||
// CHDR outputs to framework
|
||||
output wire [CHDR_W*NUM_PORTS-1:0] m_rfnoc_chdr_tdata,
|
||||
output wire [ NUM_PORTS-1:0] m_rfnoc_chdr_tlast,
|
||||
output wire [ NUM_PORTS-1:0] m_rfnoc_chdr_tvalid,
|
||||
input wire [ NUM_PORTS-1:0] m_rfnoc_chdr_tready,
|
||||
|
||||
// Backend interface
|
||||
input wire [511:0] rfnoc_core_config,
|
||||
output wire [511:0] rfnoc_core_status,
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// AXIS CTRL Port
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
input wire rfnoc_ctrl_clk,
|
||||
|
||||
// CTRL port requests from framework
|
||||
input wire [31:0] s_rfnoc_ctrl_tdata,
|
||||
input wire s_rfnoc_ctrl_tlast,
|
||||
input wire s_rfnoc_ctrl_tvalid,
|
||||
output wire s_rfnoc_ctrl_tready,
|
||||
|
||||
// CTRL port requests to framework
|
||||
output wire [31:0] m_rfnoc_ctrl_tdata,
|
||||
output wire m_rfnoc_ctrl_tlast,
|
||||
output wire m_rfnoc_ctrl_tvalid,
|
||||
input wire m_rfnoc_ctrl_tready,
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// CTRL Port Peripheral Interface
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
output wire m_ctrlport_req_wr,
|
||||
output wire m_ctrlport_req_rd,
|
||||
output wire [19:0] m_ctrlport_req_addr,
|
||||
output wire [31:0] m_ctrlport_req_data,
|
||||
output wire [ 3:0] m_ctrlport_req_byte_en,
|
||||
output wire m_ctrlport_req_has_time,
|
||||
output wire [63:0] m_ctrlport_req_time,
|
||||
input wire m_ctrlport_resp_ack,
|
||||
input wire [ 1:0] m_ctrlport_resp_status,
|
||||
input wire [31:0] m_ctrlport_resp_data,
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Radio Interface
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
input wire radio_clk,
|
||||
|
||||
// Timekeeper interface
|
||||
input wire [63:0] radio_time,
|
||||
|
||||
// Radio Rx interface
|
||||
input wire [(ITEM_W*NIPC)*NUM_PORTS-1:0] radio_rx_data,
|
||||
input wire [ NUM_PORTS-1:0] radio_rx_stb,
|
||||
output wire [ NUM_PORTS-1:0] radio_rx_running,
|
||||
|
||||
// Radio Tx interface
|
||||
output wire [(ITEM_W*NIPC)*NUM_PORTS-1:0] radio_tx_data,
|
||||
input wire [ NUM_PORTS-1:0] radio_tx_stb,
|
||||
output wire [ NUM_PORTS-1:0] radio_tx_running
|
||||
);
|
||||
|
||||
`include "rfnoc_block_radio_regs.vh"
|
||||
`include "../../core/rfnoc_axis_ctrl_utils.vh"
|
||||
|
||||
localparam NOC_ID = 32'h12AD1000;
|
||||
localparam RADIO_W = NIPC*ITEM_W;
|
||||
|
||||
|
||||
// Radio Tx data stream
|
||||
wire [RADIO_W*NUM_PORTS-1:0] axis_tx_tdata;
|
||||
wire [ NUM_PORTS-1:0] axis_tx_tlast;
|
||||
wire [ NUM_PORTS-1:0] axis_tx_tvalid;
|
||||
wire [ NUM_PORTS-1:0] axis_tx_tready;
|
||||
wire [ 64*NUM_PORTS-1:0] axis_tx_ttimestamp;
|
||||
wire [ NUM_PORTS-1:0] axis_tx_thas_time;
|
||||
wire [ NUM_PORTS-1:0] axis_tx_teob;
|
||||
|
||||
// Radio Rx data stream
|
||||
wire [RADIO_W*NUM_PORTS-1:0] axis_rx_tdata;
|
||||
wire [ NUM_PORTS-1:0] axis_rx_tlast;
|
||||
wire [ NUM_PORTS-1:0] axis_rx_tvalid;
|
||||
wire [ NUM_PORTS-1:0] axis_rx_tready;
|
||||
wire [ 64*NUM_PORTS-1:0] axis_rx_ttimestamp;
|
||||
wire [ NUM_PORTS-1:0] axis_rx_thas_time;
|
||||
wire [ NUM_PORTS-1:0] axis_rx_teob;
|
||||
|
||||
// Control port signals used for register access (NoC shell masters user logic)
|
||||
wire ctrlport_reg_req_wr;
|
||||
wire ctrlport_reg_req_rd;
|
||||
wire [19:0] ctrlport_reg_req_addr;
|
||||
wire ctrlport_reg_has_time;
|
||||
wire [63:0] ctrlport_reg_time;
|
||||
wire [31:0] ctrlport_reg_req_data;
|
||||
wire [31:0] ctrlport_reg_resp_data;
|
||||
wire ctrlport_reg_resp_ack;
|
||||
|
||||
// Control port signals used for error reporting (user logic masters to NoC shell)
|
||||
wire ctrlport_err_req_wr;
|
||||
wire [19:0] ctrlport_err_req_addr;
|
||||
wire [ 9:0] ctrlport_err_req_portid;
|
||||
wire [15:0] ctrlport_err_req_rem_epid;
|
||||
wire [ 9:0] ctrlport_err_req_rem_portid;
|
||||
wire [31:0] ctrlport_err_req_data;
|
||||
wire ctrlport_err_req_has_time;
|
||||
wire [63:0] ctrlport_err_req_time;
|
||||
wire ctrlport_err_resp_ack;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// NoC Shell
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
wire rfnoc_chdr_rst;
|
||||
wire radio_rst;
|
||||
|
||||
noc_shell_radio #(
|
||||
.NOC_ID (NOC_ID),
|
||||
.THIS_PORTID (THIS_PORTID),
|
||||
.CHDR_W (CHDR_W),
|
||||
.CTRLPORT_SLV_EN (1),
|
||||
.CTRLPORT_MST_EN (1),
|
||||
.CTRL_FIFO_SIZE (CTRL_FIFO_SIZE),
|
||||
.NUM_DATA_I (NUM_PORTS),
|
||||
.NUM_DATA_O (NUM_PORTS),
|
||||
.ITEM_W (ITEM_W),
|
||||
.NIPC (NIPC),
|
||||
.PYLD_FIFO_SIZE (MTU),
|
||||
.MTU (MTU)
|
||||
) noc_shell_radio_i (
|
||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||
.rfnoc_ctrl_rst (),
|
||||
.rfnoc_core_config (rfnoc_core_config),
|
||||
.rfnoc_core_status (rfnoc_core_status),
|
||||
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
|
||||
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
|
||||
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
|
||||
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
|
||||
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
|
||||
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
|
||||
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
|
||||
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
|
||||
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
||||
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
||||
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
||||
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
||||
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
||||
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
||||
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
||||
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
||||
.ctrlport_clk (radio_clk),
|
||||
.ctrlport_rst (radio_rst),
|
||||
.m_ctrlport_req_wr (ctrlport_reg_req_wr),
|
||||
.m_ctrlport_req_rd (ctrlport_reg_req_rd),
|
||||
.m_ctrlport_req_addr (ctrlport_reg_req_addr),
|
||||
.m_ctrlport_req_data (ctrlport_reg_req_data),
|
||||
.m_ctrlport_req_byte_en (),
|
||||
.m_ctrlport_req_has_time (ctrlport_reg_has_time),
|
||||
.m_ctrlport_req_time (ctrlport_reg_time),
|
||||
.m_ctrlport_resp_ack (ctrlport_reg_resp_ack),
|
||||
.m_ctrlport_resp_status (AXIS_CTRL_STS_OKAY),
|
||||
.m_ctrlport_resp_data (ctrlport_reg_resp_data),
|
||||
.s_ctrlport_req_wr (ctrlport_err_req_wr),
|
||||
.s_ctrlport_req_rd (1'b0),
|
||||
.s_ctrlport_req_addr (ctrlport_err_req_addr),
|
||||
.s_ctrlport_req_portid (ctrlport_err_req_portid),
|
||||
.s_ctrlport_req_rem_epid (ctrlport_err_req_rem_epid),
|
||||
.s_ctrlport_req_rem_portid (ctrlport_err_req_rem_portid),
|
||||
.s_ctrlport_req_data (ctrlport_err_req_data),
|
||||
.s_ctrlport_req_byte_en (4'hF),
|
||||
.s_ctrlport_req_has_time (ctrlport_err_req_has_time),
|
||||
.s_ctrlport_req_time (ctrlport_err_req_time),
|
||||
.s_ctrlport_resp_ack (ctrlport_err_resp_ack),
|
||||
.s_ctrlport_resp_status (),
|
||||
.s_ctrlport_resp_data (),
|
||||
.axis_data_clk (radio_clk),
|
||||
.axis_data_rst (radio_rst),
|
||||
.m_axis_tdata (axis_tx_tdata),
|
||||
.m_axis_tkeep (), // Radio only transmits full words
|
||||
.m_axis_tlast (axis_tx_tlast),
|
||||
.m_axis_tvalid (axis_tx_tvalid),
|
||||
.m_axis_tready (axis_tx_tready),
|
||||
.m_axis_ttimestamp (axis_tx_ttimestamp),
|
||||
.m_axis_thas_time (axis_tx_thas_time),
|
||||
.m_axis_teov (),
|
||||
.m_axis_teob (axis_tx_teob),
|
||||
.s_axis_tdata (axis_rx_tdata),
|
||||
.s_axis_tkeep ({NUM_PORTS*NIPC{1'b1}}), // Radio only receives full words
|
||||
.s_axis_tlast (axis_rx_tlast),
|
||||
.s_axis_tvalid (axis_rx_tvalid),
|
||||
.s_axis_tready (axis_rx_tready),
|
||||
.s_axis_ttimestamp (axis_rx_ttimestamp),
|
||||
.s_axis_thas_time (axis_rx_thas_time),
|
||||
.s_axis_teov ({NUM_PORTS{1'b0}}),
|
||||
.s_axis_teob (axis_rx_teob)
|
||||
);
|
||||
|
||||
// Cross the CHDR reset to the radio_clk domain
|
||||
pulse_synchronizer #(
|
||||
.MODE ("POSEDGE")
|
||||
) ctrl_rst_sync_i (
|
||||
.clk_a (rfnoc_chdr_clk),
|
||||
.rst_a (1'b0),
|
||||
.pulse_a (rfnoc_chdr_rst),
|
||||
.busy_a (),
|
||||
.clk_b (radio_clk),
|
||||
.pulse_b (radio_rst)
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Decode Control Port Addresses
|
||||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// This block splits the NoC shell's single master control port interface
|
||||
// into three masters, connected to the shared registers, radio cores, and
|
||||
// the external CTRL port peripheral interface. The responses from each of
|
||||
// these are merged into a single response and sent back to the NoC shell.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
wire ctrlport_shared_req_wr;
|
||||
wire ctrlport_shared_req_rd;
|
||||
wire [19:0] ctrlport_shared_req_addr;
|
||||
wire [31:0] ctrlport_shared_req_data;
|
||||
wire [ 3:0] ctrlport_shared_req_byte_en;
|
||||
wire ctrlport_shared_req_has_time;
|
||||
wire [63:0] ctrlport_shared_req_time;
|
||||
reg ctrlport_shared_resp_ack = 1'b0;
|
||||
reg [31:0] ctrlport_shared_resp_data = 0;
|
||||
|
||||
wire ctrlport_core_req_wr;
|
||||
wire ctrlport_core_req_rd;
|
||||
wire [19:0] ctrlport_core_req_addr;
|
||||
wire [31:0] ctrlport_core_req_data;
|
||||
wire [ 3:0] ctrlport_core_req_byte_en;
|
||||
wire ctrlport_core_req_has_time;
|
||||
wire [63:0] ctrlport_core_req_time;
|
||||
wire ctrlport_core_resp_ack;
|
||||
wire [31:0] ctrlport_core_resp_data;
|
||||
|
||||
ctrlport_decoder_param #(
|
||||
.NUM_SLAVES (3),
|
||||
.PORT_BASE ({PERIPH_BASE_ADDR, RADIO_BASE_ADDR, SHARED_BASE_ADDR}),
|
||||
.PORT_ADDR_W({PERIPH_ADDR_W, RADIO_ADDR_W + $clog2(NUM_PORTS), SHARED_ADDR_W})
|
||||
) ctrlport_decoder_param_i (
|
||||
.ctrlport_clk (radio_clk),
|
||||
.ctrlport_rst (radio_rst),
|
||||
.s_ctrlport_req_wr (ctrlport_reg_req_wr),
|
||||
.s_ctrlport_req_rd (ctrlport_reg_req_rd),
|
||||
.s_ctrlport_req_addr (ctrlport_reg_req_addr),
|
||||
.s_ctrlport_req_data (ctrlport_reg_req_data),
|
||||
.s_ctrlport_req_byte_en (4'b0),
|
||||
.s_ctrlport_req_has_time (ctrlport_reg_has_time),
|
||||
.s_ctrlport_req_time (ctrlport_reg_time),
|
||||
.s_ctrlport_resp_ack (ctrlport_reg_resp_ack),
|
||||
.s_ctrlport_resp_status (),
|
||||
.s_ctrlport_resp_data (ctrlport_reg_resp_data),
|
||||
.m_ctrlport_req_wr ({m_ctrlport_req_wr,
|
||||
ctrlport_core_req_wr,
|
||||
ctrlport_shared_req_wr}),
|
||||
.m_ctrlport_req_rd ({m_ctrlport_req_rd,
|
||||
ctrlport_core_req_rd,
|
||||
ctrlport_shared_req_rd}),
|
||||
.m_ctrlport_req_addr ({m_ctrlport_req_addr,
|
||||
ctrlport_core_req_addr,
|
||||
ctrlport_shared_req_addr}),
|
||||
.m_ctrlport_req_data ({m_ctrlport_req_data,
|
||||
ctrlport_core_req_data,
|
||||
ctrlport_shared_req_data}),
|
||||
.m_ctrlport_req_byte_en ({m_ctrlport_req_byte_en,
|
||||
ctrlport_core_req_byte_en,
|
||||
ctrlport_shared_req_byte_en}),
|
||||
.m_ctrlport_req_has_time ({m_ctrlport_req_has_time,
|
||||
ctrlport_core_req_has_time,
|
||||
ctrlport_shared_req_has_time}),
|
||||
.m_ctrlport_req_time ({m_ctrlport_req_time,
|
||||
ctrlport_core_req_time,
|
||||
ctrlport_shared_req_time}),
|
||||
.m_ctrlport_resp_ack ({m_ctrlport_resp_ack,
|
||||
ctrlport_core_resp_ack,
|
||||
ctrlport_shared_resp_ack}),
|
||||
.m_ctrlport_resp_status ({m_ctrlport_resp_status,
|
||||
2'b00,
|
||||
2'b00}),
|
||||
.m_ctrlport_resp_data ({m_ctrlport_resp_data,
|
||||
ctrlport_core_resp_data,
|
||||
ctrlport_shared_resp_data
|
||||
})
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Split Radio Control Port Interfaces
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
wire [ NUM_PORTS-1:0] ctrlport_radios_req_wr;
|
||||
wire [ NUM_PORTS-1:0] ctrlport_radios_req_rd;
|
||||
wire [20*NUM_PORTS-1:0] ctrlport_radios_req_addr;
|
||||
wire [32*NUM_PORTS-1:0] ctrlport_radios_req_data;
|
||||
wire [ NUM_PORTS-1:0] ctrlport_radios_resp_ack;
|
||||
wire [32*NUM_PORTS-1:0] ctrlport_radios_resp_data;
|
||||
|
||||
ctrlport_decoder #(
|
||||
.NUM_SLAVES (NUM_PORTS),
|
||||
.BASE_ADDR (0),
|
||||
.SLAVE_ADDR_W (RADIO_ADDR_W)
|
||||
) ctrlport_decoder_i (
|
||||
.ctrlport_clk (radio_clk),
|
||||
.ctrlport_rst (radio_rst),
|
||||
.s_ctrlport_req_wr (ctrlport_core_req_wr),
|
||||
.s_ctrlport_req_rd (ctrlport_core_req_rd),
|
||||
.s_ctrlport_req_addr (ctrlport_core_req_addr),
|
||||
.s_ctrlport_req_data (ctrlport_core_req_data),
|
||||
.s_ctrlport_req_byte_en (4'b0),
|
||||
.s_ctrlport_req_has_time (1'b0),
|
||||
.s_ctrlport_req_time (64'b0),
|
||||
.s_ctrlport_resp_ack (ctrlport_core_resp_ack),
|
||||
.s_ctrlport_resp_status (),
|
||||
.s_ctrlport_resp_data (ctrlport_core_resp_data),
|
||||
.m_ctrlport_req_wr (ctrlport_radios_req_wr),
|
||||
.m_ctrlport_req_rd (ctrlport_radios_req_rd),
|
||||
.m_ctrlport_req_addr (ctrlport_radios_req_addr),
|
||||
.m_ctrlport_req_data (ctrlport_radios_req_data),
|
||||
.m_ctrlport_req_byte_en (),
|
||||
.m_ctrlport_req_has_time (),
|
||||
.m_ctrlport_req_time (),
|
||||
.m_ctrlport_resp_ack (ctrlport_radios_resp_ack),
|
||||
.m_ctrlport_resp_status ({NUM_PORTS{2'b00}}),
|
||||
.m_ctrlport_resp_data (ctrlport_radios_resp_data)
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Merge Control Port Interfaces
|
||||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// This block merges the master control port interfaces of all radio_cores
|
||||
// into a single master for the NoC shell.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
wire [ NUM_PORTS-1:0] ctrlport_err_radio_req_wr;
|
||||
wire [20*NUM_PORTS-1:0] ctrlport_err_radio_req_addr;
|
||||
wire [10*NUM_PORTS-1:0] ctrlport_err_radio_req_portid;
|
||||
wire [16*NUM_PORTS-1:0] ctrlport_err_radio_req_rem_epid;
|
||||
wire [10*NUM_PORTS-1:0] ctrlport_err_radio_req_rem_portid;
|
||||
wire [32*NUM_PORTS-1:0] ctrlport_err_radio_req_data;
|
||||
wire [ NUM_PORTS-1:0] ctrlport_err_radio_req_has_time;
|
||||
wire [64*NUM_PORTS-1:0] ctrlport_err_radio_req_time;
|
||||
wire [ NUM_PORTS-1:0] ctrlport_err_radio_resp_ack;
|
||||
|
||||
ctrlport_combiner #(
|
||||
.NUM_MASTERS (NUM_PORTS),
|
||||
.PRIORITY (0)
|
||||
) ctrlport_combiner_i (
|
||||
.ctrlport_clk (radio_clk),
|
||||
.ctrlport_rst (radio_rst),
|
||||
.s_ctrlport_req_wr (ctrlport_err_radio_req_wr),
|
||||
.s_ctrlport_req_rd ({NUM_PORTS{1'b0}}),
|
||||
.s_ctrlport_req_addr (ctrlport_err_radio_req_addr),
|
||||
.s_ctrlport_req_portid (ctrlport_err_radio_req_portid),
|
||||
.s_ctrlport_req_rem_epid (ctrlport_err_radio_req_rem_epid),
|
||||
.s_ctrlport_req_rem_portid (ctrlport_err_radio_req_rem_portid),
|
||||
.s_ctrlport_req_data (ctrlport_err_radio_req_data),
|
||||
.s_ctrlport_req_byte_en ({4*NUM_PORTS{1'b1}}),
|
||||
.s_ctrlport_req_has_time (ctrlport_err_radio_req_has_time),
|
||||
.s_ctrlport_req_time (ctrlport_err_radio_req_time),
|
||||
.s_ctrlport_resp_ack (ctrlport_err_radio_resp_ack),
|
||||
.s_ctrlport_resp_status (),
|
||||
.s_ctrlport_resp_data (),
|
||||
.m_ctrlport_req_wr (ctrlport_err_req_wr),
|
||||
.m_ctrlport_req_rd (),
|
||||
.m_ctrlport_req_addr (ctrlport_err_req_addr),
|
||||
.m_ctrlport_req_portid (ctrlport_err_req_portid),
|
||||
.m_ctrlport_req_rem_epid (ctrlport_err_req_rem_epid),
|
||||
.m_ctrlport_req_rem_portid (ctrlport_err_req_rem_portid),
|
||||
.m_ctrlport_req_data (ctrlport_err_req_data),
|
||||
.m_ctrlport_req_byte_en (),
|
||||
.m_ctrlport_req_has_time (ctrlport_err_req_has_time),
|
||||
.m_ctrlport_req_time (ctrlport_err_req_time),
|
||||
.m_ctrlport_resp_ack (ctrlport_err_resp_ack),
|
||||
.m_ctrlport_resp_status (2'b0),
|
||||
.m_ctrlport_resp_data (32'b0)
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Shared Registers
|
||||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// These registers are shared by all radio channels.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
localparam [15:0] compat_major = 16'd0;
|
||||
localparam [15:0] compat_minor = 16'd0;
|
||||
|
||||
always @(posedge radio_clk) begin
|
||||
if (radio_rst) begin
|
||||
ctrlport_shared_resp_ack <= 0;
|
||||
ctrlport_shared_resp_data <= 0;
|
||||
end else begin
|
||||
// Default assignments
|
||||
ctrlport_shared_resp_ack <= 0;
|
||||
ctrlport_shared_resp_data <= 0;
|
||||
|
||||
// Handle register reads
|
||||
if (ctrlport_shared_req_rd) begin
|
||||
case (ctrlport_shared_req_addr)
|
||||
REG_COMPAT_NUM: begin
|
||||
ctrlport_shared_resp_ack <= 1;
|
||||
ctrlport_shared_resp_data <= { compat_major, compat_minor };
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Radio Cores
|
||||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// This generate block instantiates one radio core for each channel that is
|
||||
// requested by NUM_PORTS.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < NUM_PORTS; i = i+1) begin : radio_core_gen
|
||||
|
||||
// The radio core contains all the logic related to a single radio channel.
|
||||
radio_core #(
|
||||
.SAMP_W (ITEM_W),
|
||||
.NSPC (NIPC)
|
||||
) radio_core_i (
|
||||
.radio_clk (radio_clk),
|
||||
.radio_rst (radio_rst),
|
||||
|
||||
// Slave Control Port (Register Access)
|
||||
.s_ctrlport_req_wr (ctrlport_radios_req_wr[i]),
|
||||
.s_ctrlport_req_rd (ctrlport_radios_req_rd[i]),
|
||||
.s_ctrlport_req_addr (ctrlport_radios_req_addr[i*20 +: 20]),
|
||||
.s_ctrlport_req_data (ctrlport_radios_req_data[i*32 +: 32]),
|
||||
.s_ctrlport_resp_ack (ctrlport_radios_resp_ack[i]),
|
||||
.s_ctrlport_resp_data (ctrlport_radios_resp_data[i*32 +: 32]),
|
||||
|
||||
// Master Control Port (Error Reporting)
|
||||
.m_ctrlport_req_wr (ctrlport_err_radio_req_wr[i]),
|
||||
.m_ctrlport_req_addr (ctrlport_err_radio_req_addr[i*20 +: 20]),
|
||||
.m_ctrlport_req_portid (ctrlport_err_radio_req_portid[i*10 +: 10]),
|
||||
.m_ctrlport_req_rem_epid (ctrlport_err_radio_req_rem_epid[i*16 +: 16]),
|
||||
.m_ctrlport_req_rem_portid (ctrlport_err_radio_req_rem_portid[i*10 +: 10]),
|
||||
.m_ctrlport_req_data (ctrlport_err_radio_req_data[i*32 +: 32]),
|
||||
.m_ctrlport_req_has_time (ctrlport_err_radio_req_has_time[i]),
|
||||
.m_ctrlport_req_time (ctrlport_err_radio_req_time[i*64 +: 64]),
|
||||
.m_ctrlport_resp_ack (ctrlport_err_radio_resp_ack[i]),
|
||||
|
||||
// Tx Data Stream
|
||||
.s_axis_tdata (axis_tx_tdata[RADIO_W*i +: RADIO_W]),
|
||||
.s_axis_tlast (axis_tx_tlast[i]),
|
||||
.s_axis_tvalid (axis_tx_tvalid[i]),
|
||||
.s_axis_tready (axis_tx_tready[i]),
|
||||
// Sideband Info
|
||||
.s_axis_ttimestamp (axis_tx_ttimestamp[i*64 +: 64]),
|
||||
.s_axis_thas_time (axis_tx_thas_time[i]),
|
||||
.s_axis_teob (axis_tx_teob[i]),
|
||||
|
||||
// Rx Data Stream
|
||||
.m_axis_tdata (axis_rx_tdata[RADIO_W*i +: RADIO_W]),
|
||||
.m_axis_tlast (axis_rx_tlast[i]),
|
||||
.m_axis_tvalid (axis_rx_tvalid[i]),
|
||||
.m_axis_tready (axis_rx_tready[i]),
|
||||
// Sideband Info
|
||||
.m_axis_ttimestamp (axis_rx_ttimestamp[i*64 +: 64]),
|
||||
.m_axis_thas_time (axis_rx_thas_time[i]),
|
||||
.m_axis_teob (axis_rx_teob[i]),
|
||||
|
||||
// Radio Data
|
||||
.radio_time (radio_time),
|
||||
.radio_rx_data (radio_rx_data[(RADIO_W)*i +: (RADIO_W)]),
|
||||
.radio_rx_stb (radio_rx_stb[i]),
|
||||
.radio_rx_running (radio_rx_running[i]),
|
||||
.radio_tx_data (radio_tx_data[(RADIO_W)*i +: (RADIO_W)]),
|
||||
.radio_tx_stb (radio_tx_stb[i]),
|
||||
.radio_tx_running (radio_tx_running[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
@@ -0,0 +1,68 @@
|
||||
//
|
||||
// Copyright 2019 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: rfnoc_block_radio_all_tb
|
||||
//
|
||||
// Description: This is the testbench for rfnoc_block_radio that instantiates
|
||||
// several variations of rfnoc_block_radio_tb to test different configurations.
|
||||
//
|
||||
|
||||
|
||||
module rfnoc_block_radio_all_tb;
|
||||
|
||||
timeunit 1ns;
|
||||
timeprecision 1ps;
|
||||
|
||||
import PkgTestExec::*;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Test Definitions
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
typedef struct {
|
||||
int CHDR_W;
|
||||
int ITEM_W;
|
||||
int NIPC;
|
||||
int NUM_PORTS;
|
||||
int STALL_PROB;
|
||||
int STB_PROB;
|
||||
bit TEST_REGS;
|
||||
} test_config_t;
|
||||
|
||||
localparam NUM_TESTS = 9;
|
||||
|
||||
localparam test_config_t test[NUM_TESTS] = '{
|
||||
'{CHDR_W: 64, ITEM_W: 16, NIPC: 1, NUM_PORTS: 3, STALL_PROB: 10, STB_PROB: 100, TEST_REGS: 1 },
|
||||
'{CHDR_W: 64, ITEM_W: 16, NIPC: 1, NUM_PORTS: 2, STALL_PROB: 25, STB_PROB: 80, TEST_REGS: 1 },
|
||||
'{CHDR_W: 64, ITEM_W: 16, NIPC: 2, NUM_PORTS: 1, STALL_PROB: 25, STB_PROB: 80, TEST_REGS: 0 },
|
||||
'{CHDR_W: 64, ITEM_W: 32, NIPC: 1, NUM_PORTS: 1, STALL_PROB: 25, STB_PROB: 80, TEST_REGS: 0 },
|
||||
'{CHDR_W: 64, ITEM_W: 32, NIPC: 2, NUM_PORTS: 1, STALL_PROB: 10, STB_PROB: 80, TEST_REGS: 0 },
|
||||
'{CHDR_W: 128, ITEM_W: 32, NIPC: 1, NUM_PORTS: 3, STALL_PROB: 10, STB_PROB: 100, TEST_REGS: 1 },
|
||||
'{CHDR_W: 128, ITEM_W: 32, NIPC: 1, NUM_PORTS: 2, STALL_PROB: 25, STB_PROB: 80, TEST_REGS: 0 },
|
||||
'{CHDR_W: 128, ITEM_W: 32, NIPC: 2, NUM_PORTS: 1, STALL_PROB: 25, STB_PROB: 80, TEST_REGS: 0 },
|
||||
'{CHDR_W: 128, ITEM_W: 32, NIPC: 4, NUM_PORTS: 1, STALL_PROB: 10, STB_PROB: 80, TEST_REGS: 0 }
|
||||
};
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// DUT Instances
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
genvar i;
|
||||
for (i = 0; i < NUM_TESTS; i++) begin : gen_test_config
|
||||
rfnoc_block_radio_tb #(
|
||||
.CHDR_W (test[i].CHDR_W ),
|
||||
.ITEM_W (test[i].ITEM_W ),
|
||||
.NIPC (test[i].NIPC ),
|
||||
.NUM_PORTS (test[i].NUM_PORTS ),
|
||||
.STALL_PROB (test[i].STALL_PROB),
|
||||
.STB_PROB (test[i].STB_PROB ),
|
||||
.TEST_REGS (test[i].TEST_REGS )
|
||||
) rfnoc_block_radio_tb_i ();
|
||||
end : gen_test_config
|
||||
|
||||
|
||||
endmodule : rfnoc_block_radio_all_tb
|
||||
@@ -0,0 +1,125 @@
|
||||
//
|
||||
// Copyright 2019 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: rfnoc_block_radio_regs (Header)
|
||||
//
|
||||
// Description: Header file for RFNoC radio functionality. This includes
|
||||
// register offsets, bitfields and constants for the radio components.
|
||||
//
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Shared Register Offsets (One Set Per Radio NoC Block)
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
localparam SHARED_BASE_ADDR = 20'h00; // Base address for shared radio registers
|
||||
localparam SHARED_ADDR_W = 4; // Address space size for shared registers
|
||||
|
||||
localparam REG_COMPAT_NUM = 'h00; // Compatibility number register offset
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Radio Core Register Offsets (One Set Per Radio Port)
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// These registers are replicated depending on the number of radio channels
|
||||
// requested. They start at BASE_ADDR_RADIO and repeat every RADIO_ADDR_SPACE
|
||||
// bytes.
|
||||
//
|
||||
// WARNING: All registers larger than a single 32-bit word must be read and
|
||||
// written least significant word first to guarantee coherency.
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
localparam RADIO_BASE_ADDR = 20'h1000; // Base address of first radio. Choose a
|
||||
// nice big power of 2 so we can just pass
|
||||
// the lower bits to the radio cores.
|
||||
localparam RADIO_ADDR_W = 7; // Address space size per radio
|
||||
|
||||
// General Radio Registers
|
||||
localparam REG_LOOPBACK_EN = 'h00; // Loopback enable (connect Tx output to Rx input)
|
||||
localparam REG_RADIO_WIDTH = 'h04; // Upper 16 bits is sample width, lower 16 bits is NSPC
|
||||
|
||||
// RX Control Registers
|
||||
localparam REG_RX_STATUS = 'h10; // Status of Rx radio
|
||||
localparam REG_RX_CMD = 'h14; // The next radio command to execute
|
||||
localparam REG_RX_CMD_NUM_WORDS_LO = 'h18; // Number of radio words for the next command (low word)
|
||||
localparam REG_RX_CMD_NUM_WORDS_HI = 'h1C; // Number of radio words for the next command (high word)
|
||||
localparam REG_RX_CMD_TIME_LO = 'h20; // Time for the next command (low word)
|
||||
localparam REG_RX_CMD_TIME_HI = 'h24; // Time for the next command (high word)
|
||||
localparam REG_RX_MAX_WORDS_PER_PKT = 'h28; // Maximum packet length to build from Rx data
|
||||
localparam REG_RX_ERR_PORT = 'h2C; // Port ID for error reporting
|
||||
localparam REG_RX_ERR_REM_PORT = 'h30; // Remote port ID for error reporting
|
||||
localparam REG_RX_ERR_REM_EPID = 'h34; // Remote EPID (endpoint ID) for error reporting
|
||||
localparam REG_RX_ERR_ADDR = 'h38; // Offset to write error code to
|
||||
localparam REG_RX_DATA = 'h3C; // Read the current Rx output of the radio
|
||||
localparam REG_RX_HAS_TIME = 'h70; // Controls whether or not a channel has timestamps
|
||||
|
||||
// TX Control Registers
|
||||
localparam REG_TX_IDLE_VALUE = 'h40; // Value to output when transmitter is idle
|
||||
localparam REG_TX_ERROR_POLICY = 'h44; // Tx error policy
|
||||
localparam REG_TX_ERR_PORT = 'h48; // Port ID for error reporting
|
||||
localparam REG_TX_ERR_REM_PORT = 'h4C; // Remote port ID for error reporting
|
||||
localparam REG_TX_ERR_REM_EPID = 'h50; // Remote EPID (endpoint ID) for error reporting
|
||||
localparam REG_TX_ERR_ADDR = 'h54; // Offset to write error code to
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Register Bit Fields
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
// REG_RX_CMD bit fields
|
||||
localparam RX_CMD_POS = 0; // Location of the command bit field
|
||||
localparam RX_CMD_LEN = 2; // Bit length of the command bit field
|
||||
localparam RX_CMD_TIMED_POS = 31; // Location of the bit indicating if this is
|
||||
// a timed command or not.
|
||||
|
||||
// REG_RX_CMD_NUM_WORDS_HI/LO length field
|
||||
localparam RX_CMD_NUM_WORDS_LEN = 48; // Number of bits that are used in the 64-bit
|
||||
// NUM_WORDS register (must be in range [33:64]).
|
||||
|
||||
// REG_RX_STATUS bit fields
|
||||
localparam CMD_FIFO_SPACE_POS = 0; // Indicates if radio is busy executing a command.
|
||||
localparam CMD_FIFO_SPACE_LEN = 6; // Length of the FIFO_SPACE field
|
||||
localparam CMD_FIFO_SPACE_MAX = 32; // Size of command FIFO
|
||||
|
||||
// REG_TX_ERROR_POLICY bit fields
|
||||
localparam TX_ERR_POLICY_LEN = 2; // Length of error policy bit field
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Rx Radio Commands
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
localparam [RX_CMD_LEN-1:0] RX_CMD_STOP = 0; // Stop acquiring at end of next packet
|
||||
localparam [RX_CMD_LEN-1:0] RX_CMD_FINITE = 1; // Acquire NUM_SAMPS then stop
|
||||
localparam [RX_CMD_LEN-1:0] RX_CMD_CONTINUOUS = 2; // Acquire until stopped
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Tx Error Policies
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
localparam TX_ERR_POLICY_PACKET = 1; // Wait for end of packet after error
|
||||
localparam TX_ERR_POLICY_BURST = 2; // Wait for end of burst after error
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Error Codes
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
// Rx Error Codes
|
||||
localparam ERR_RX_CODE_W = 2; // Bit width of error code values
|
||||
//
|
||||
localparam ERR_RX_LATE_CMD = 1; // Late command (arrived after indicated time)
|
||||
localparam ERR_RX_OVERRUN = 2; // FIFO overflow
|
||||
|
||||
|
||||
// Tx Error Codes
|
||||
localparam ERR_TX_CODE_W = 2; // Bit width of error code values
|
||||
//
|
||||
localparam ERR_TX_UNDERRUN = 1; // Data underflow (data not available when needed)
|
||||
localparam ERR_TX_LATE_DATA = 2; // Late data (arrived after indicated time)
|
||||
localparam ERR_TX_EOB_ACK = 3; // Acknowledge end-of-burst (this is not an error)
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,246 @@
|
||||
//
|
||||
// Copyright 2015 Ettus Research LLC
|
||||
// Copyright 2018 Ettus Research, a National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
|
||||
module rx_frontend_gen3 #(
|
||||
parameter SR_MAG_CORRECTION = 0,
|
||||
parameter SR_PHASE_CORRECTION = 1,
|
||||
parameter SR_OFFSET_I = 2,
|
||||
parameter SR_OFFSET_Q = 3,
|
||||
parameter SR_IQ_MAPPING = 4,
|
||||
parameter SR_HET_PHASE_INCR = 5,
|
||||
parameter BYPASS_DC_OFFSET_CORR = 0,
|
||||
parameter BYPASS_IQ_COMP = 0,
|
||||
parameter BYPASS_REALMODE_DSP = 0,
|
||||
parameter DEVICE = "7SERIES"
|
||||
)(
|
||||
input clk, input reset, input sync_in,
|
||||
input set_stb, input [7:0] set_addr, input [31:0] set_data,
|
||||
input adc_stb, input [15:0] adc_i, input [15:0] adc_q,
|
||||
output rx_stb, output [15:0] rx_i, output [15:0] rx_q
|
||||
);
|
||||
|
||||
wire realmode;
|
||||
wire swap_iq;
|
||||
wire invert_i;
|
||||
wire invert_q;
|
||||
wire realmode_decim;
|
||||
wire bypass_all;
|
||||
wire [1:0] iq_map_reserved;
|
||||
wire [17:0] mag_corr, phase_corr;
|
||||
wire phase_dir;
|
||||
wire phase_sync;
|
||||
|
||||
reg [23:0] adc_i_mux, adc_q_mux;
|
||||
reg adc_mux_stb;
|
||||
wire [23:0] adc_i_ofs, adc_q_ofs, adc_i_comp, adc_q_comp;
|
||||
reg [23:0] adc_i_ofs_dly, adc_q_ofs_dly;
|
||||
wire adc_ofs_stb, adc_comp_stb;
|
||||
reg [1:0] adc_ofs_stb_dly;
|
||||
wire [23:0] adc_i_dsp, adc_q_dsp;
|
||||
wire adc_dsp_stb;
|
||||
wire [35:0] corr_i, corr_q;
|
||||
wire [15:0] rx_i_out, rx_q_out;
|
||||
|
||||
/********************************************************
|
||||
** Settings Bus Registers
|
||||
********************************************************/
|
||||
setting_reg #(.my_addr(SR_MAG_CORRECTION),.width(18)) sr_mag_corr (
|
||||
.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
|
||||
.in(set_data),.out(mag_corr),.changed());
|
||||
|
||||
setting_reg #(.my_addr(SR_PHASE_CORRECTION),.width(18)) sr_phase_corr (
|
||||
.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
|
||||
.in(set_data),.out(phase_corr),.changed());
|
||||
|
||||
setting_reg #(.my_addr(SR_IQ_MAPPING), .width(8)) sr_mux_sel (
|
||||
.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
|
||||
.in(set_data),.out({bypass_all,iq_map_reserved,realmode_decim,invert_i,invert_q,realmode,swap_iq}),.changed());
|
||||
|
||||
// Setting reg: 1 bit to set phase direction: default to 0:
|
||||
// direction bit == 0: the phase is increased by pi/2 (counter clockwise)
|
||||
// direction bit == 1: the phase is increased by -pi/2 (clockwise)
|
||||
setting_reg #(.my_addr(SR_HET_PHASE_INCR), .width(1)) sr_phase_dir (
|
||||
.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
|
||||
.in(set_data),.out(phase_dir),.changed(phase_sync));
|
||||
|
||||
/********************************************************
|
||||
** IQ Mapping (swapping, inversion, real-mode)
|
||||
********************************************************/
|
||||
// MUX so we can do realmode signals on either input
|
||||
always @(posedge clk) begin
|
||||
if (swap_iq) begin
|
||||
adc_i_mux[23:8] <= invert_q ? ~adc_q : adc_q;
|
||||
adc_q_mux[23:8] <= realmode ? 16'd0 : invert_i ? ~adc_i : adc_i;
|
||||
end else begin
|
||||
adc_i_mux[23:8] <= invert_i ? ~adc_i : adc_i;
|
||||
adc_q_mux[23:8] <= realmode ? 16'd0 : invert_q ? ~adc_q : adc_q;
|
||||
end
|
||||
adc_mux_stb <= adc_stb;
|
||||
adc_i_mux[7:0] <= 8'd0;
|
||||
adc_q_mux[7:0] <= 8'd0;
|
||||
end
|
||||
|
||||
/********************************************************
|
||||
** DC offset Correction
|
||||
********************************************************/
|
||||
generate
|
||||
if (BYPASS_DC_OFFSET_CORR == 0) begin
|
||||
|
||||
rx_dcoffset #(.WIDTH(24),.ADDR(SR_OFFSET_I)) rx_dcoffset_i (
|
||||
.clk(clk),.rst(reset),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
|
||||
.in_stb(adc_mux_stb),.in(adc_i_mux),
|
||||
.out_stb(adc_ofs_stb),.out(adc_i_ofs));
|
||||
rx_dcoffset #(.WIDTH(24),.ADDR(SR_OFFSET_Q)) rx_dcoffset_q (
|
||||
.clk(clk),.rst(reset),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
|
||||
.in_stb(adc_mux_stb),.in(adc_q_mux),
|
||||
.out_stb(),.out(adc_q_ofs));
|
||||
|
||||
end else begin
|
||||
assign adc_ofs_stb = adc_mux_stb;
|
||||
assign adc_i_ofs = adc_i_mux;
|
||||
assign adc_q_ofs = adc_q_mux;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
/********************************************************
|
||||
** IQ Imbalance Compensation
|
||||
********************************************************/
|
||||
generate
|
||||
if (BYPASS_IQ_COMP == 0) begin
|
||||
|
||||
mult_add_clip #(
|
||||
.WIDTH_A(18),
|
||||
.BIN_PT_A(17),
|
||||
.WIDTH_B(18),
|
||||
.BIN_PT_B(17),
|
||||
.WIDTH_C(24),
|
||||
.BIN_PT_C(23),
|
||||
.WIDTH_O(24),
|
||||
.BIN_PT_O(23),
|
||||
.LATENCY(2)
|
||||
) mult_i (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.CE(1'b1),
|
||||
.A(adc_i_ofs[23:6]),
|
||||
.B(mag_corr),
|
||||
.C(adc_i_ofs),
|
||||
.O(adc_i_comp)
|
||||
);
|
||||
|
||||
mult_add_clip #(
|
||||
.WIDTH_A(18),
|
||||
.BIN_PT_A(17),
|
||||
.WIDTH_B(18),
|
||||
.BIN_PT_B(17),
|
||||
.WIDTH_C(24),
|
||||
.BIN_PT_C(23),
|
||||
.WIDTH_O(24),
|
||||
.BIN_PT_O(23),
|
||||
.LATENCY(2)
|
||||
) mult_q (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.CE(1'b1),
|
||||
.A(adc_i_ofs[23:6]),
|
||||
.B(phase_corr),
|
||||
.C(adc_q_ofs),
|
||||
.O(adc_q_comp)
|
||||
);
|
||||
|
||||
// Delay to match path latencies
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
adc_ofs_stb_dly <= 2'b0;
|
||||
end else begin
|
||||
adc_ofs_stb_dly <= {adc_ofs_stb_dly[0], adc_ofs_stb};
|
||||
end
|
||||
end
|
||||
|
||||
assign adc_comp_stb = adc_ofs_stb_dly[1];
|
||||
|
||||
end else begin
|
||||
assign adc_comp_stb = adc_ofs_stb;
|
||||
assign adc_i_comp = adc_i_ofs;
|
||||
assign adc_q_comp = adc_q_ofs;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
/********************************************************
|
||||
** Realmode DSP:
|
||||
* - Heterodyne frequency translation
|
||||
* - Realmode decimation (by 2)
|
||||
********************************************************/
|
||||
generate
|
||||
if (BYPASS_REALMODE_DSP == 0) begin
|
||||
|
||||
wire [24:0] adc_i_dsp_cout, adc_q_dsp_cout;
|
||||
wire [23:0] adc_i_cclip, adc_q_cclip;
|
||||
wire [23:0] adc_i_hb, adc_q_hb;
|
||||
wire [23:0] adc_i_dec, adc_q_dec;
|
||||
wire adc_dsp_cout_stb;
|
||||
wire adc_cclip_stb;
|
||||
wire adc_hb_stb;
|
||||
|
||||
wire valid_hbf0;
|
||||
wire valid_hbf1;
|
||||
wire valid_dec0;
|
||||
wire valid_dec1;
|
||||
|
||||
// 90 degree mixer
|
||||
quarter_rate_downconverter #(.WIDTH(24)) qr_dc_i(
|
||||
.clk(clk), .reset(reset || sync_in), .phase_sync(phase_sync),
|
||||
.i_tdata({adc_i_comp, adc_q_comp}), .i_tlast(1'b1), .i_tvalid(adc_comp_stb), .i_tready(),
|
||||
.o_tdata({adc_i_dsp_cout, adc_q_dsp_cout}), .o_tlast(), .o_tvalid(adc_dsp_cout_stb), .o_tready(1'b1),
|
||||
.dirctn(phase_dir));
|
||||
|
||||
// Double FIR and decimator block
|
||||
localparam HB_COEFS = {-18'd62, 18'd0, 18'd194, 18'd0, -18'd440, 18'd0, 18'd855, 18'd0, -18'd1505, 18'd0, 18'd2478, 18'd0,
|
||||
-18'd3900, 18'd0, 18'd5990, 18'd0, -18'd9187, 18'd0, 18'd14632, 18'd0, -18'd26536, 18'd0, 18'd83009, 18'd131071, 18'd83009,
|
||||
18'd0, -18'd26536, 18'd0, 18'd14632, 18'd0, -18'd9187, 18'd0, 18'd5990, 18'd0, -18'd3900, 18'd0, 18'd2478, 18'd0, -18'd1505,
|
||||
18'd0, 18'd855, 18'd0, -18'd440, 18'd0, 18'd194, 18'd0, -18'd62};
|
||||
|
||||
axi_fir_filter_dec #(
|
||||
.WIDTH(24),
|
||||
.COEFF_WIDTH(18),
|
||||
.NUM_COEFFS(47),
|
||||
.COEFFS_VEC(HB_COEFS),
|
||||
.BLANK_OUTPUT(0)
|
||||
) ffd0 (
|
||||
.clk(clk), .reset(reset || sync_in),
|
||||
|
||||
.i_tdata({adc_i_dsp_cout, adc_q_dsp_cout}),
|
||||
.i_tlast(1'b1),
|
||||
.i_tvalid(adc_dsp_cout_stb),
|
||||
.i_tready(),
|
||||
|
||||
.o_tdata({adc_i_dec, adc_q_dec}),
|
||||
.o_tlast(),
|
||||
.o_tvalid(adc_hb_stb),
|
||||
.o_tready(1'b1));
|
||||
|
||||
assign adc_dsp_stb = realmode_decim ? adc_hb_stb : adc_comp_stb;
|
||||
assign adc_i_dsp = realmode_decim ? adc_i_dec : adc_i_comp;
|
||||
assign adc_q_dsp = realmode_decim ? adc_q_dec : adc_q_comp;
|
||||
|
||||
end else begin
|
||||
assign adc_dsp_stb = adc_comp_stb;
|
||||
assign adc_i_dsp = adc_i_comp;
|
||||
assign adc_q_dsp = adc_q_comp;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Round to short complex (sc16)
|
||||
round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i (
|
||||
.clk(clk),.reset(reset), .in(adc_i_dsp),.strobe_in(adc_dsp_stb), .out(rx_i_out), .strobe_out(rx_stb));
|
||||
round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q (
|
||||
.clk(clk),.reset(reset), .in(adc_q_dsp),.strobe_in(adc_dsp_stb), .out(rx_q_out), .strobe_out());
|
||||
|
||||
assign rx_i = bypass_all ? adc_i : rx_i_out;
|
||||
assign rx_q = bypass_all ? adc_q : rx_q_out;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,104 @@
|
||||
//
|
||||
// Copyright 2019 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: sim_radio_gen
|
||||
//
|
||||
// Description: Generate radio data for simulation purposes. The strobe pattern
|
||||
// is random, which is not like a normal radio but covers every possibility.
|
||||
// The data pattern is an incrementing sequence of samples, with each channel
|
||||
// starting at a different value to differentiate them. Strobe and time are
|
||||
// common between channels.
|
||||
//
|
||||
|
||||
module sim_radio_gen #(
|
||||
parameter int NSPC = 1, // Number of samples per clock cycle
|
||||
parameter int SAMP_W = 32, // Length of each radio sample
|
||||
parameter int NUM_CHANNELS = 1, // Number of radio RX ports
|
||||
parameter int STB_PROB = 50, // Probability of STB being asserted on each clock cycle
|
||||
parameter int INCREMENT = 2, // Amount by which to increment
|
||||
parameter int PPS_PERIOD = 50 // Period of the PPS output
|
||||
) (
|
||||
input bit radio_clk,
|
||||
input bit radio_rst,
|
||||
output bit [NUM_CHANNELS*SAMP_W*NSPC-1:0] radio_rx_data,
|
||||
output bit [ NUM_CHANNELS-1:0] radio_rx_stb,
|
||||
output bit [ 63:0] radio_time,
|
||||
output bit radio_pps
|
||||
);
|
||||
|
||||
localparam int RADIO_W = SAMP_W*NSPC;
|
||||
typedef bit [RADIO_W-1:0] radio_t; // Radio output word
|
||||
typedef bit [SAMP_W-1:0] sample_t; // Single sample
|
||||
|
||||
initial assert (PPS_PERIOD % INCREMENT == 0) else
|
||||
$fatal(1, "PPS_PERIOD must be a multiple of INCREMENT");
|
||||
|
||||
|
||||
// Generate an initial value all radio channels
|
||||
function radio_t [NUM_CHANNELS-1:0] radio_init();
|
||||
radio_t [NUM_CHANNELS-1:0] ret_val;
|
||||
|
||||
for (int n = 0; n < NUM_CHANNELS; n++) begin
|
||||
sample_t sample;
|
||||
|
||||
// Calculate the value of first sample in this radio channel
|
||||
sample = sample_t'((2.0 ** SAMP_W) / NUM_CHANNELS * n);
|
||||
|
||||
// Calculate the value of subsequent samples in the channel
|
||||
for (int s = 0; s < NSPC; s++) begin
|
||||
ret_val[n][s*SAMP_W +: SAMP_W] = sample + s;
|
||||
end
|
||||
end
|
||||
|
||||
return ret_val;
|
||||
endfunction : radio_init
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Radio Data Generation
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
radio_t [NUM_CHANNELS-1:0] data = radio_init();
|
||||
|
||||
assign radio_rx_data = data;
|
||||
|
||||
always @(posedge radio_clk) begin : radio_data_count_reg
|
||||
if (radio_rst) begin
|
||||
data <= radio_init();
|
||||
radio_rx_stb <= '0;
|
||||
end else begin
|
||||
radio_rx_stb <= '0;
|
||||
if ($urandom_range(100) < STB_PROB) begin
|
||||
for (int n = 0; n < NUM_CHANNELS; n++) begin
|
||||
for (int s = 0; s < NSPC; s++) begin
|
||||
data[n][s*SAMP_W +: SAMP_W] <= data[n][s*SAMP_W +: SAMP_W] + NSPC;
|
||||
end
|
||||
end
|
||||
radio_rx_stb <= '1;
|
||||
end
|
||||
end
|
||||
end : radio_data_count_reg
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Radio Time
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
always @(posedge radio_clk) begin
|
||||
if (radio_rst) begin
|
||||
radio_time <= 64'b0;
|
||||
radio_pps <= 1'b0;
|
||||
end else begin
|
||||
radio_pps <= 1'b0;
|
||||
if (radio_rx_stb[0]) begin
|
||||
radio_time <= radio_time + INCREMENT;
|
||||
if (radio_time % PPS_PERIOD == 0 && radio_time != 0) begin
|
||||
radio_pps <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule : sim_radio_gen
|
||||
@@ -0,0 +1,173 @@
|
||||
//
|
||||
// Copyright 2015 Ettus Research LLC
|
||||
// Copyright 2018 Ettus Research, a National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
|
||||
module tx_frontend_gen3 #(
|
||||
parameter SR_OFFSET_I = 0,
|
||||
parameter SR_OFFSET_Q = 1,
|
||||
parameter SR_MAG_CORRECTION = 2,
|
||||
parameter SR_PHASE_CORRECTION = 3,
|
||||
parameter SR_MUX = 4,
|
||||
parameter BYPASS_DC_OFFSET_CORR = 0,
|
||||
parameter BYPASS_IQ_COMP = 0,
|
||||
parameter DEVICE = "7SERIES"
|
||||
)(
|
||||
input clk, input reset,
|
||||
input set_stb, input [7:0] set_addr, input [31:0] set_data,
|
||||
input tx_stb, input [15:0] tx_i, input [15:0] tx_q,
|
||||
output reg dac_stb, output reg [15:0] dac_i, output reg [15:0] dac_q
|
||||
);
|
||||
|
||||
wire [23:0] i_dco, q_dco;
|
||||
wire [7:0] mux_ctrl;
|
||||
wire [17:0] mag_corr, phase_corr;
|
||||
|
||||
wire [35:0] corr_i, corr_q;
|
||||
reg [1:0] tx_stb_dly;
|
||||
reg [23:0] tx_i_dly, tx_q_dly;
|
||||
wire tx_comp_stb, tx_ofs_stb;
|
||||
wire [23:0] tx_i_comp, tx_q_comp, tx_i_ofs, tx_q_ofs;
|
||||
wire tx_round_stb;
|
||||
wire [15:0] tx_i_round, tx_q_round;
|
||||
|
||||
/********************************************************
|
||||
** Settings Registers
|
||||
********************************************************/
|
||||
setting_reg #(.my_addr(SR_OFFSET_I), .width(24)) sr_i_dc_offset (
|
||||
.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
|
||||
.in(set_data),.out(i_dco),.changed());
|
||||
|
||||
setting_reg #(.my_addr(SR_OFFSET_Q), .width(24)) sr_q_dc_offset (
|
||||
.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
|
||||
.in(set_data),.out(q_dco),.changed());
|
||||
|
||||
setting_reg #(.my_addr(SR_MAG_CORRECTION),.width(18)) sr_mag_corr (
|
||||
.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
|
||||
.in(set_data),.out(mag_corr),.changed());
|
||||
|
||||
setting_reg #(.my_addr(SR_PHASE_CORRECTION),.width(18)) sr_phase_corr (
|
||||
.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
|
||||
.in(set_data),.out(phase_corr),.changed());
|
||||
|
||||
setting_reg #(.my_addr(SR_MUX), .width(8), .at_reset(8'h10)) sr_mux_ctrl (
|
||||
.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
|
||||
.in(set_data),.out(mux_ctrl),.changed());
|
||||
|
||||
/********************************************************
|
||||
** DSP
|
||||
********************************************************/
|
||||
// I/Q compensation with option to bypass
|
||||
generate
|
||||
if (BYPASS_IQ_COMP == 0) begin
|
||||
|
||||
mult_add_clip #(
|
||||
.WIDTH_A(16),
|
||||
.BIN_PT_A(15),
|
||||
.WIDTH_B(18),
|
||||
.BIN_PT_B(17),
|
||||
.WIDTH_C(16),
|
||||
.BIN_PT_C(15),
|
||||
.WIDTH_O(24),
|
||||
.BIN_PT_O(23),
|
||||
.LATENCY(2)
|
||||
) mult_i (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.CE(1'b1),
|
||||
.A(tx_i),
|
||||
.B(mag_corr),
|
||||
.C(tx_i),
|
||||
.O(tx_i_comp)
|
||||
);
|
||||
|
||||
mult_add_clip #(
|
||||
.WIDTH_A(16),
|
||||
.BIN_PT_A(15),
|
||||
.WIDTH_B(18),
|
||||
.BIN_PT_B(17),
|
||||
.WIDTH_C(16),
|
||||
.BIN_PT_C(15),
|
||||
.WIDTH_O(24),
|
||||
.BIN_PT_O(23),
|
||||
.LATENCY(2)
|
||||
) mult_q (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.CE(1'b1),
|
||||
.A(tx_i),
|
||||
.B(phase_corr),
|
||||
.C(tx_q),
|
||||
.O(tx_q_comp)
|
||||
);
|
||||
|
||||
// Delay to match path latencies
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
tx_stb_dly <= 2'b0;
|
||||
end else begin
|
||||
tx_stb_dly <= {tx_stb_dly[0], tx_stb};
|
||||
end
|
||||
end
|
||||
|
||||
assign tx_comp_stb = tx_stb_dly[1];
|
||||
|
||||
end else begin
|
||||
assign tx_comp_stb = tx_stb;
|
||||
assign tx_i_comp = {tx_i,8'd0};
|
||||
assign tx_q_comp = {tx_q,8'd0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// DC offset correction
|
||||
generate
|
||||
if (BYPASS_DC_OFFSET_CORR == 0) begin
|
||||
add2_and_clip_reg #(.WIDTH(24)) add_dco_i (
|
||||
.clk(clk), .rst(reset), .in1(i_dco), .in2(tx_i_comp), .strobe_in(tx_comp_stb), .sum(tx_i_ofs), .strobe_out(tx_ofs_stb));
|
||||
add2_and_clip_reg #(.WIDTH(24)) add_dco_q (
|
||||
.clk(clk), .rst(reset), .in1(q_dco), .in2(tx_q_comp), .strobe_in(tx_comp_stb), .sum(tx_q_ofs), .strobe_out());
|
||||
end else begin
|
||||
assign tx_ofs_stb = tx_comp_stb;
|
||||
assign tx_i_ofs = tx_i_comp;
|
||||
assign tx_q_ofs = tx_q_comp;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Round to short complex (sc16)
|
||||
round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i (
|
||||
.clk(clk),.reset(reset), .in(tx_i_ofs),.strobe_in(tx_ofs_stb), .out(tx_i_round), .strobe_out(tx_round_stb));
|
||||
round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q (
|
||||
.clk(clk),.reset(reset), .in(tx_q_ofs),.strobe_in(tx_ofs_stb), .out(tx_q_round), .strobe_out());
|
||||
|
||||
// Mux
|
||||
// Muxing logic matches that in tx_frontend.v, and what tx_frontend_core_200.cpp expects.
|
||||
//
|
||||
// mux_ctrl ! 0+0 ! 0+16 ! 1+0 ! 1+16
|
||||
// =========!======!======!======!========
|
||||
// DAC_I ! tx_i ! tx_i ! tx_q ! tx_q
|
||||
// DAC_Q ! tx_i ! tx_q ! tx_i ! tx_q
|
||||
//
|
||||
// Most daughterboards will thus use 0x01 or 0x10 as the mux_ctrl value.
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
dac_stb <= 1'b0;
|
||||
dac_i <= 16'd0;
|
||||
dac_q <= 16'd0;
|
||||
end else begin
|
||||
dac_stb <= tx_round_stb;
|
||||
case(mux_ctrl[3:0])
|
||||
0 : dac_i <= tx_i_round;
|
||||
1 : dac_i <= tx_q_round;
|
||||
default : dac_i <= 0;
|
||||
endcase
|
||||
case(mux_ctrl[7:4])
|
||||
0 : dac_q <= tx_i_round;
|
||||
1 : dac_q <= tx_q_round;
|
||||
default : dac_q <= 0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user