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Merge FPGA repository back into UHD repository

Browse Source 
The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>


Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
2020-01-28 09:35:36 -08:00
co-authored by Alex Williams Andrej Rode Ashish Chaudhari Ben Hilburn Ciro Nishiguchi Daniel Jepson Derek Kozel EJ Kreinar Humberto Jimenez Ian Buckley Jörg Hofrichter Jon Kiser Josh Blum Jonathon Pendlum Matt Ettus Michael West Moritz Fischer Nick Foster Nicolas Cuervo Paul Butler Paul David Ryan Marlow Sugandha Gupta Sylvain Munaut Trung Tran Vidush Vishwanath Wade Fife
parent 74893643ca
commit 6b67702ad7
2157 changed files with 1282567 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/rfnoc/blocks/rfnoc_block_null_src_sink/Makefile
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#
# Copyright 2019 Ettus Research, A National Instruments Company
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
#-------------------------------------------------
# Top-of-Makefile
#-------------------------------------------------
# Define BASE_DIR to point to the "top" dir
BASE_DIR = $(abspath ../../../../top)
# Include viv_sim_preamble after defining BASE_DIR
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
#-------------------------------------------------
# Design Specific
#-------------------------------------------------
# Include makefiles and sources for the DUT and its dependencies
include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
include Makefile.srcs
DESIGN_SRCS += $(abspath \
$(RFNOC_CORE_SRCS) \
$(RFNOC_UTIL_SRCS) \
$(RFNOC_OOT_SRCS) \
)
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
SIM_TOP = rfnoc_block_null_src_sink_tb
SIM_SRCS = \
$(abspath rfnoc_block_null_src_sink_tb.sv) \
# MODELSIM_USER_DO = $(abspath wave.do)
#-------------------------------------------------
# Bottom-of-Makefile
#-------------------------------------------------
# Include all simulator specific makefiles here
# Each should define a unique target to simulate
# e.g. xsim, vsim, etc and a common "clean" target
include $(BASE_DIR)/../tools/make/viv_simulator.mak
lib/rfnoc/blocks/rfnoc_block_null_src_sink/Makefile.srcs
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#
# Copyright 2019 Ettus Research, A National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
##################################################
# RFNoC Utility Sources
##################################################
RFNOC_OOT_SRCS += $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_null_src_sink/, \
rfnoc_block_null_src_sink.v \
))
lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink.v
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//
// Copyright 2019 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfnoc_block_null_src_sink
// Description:
//
// Parameters:
//
// Signals:
module rfnoc_block_null_src_sink #(
parameter [9:0] THIS_PORTID = 10'd0,
parameter CHDR_W = 64,
parameter NIPC = 2,
parameter [5:0] MTU = 10
)(
// RFNoC Framework Clocks and Resets
input wire rfnoc_chdr_clk,
input wire rfnoc_ctrl_clk,
// RFNoC Backend Interface
input wire [511:0] rfnoc_core_config,
output wire [511:0] rfnoc_core_status,
// 2 CHDR Input Ports (from framework)
input wire [(CHDR_W*2)-1:0] s_rfnoc_chdr_tdata,
input wire [1:0] s_rfnoc_chdr_tlast,
input wire [1:0] s_rfnoc_chdr_tvalid,
output wire [1:0] s_rfnoc_chdr_tready,
// 2 CHDR Output Ports (to framework)
output wire [(CHDR_W*2)-1:0] m_rfnoc_chdr_tdata,
output wire [1:0] m_rfnoc_chdr_tlast,
output wire [1:0] m_rfnoc_chdr_tvalid,
input wire [1:0] m_rfnoc_chdr_tready,
// AXIS-Ctrl Input Port (from framework)
input wire [31:0] s_rfnoc_ctrl_tdata,
input wire s_rfnoc_ctrl_tlast,
input wire s_rfnoc_ctrl_tvalid,
output wire s_rfnoc_ctrl_tready,
// AXIS-Ctrl Output Port (to framework)
output wire [31:0] m_rfnoc_ctrl_tdata,
output wire m_rfnoc_ctrl_tlast,
output wire m_rfnoc_ctrl_tvalid,
input wire m_rfnoc_ctrl_tready
);
`include "../../core/rfnoc_chdr_utils.vh"
localparam [19:0] REG_CTRL_STATUS = 20'h00;
localparam [19:0] REG_SRC_LINES_PER_PKT = 20'h04;
localparam [19:0] REG_SRC_BYTES_PER_PKT = 20'h08;
localparam [19:0] REG_SRC_THROTTLE_CYC = 20'h0C;
localparam [19:0] REG_SNK_LINE_CNT_LO = 20'h10;
localparam [19:0] REG_SNK_LINE_CNT_HI = 20'h14;
localparam [19:0] REG_SNK_PKT_CNT_LO = 20'h18;
localparam [19:0] REG_SNK_PKT_CNT_HI = 20'h1C;
localparam [19:0] REG_SRC_LINE_CNT_LO = 20'h20;
localparam [19:0] REG_SRC_LINE_CNT_HI = 20'h24;
localparam [19:0] REG_SRC_PKT_CNT_LO = 20'h28;
localparam [19:0] REG_SRC_PKT_CNT_HI = 20'h2C;
localparam [19:0] REG_LOOP_LINE_CNT_LO = 20'h30;
localparam [19:0] REG_LOOP_LINE_CNT_HI = 20'h34;
localparam [19:0] REG_LOOP_PKT_CNT_LO = 20'h38;
localparam [19:0] REG_LOOP_PKT_CNT_HI = 20'h3C;
wire rfnoc_chdr_rst;
wire rfnoc_ctrl_rst;
wire ctrlport_req_wr;
wire ctrlport_req_rd;
wire [19:0] ctrlport_req_addr;
wire [31:0] ctrlport_req_data;
reg ctrlport_resp_ack;
reg [31:0] ctrlport_resp_data;
wire [(32*NIPC)-1:0] src_pyld_tdata , snk_pyld_tdata , loop_pyld_tdata ;
wire [NIPC-1:0] src_pyld_tkeep , snk_pyld_tkeep , loop_pyld_tkeep ;
wire src_pyld_tlast , snk_pyld_tlast , loop_pyld_tlast ;
wire src_pyld_tvalid, snk_pyld_tvalid, loop_pyld_tvalid;
wire src_pyld_tready, snk_pyld_tready, loop_pyld_tready;
wire [CHDR_W-1:0] src_ctxt_tdata , snk_ctxt_tdata , loop_ctxt_tdata ;
wire [3:0] src_ctxt_tuser , snk_ctxt_tuser , loop_ctxt_tuser ;
wire src_ctxt_tlast , snk_ctxt_tlast , loop_ctxt_tlast ;
wire src_ctxt_tvalid, snk_ctxt_tvalid, loop_ctxt_tvalid;
wire src_ctxt_tready, snk_ctxt_tready, loop_ctxt_tready;
// NoC Shell
// ---------------------------
noc_shell_generic_ctrlport_pyld_chdr #(
.NOC_ID (32'h0000_0001),
.THIS_PORTID (THIS_PORTID),
.CHDR_W (CHDR_W),
.CTRL_FIFOSIZE (5),
.CTRLPORT_SLV_EN (0),
.NUM_DATA_I (2),
.NUM_DATA_O (2),
.ITEM_W (32),
.NIPC (NIPC),
.MTU (MTU),
.CTXT_FIFOSIZE (1),
.PYLD_FIFOSIZE (1)
) noc_shell_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk ),
.rfnoc_chdr_rst (rfnoc_chdr_rst ),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
.rfnoc_core_config (rfnoc_core_config ),
.rfnoc_core_status (rfnoc_core_status ),
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata ),
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast ),
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid ),
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready ),
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata ),
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast ),
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid ),
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready ),
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid ),
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready ),
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid ),
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready ),
.m_ctrlport_req_wr (ctrlport_req_wr ),
.m_ctrlport_req_rd (ctrlport_req_rd ),
.m_ctrlport_req_addr (ctrlport_req_addr ),
.m_ctrlport_req_data (ctrlport_req_data ),
.m_ctrlport_req_byte_en ( ),
.m_ctrlport_req_has_time ( ),
.m_ctrlport_req_time ( ),
.m_ctrlport_resp_ack (ctrlport_resp_ack ),
.m_ctrlport_resp_status (2'd0 ),
.m_ctrlport_resp_data (ctrlport_resp_data ),
.s_ctrlport_req_wr ('h0 ),
.s_ctrlport_req_rd ('h0 ),
.s_ctrlport_req_addr ('h0 ),
.s_ctrlport_req_portid ('h0 ),
.s_ctrlport_req_rem_epid ('h0 ),
.s_ctrlport_req_rem_portid('h0 ),
.s_ctrlport_req_data ('h0 ),
.s_ctrlport_req_byte_en ('h0 ),
.s_ctrlport_req_has_time ('h0 ),
.s_ctrlport_req_time ('h0 ),
.s_ctrlport_resp_ack ( ),
.s_ctrlport_resp_status ( ),
.s_ctrlport_resp_data ( ),
.m_axis_payload_tdata ({loop_pyld_tdata , snk_pyld_tdata }),
.m_axis_payload_tkeep ({loop_pyld_tkeep , snk_pyld_tkeep }),
.m_axis_payload_tlast ({loop_pyld_tlast , snk_pyld_tlast }),
.m_axis_payload_tvalid ({loop_pyld_tvalid, snk_pyld_tvalid}),
.m_axis_payload_tready ({loop_pyld_tready, snk_pyld_tready}),
.m_axis_context_tdata ({loop_ctxt_tdata , snk_ctxt_tdata }),
.m_axis_context_tuser ({loop_ctxt_tuser , snk_ctxt_tuser }),
.m_axis_context_tlast ({loop_ctxt_tlast , snk_ctxt_tlast }),
.m_axis_context_tvalid ({loop_ctxt_tvalid, snk_ctxt_tvalid}),
.m_axis_context_tready ({loop_ctxt_tready, snk_ctxt_tready}),
.s_axis_payload_tdata ({loop_pyld_tdata , src_pyld_tdata }),
.s_axis_payload_tkeep ({loop_pyld_tkeep , src_pyld_tkeep }),
.s_axis_payload_tlast ({loop_pyld_tlast , src_pyld_tlast }),
.s_axis_payload_tvalid ({loop_pyld_tvalid, src_pyld_tvalid}),
.s_axis_payload_tready ({loop_pyld_tready, src_pyld_tready}),
.s_axis_context_tdata ({loop_ctxt_tdata , src_ctxt_tdata }),
.s_axis_context_tuser ({loop_ctxt_tuser , src_ctxt_tuser }),
.s_axis_context_tlast ({loop_ctxt_tlast , src_ctxt_tlast }),
.s_axis_context_tvalid ({loop_ctxt_tvalid, src_ctxt_tvalid}),
.s_axis_context_tready ({loop_ctxt_tready, src_ctxt_tready})
);
// Packet Counters
// ---------------------------
reg reg_clear_cnts = 1'b0;
reg [63:0] snk_line_cnt = 64'd0, snk_pkt_cnt = 64'd0;
reg [63:0] src_line_cnt = 64'd0, src_pkt_cnt = 64'd0;
reg [63:0] loop_line_cnt = 64'd0, loop_pkt_cnt = 64'd0;
always @(posedge rfnoc_chdr_clk) begin
if (rfnoc_chdr_rst | reg_clear_cnts) begin
snk_line_cnt <= 64'd0;
snk_pkt_cnt <= 64'd0;
src_line_cnt <= 64'd0;
src_pkt_cnt <= 64'd0;
loop_line_cnt <= 64'd0;
loop_pkt_cnt <= 64'd0;
end else begin
if (snk_pyld_tvalid & snk_pyld_tready) begin
snk_line_cnt <= snk_line_cnt + 1;
if (snk_pyld_tlast)
snk_pkt_cnt <= snk_pkt_cnt + 1;
end
if (src_pyld_tvalid & src_pyld_tready) begin
src_line_cnt <= src_line_cnt + 1;
if (src_pyld_tlast)
src_pkt_cnt <= src_pkt_cnt + 1;
end
if (loop_pyld_tvalid & loop_pyld_tready) begin
loop_line_cnt <= loop_line_cnt + 1;
if (loop_pyld_tlast)
loop_pkt_cnt <= loop_pkt_cnt + 1;
end
end
end
// NULL Sink
// ---------------------------
assign snk_pyld_tready = 1'b1;
assign snk_ctxt_tready = 1'b1;
// NULL Source
// ---------------------------
reg reg_src_en = 1'b0;
reg [11:0] reg_src_lpp = 12'd0;
reg [15:0] reg_src_bpp = 16'd0;
reg [9:0] reg_throttle_cyc = 10'd0;
localparam [1:0] ST_HDR = 2'd0;
localparam [1:0] ST_PYLD = 2'd1;
localparam [1:0] ST_WAIT = 2'd2;
reg [1:0] state = ST_HDR;
reg [11:0] lines_left = 12'd0;
reg [9:0] throttle_cntr = 10'd0;
always @(posedge rfnoc_chdr_clk) begin
if (rfnoc_chdr_rst) begin
state <= ST_HDR;
end else begin
case (state)
ST_HDR: begin
if (src_ctxt_tvalid && src_ctxt_tready) begin
state <= ST_PYLD;
lines_left <= reg_src_lpp;
end
end
ST_PYLD: begin
if (src_pyld_tvalid && src_pyld_tready) begin
if (src_pyld_tlast) begin
if (reg_throttle_cyc == 10'd0) begin
state <= ST_HDR;
end else begin
state <= ST_WAIT;
throttle_cntr <= reg_throttle_cyc;
end
end else begin
lines_left <= lines_left - 12'd1;
end
end
end
ST_WAIT: begin
if (throttle_cntr == 10'd0)
state <= ST_HDR;
else
throttle_cntr <= throttle_cntr - 10'd1;
end
default: begin
state <= ST_HDR;
end
endcase
end
end
assign src_pyld_tdata = {NIPC{{~src_line_cnt[15:0], src_line_cnt[15:0]}}};
assign src_pyld_tkeep = {NIPC{1'b1}};
assign src_pyld_tlast = (lines_left == 12'd0);
assign src_pyld_tvalid = (state == ST_PYLD);
assign src_ctxt_tdata = chdr_build_header(
6'd0, 1'b0, 1'b0, CHDR_PKT_TYPE_DATA, CHDR_NO_MDATA, src_pkt_cnt[15:0], reg_src_bpp, 16'd0);
assign src_ctxt_tuser = CONTEXT_FIELD_HDR;
assign src_ctxt_tlast = 1'b1;
assign src_ctxt_tvalid = (state == ST_HDR && reg_src_en);
// Register Interface
// ---------------------------
always @(posedge rfnoc_chdr_clk) begin
if (rfnoc_chdr_rst) begin
ctrlport_resp_ack <= 1'b0;
end else begin
// All transactions finish in 1 cycle
ctrlport_resp_ack <= ctrlport_req_wr | ctrlport_req_rd;
// Handle register writes
if (ctrlport_req_wr) begin
case(ctrlport_req_addr)
REG_CTRL_STATUS:
{reg_src_en, reg_clear_cnts} <= ctrlport_req_data[1:0];
REG_SRC_LINES_PER_PKT:
reg_src_lpp <= ctrlport_req_data[11:0];
REG_SRC_BYTES_PER_PKT:
reg_src_bpp <= ctrlport_req_data[15:0];
REG_SRC_THROTTLE_CYC:
reg_throttle_cyc <= ctrlport_req_data[9:0];
endcase
end
// Handle register reads
if (ctrlport_req_rd) begin
case(ctrlport_req_addr)
REG_CTRL_STATUS:
ctrlport_resp_data <= {NIPC[7:0], 8'd32, state, 12'h0, reg_src_en, reg_clear_cnts};
REG_SRC_LINES_PER_PKT:
ctrlport_resp_data <= {20'h0, reg_src_lpp};
REG_SRC_BYTES_PER_PKT:
ctrlport_resp_data <= {16'h0, reg_src_bpp};
REG_SRC_THROTTLE_CYC:
ctrlport_resp_data <= {22'h0, reg_throttle_cyc};
REG_SNK_LINE_CNT_LO:
ctrlport_resp_data <= snk_line_cnt[31:0];
REG_SNK_LINE_CNT_HI:
ctrlport_resp_data <= snk_line_cnt[63:32];
REG_SNK_PKT_CNT_LO:
ctrlport_resp_data <= snk_pkt_cnt[31:0];
REG_SNK_PKT_CNT_HI:
ctrlport_resp_data <= snk_pkt_cnt[63:32];
REG_SRC_LINE_CNT_LO:
ctrlport_resp_data <= src_line_cnt[31:0];
REG_SRC_LINE_CNT_HI:
ctrlport_resp_data <= src_line_cnt[63:32];
REG_SRC_PKT_CNT_LO:
ctrlport_resp_data <= src_pkt_cnt[31:0];
REG_SRC_PKT_CNT_HI:
ctrlport_resp_data <= src_pkt_cnt[63:32];
REG_LOOP_LINE_CNT_LO:
ctrlport_resp_data <= loop_line_cnt[31:0];
REG_LOOP_LINE_CNT_HI:
ctrlport_resp_data <= loop_line_cnt[63:32];
REG_LOOP_PKT_CNT_LO:
ctrlport_resp_data <= loop_pkt_cnt[31:0];
REG_LOOP_PKT_CNT_HI:
ctrlport_resp_data <= loop_pkt_cnt[63:32];
default:
ctrlport_resp_data <= 32'h0;
endcase
end
end
end
endmodule // rfnoc_block_null_src_sink
lib/rfnoc/blocks/rfnoc_block_null_src_sink/rfnoc_block_null_src_sink_tb.sv
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//
// Copyright 2019 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfnoc_block_null_src_sink_tb
//
`default_nettype none
module rfnoc_block_null_src_sink_tb;
// Include macros and time declarations for use with PkgTestExec
`include "test_exec.svh"
import PkgTestExec::*;
import PkgChdrUtils::*;
import PkgRfnocBlockCtrlBfm::*;
import PkgRfnocItemUtils::*;
// Parameters
localparam [9:0] THIS_PORTID = 10'h17;
localparam [15:0] THIS_EPID = 16'hDEAD;
localparam int CHDR_W = 64;
localparam int SPP = 201;
localparam int LPP = ((SPP+1)/2);
localparam int NUM_PKTS = 50;
localparam int PORT_SRCSNK = 0;
localparam int PORT_LOOP = 1;
// Clock and Reset Definition
bit rfnoc_chdr_clk;
sim_clock_gen #(2.5) rfnoc_chdr_clk_gen (rfnoc_chdr_clk); // 400 MHz
// ----------------------------------------
// Instantiate DUT
// ----------------------------------------
// Connections to DUT as interfaces:
RfnocBackendIf backend (rfnoc_chdr_clk, rfnoc_chdr_clk); // Required backend iface
AxiStreamIf #(32) m_ctrl (rfnoc_chdr_clk); // Required control iface
AxiStreamIf #(32) s_ctrl (rfnoc_chdr_clk); // Required control iface
AxiStreamIf #(CHDR_W) m0_chdr (rfnoc_chdr_clk); // Optional data iface
AxiStreamIf #(CHDR_W) m1_chdr (rfnoc_chdr_clk); // Optional data iface
AxiStreamIf #(CHDR_W) s0_chdr (rfnoc_chdr_clk); // Optional data iface
AxiStreamIf #(CHDR_W) s1_chdr (rfnoc_chdr_clk); // Optional data iface
// Bus functional model for a software block controller
RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl;
// DUT
rfnoc_block_null_src_sink #(
.THIS_PORTID (THIS_PORTID),
.CHDR_W (CHDR_W),
.NIPC (2),
.MTU (10)
) dut (
.rfnoc_chdr_clk (backend.chdr_clk),
.rfnoc_ctrl_clk (backend.ctrl_clk),
.rfnoc_core_config (backend.slave.cfg),
.rfnoc_core_status (backend.slave.sts),
.s_rfnoc_chdr_tdata ({m1_chdr.slave.tdata , m0_chdr.slave.tdata }),
.s_rfnoc_chdr_tlast ({m1_chdr.slave.tlast , m0_chdr.slave.tlast }),
.s_rfnoc_chdr_tvalid({m1_chdr.slave.tvalid , m0_chdr.slave.tvalid }),
.s_rfnoc_chdr_tready({m1_chdr.slave.tready , m0_chdr.slave.tready }),
.m_rfnoc_chdr_tdata ({s1_chdr.master.tdata , s0_chdr.master.tdata }),
.m_rfnoc_chdr_tlast ({s1_chdr.master.tlast , s0_chdr.master.tlast }),
.m_rfnoc_chdr_tvalid({s1_chdr.master.tvalid, s0_chdr.master.tvalid}),
.m_rfnoc_chdr_tready({s1_chdr.master.tready, s0_chdr.master.tready}),
.s_rfnoc_ctrl_tdata (m_ctrl.slave.tdata ),
.s_rfnoc_ctrl_tlast (m_ctrl.slave.tlast ),
.s_rfnoc_ctrl_tvalid(m_ctrl.slave.tvalid ),
.s_rfnoc_ctrl_tready(m_ctrl.slave.tready ),
.m_rfnoc_ctrl_tdata (s_ctrl.master.tdata ),
.m_rfnoc_ctrl_tlast (s_ctrl.master.tlast ),
.m_rfnoc_ctrl_tvalid(s_ctrl.master.tvalid),
.m_rfnoc_ctrl_tready(s_ctrl.master.tready)
);
// ----------------------------------------
// Test Process
// ----------------------------------------
initial begin
// Shared Variables
// ----------------------------------------
timeout_t timeout;
ctrl_word_t rvalue = 0;
// Initialize
// ----------------------------------------
test.start_tb("rfnoc_block_null_src_sink_tb");
// Start the stream endpoint BFM
blk_ctrl = new(backend, m_ctrl, s_ctrl);
blk_ctrl.add_master_data_port(m0_chdr);
blk_ctrl.add_slave_data_port(s0_chdr);
blk_ctrl.add_master_data_port(m1_chdr);
blk_ctrl.add_slave_data_port(s1_chdr);
blk_ctrl.run();
// Startup block (Software initialization)
// ----------------------------------------
test.start_test("Flush block then reset it");
begin
test.start_timeout(timeout, 10us, "Waiting for flush_and_reset");
#100; //Wait for GSR to deassert
blk_ctrl.flush_and_reset();
test.end_timeout(timeout);
end
test.end_test();
// Run Tests
// ----------------------------------------
test.start_test("Read Block Info");
begin
test.start_timeout(timeout, 1us, "Waiting for block info response");
// Get static block info and validate it
`ASSERT_ERROR(blk_ctrl.get_noc_id() == 1, "Incorrect noc_id Value");
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == 2, "Incorrect num_data_i Value");
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == 2, "Incorrect num_data_o Value");
`ASSERT_ERROR(blk_ctrl.get_ctrl_fifosize() == 5, "Incorrect ctrl_fifosize Value");
`ASSERT_ERROR(blk_ctrl.get_mtu() == 10, "Incorrect mtu Value");
// Read status register and validate it
blk_ctrl.reg_read(dut.REG_CTRL_STATUS, rvalue);
`ASSERT_ERROR(rvalue[31:24] == 2, "Incorrect NIPC Value");
`ASSERT_ERROR(rvalue[23:16] == 32, "Incorrect ITEM_W Value");
test.end_timeout(timeout);
end
test.end_test();
test.start_test("Stream Data Through Loopback Port");
begin
// Send and receive packets
repeat (NUM_PKTS) begin
chdr_word_t rx_data[$];
int rx_bytes;
automatic ItemDataBuff #(logic[31:0]) tx_dbuff = new, rx_dbuff = new;
for (int i = 0; i < SPP; i++)
tx_dbuff.put($urandom());
test.start_timeout(timeout, 5us, "Waiting for pkt to loop back");
blk_ctrl.send(PORT_LOOP, tx_dbuff.to_chdr_payload(), tx_dbuff.get_bytes());
blk_ctrl.recv(PORT_LOOP, rx_data, rx_bytes);
rx_dbuff.from_chdr_payload(rx_data, rx_bytes);
`ASSERT_ERROR(rx_dbuff.equal(tx_dbuff), "Data mismatch");
test.end_timeout(timeout);
end
// Read item and packet counts on loopback port
blk_ctrl.reg_read(dut.REG_LOOP_LINE_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == (LPP*NUM_PKTS), "Incorrect REG_LOOP_LINE_CNT_LO value");
blk_ctrl.reg_read(dut.REG_LOOP_PKT_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == NUM_PKTS, "Incorrect REG_LOOP_PKT_CNT_LO value");
// Read item and packet counts on source port
blk_ctrl.reg_read(dut.REG_SRC_LINE_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == 0, "Incorrect REG_SRC_LINE_CNT_LO value");
blk_ctrl.reg_read(dut.REG_SRC_PKT_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == 0, "Incorrect REG_SRC_PKT_CNT_LO value");
// Read item and packet counts on sink port
blk_ctrl.reg_read(dut.REG_SNK_LINE_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == 0, "Incorrect REG_SNK_LINE_CNT_LO value");
blk_ctrl.reg_read(dut.REG_SNK_PKT_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == 0, "Incorrect REG_SNK_PKT_CNT_LO value");
end
test.end_test();
test.start_test("Stream Data To Sink Port");
begin
// Send packets
repeat (NUM_PKTS) begin
chdr_word_t rx_data[$];
int rx_bytes;
automatic ItemDataBuff #(logic[31:0]) tx_dbuff = new;
for (int i = 0; i < SPP; i++)
tx_dbuff.put($urandom());
test.start_timeout(timeout, 5us, "Waiting for pkt to loop back");
blk_ctrl.send(PORT_SRCSNK, tx_dbuff.to_chdr_payload(), tx_dbuff.get_bytes());
test.end_timeout(timeout);
end
repeat (NUM_PKTS * SPP * 2) @(posedge rfnoc_chdr_clk);
// Read item and packet counts on loopback port
blk_ctrl.reg_read(dut.REG_LOOP_LINE_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == (LPP*NUM_PKTS), "Incorrect REG_LOOP_LINE_CNT_LO value");
blk_ctrl.reg_read(dut.REG_LOOP_PKT_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == NUM_PKTS, "Incorrect REG_LOOP_PKT_CNT_LO value");
// Read item and packet counts on source port
blk_ctrl.reg_read(dut.REG_SRC_LINE_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == 0, "Incorrect REG_SRC_LINE_CNT_LO value");
blk_ctrl.reg_read(dut.REG_SRC_PKT_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == 0, "Incorrect REG_SRC_PKT_CNT_LO value");
// Read item and packet counts on sink port
blk_ctrl.reg_read(dut.REG_SNK_LINE_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == (LPP*NUM_PKTS), "Incorrect REG_SNK_LINE_CNT_LO value");
blk_ctrl.reg_read(dut.REG_SNK_PKT_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == NUM_PKTS, "Incorrect REG_SNK_PKT_CNT_LO value");
end
test.end_test();
test.start_test("Stream Data From Source Port");
begin
// Turn on the source for some time then stop it
blk_ctrl.reg_write(dut.REG_SRC_LINES_PER_PKT, LPP-1);
blk_ctrl.reg_write(dut.REG_SRC_BYTES_PER_PKT, (LPP+1)*8);
blk_ctrl.reg_write(dut.REG_CTRL_STATUS, 2'b10);
repeat ((NUM_PKTS / 10) * LPP) @(posedge rfnoc_chdr_clk);
blk_ctrl.reg_write(dut.REG_CTRL_STATUS, 2'b00);
blk_ctrl.reg_read(dut.REG_SRC_PKT_CNT_LO, rvalue);
repeat (rvalue * LPP * 2) @(posedge rfnoc_chdr_clk);
blk_ctrl.reg_read(dut.REG_SRC_PKT_CNT_LO, rvalue);
// Gather the accumulated packets and verify contents
for (int p = 0; p < rvalue; p++) begin
chdr_word_t exp_data[$];
chdr_word_t rx_data[$];
int rx_bytes;
test.start_timeout(timeout, 5us, "Waiting for pkt to arrive");
exp_data.delete();
for (int i = p*LPP; i < (p+1)*LPP; i++)
exp_data.push_back({~i[15:0], i[15:0], ~i[15:0], i[15:0]});
blk_ctrl.recv(PORT_SRCSNK, rx_data, rx_bytes);
`ASSERT_ERROR(blk_ctrl.compare_data(exp_data, rx_data), "Data mismatch");
test.end_timeout(timeout);
end
end
test.end_test();
test.start_test("Clear Counts");
begin
test.start_timeout(timeout, 1us, "Waiting for clear and readbacks");
// Clear
blk_ctrl.reg_write(dut.REG_CTRL_STATUS, 2'b01);
// Read item and packet counts on loopback port
blk_ctrl.reg_read(dut.REG_LOOP_LINE_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == 0, "Incorrect REG_LOOP_LINE_CNT_LO value");
blk_ctrl.reg_read(dut.REG_LOOP_PKT_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == 0, "Incorrect REG_LOOP_PKT_CNT_LO value");
// Read item and packet counts on source port
blk_ctrl.reg_read(dut.REG_SRC_LINE_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == 0, "Incorrect REG_SRC_LINE_CNT_LO value");
blk_ctrl.reg_read(dut.REG_SRC_PKT_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == 0, "Incorrect REG_SRC_PKT_CNT_LO value");
// Read item and packet counts on sink port
blk_ctrl.reg_read(dut.REG_SNK_LINE_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == 0, "Incorrect REG_SNK_LINE_CNT_LO value");
blk_ctrl.reg_read(dut.REG_SNK_PKT_CNT_LO, rvalue);
`ASSERT_ERROR(rvalue == 0, "Incorrect REG_SNK_PKT_CNT_LO value");
test.end_timeout(timeout);
end
test.end_test();
// Finish Up
// ----------------------------------------
// Display final statistics and results
test.end_tb();
end
endmodule