Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
@@ -0,0 +1,559 @@
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//
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// Copyright 2019 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfnoc_block_fft
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//
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// Description: An FFT block for RFNoC.
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//
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// Parameters:
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//
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// THIS_PORTID : Control crossbar port to which this block is connected
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// CHDR_W : AXIS CHDR interface data width
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// MTU : Maximum transmission unit (i.e., maximum packet size) in
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// CHDR words is 2**MTU.
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// EN_MAGNITUDE_OUT : CORDIC based magnitude calculation
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// EN_MAGNITUDE_APPROX_OUT : Multipler-less, lower resource usage
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// EN_MAGNITUDE_SQ_OUT : Magnitude squared
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// EN_FFT_SHIFT : Center zero frequency bin
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//
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module rfnoc_block_fft #(
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parameter THIS_PORTID = 0,
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parameter CHDR_W = 64,
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parameter MTU = 10,
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parameter EN_MAGNITUDE_OUT = 0,
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parameter EN_MAGNITUDE_APPROX_OUT = 1,
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parameter EN_MAGNITUDE_SQ_OUT = 1,
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parameter EN_FFT_SHIFT = 1
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)
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(
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//---------------------------------------------------------------------------
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// AXIS CHDR Port
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//---------------------------------------------------------------------------
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input wire rfnoc_chdr_clk,
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input wire ce_clk,
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// CHDR inputs from framework
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input wire [CHDR_W-1:0] s_rfnoc_chdr_tdata,
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input wire s_rfnoc_chdr_tlast,
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input wire s_rfnoc_chdr_tvalid,
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output wire s_rfnoc_chdr_tready,
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// CHDR outputs to framework
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output wire [CHDR_W-1:0] m_rfnoc_chdr_tdata,
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output wire m_rfnoc_chdr_tlast,
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output wire m_rfnoc_chdr_tvalid,
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input wire m_rfnoc_chdr_tready,
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// Backend interface
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input wire [511:0] rfnoc_core_config,
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output wire [511:0] rfnoc_core_status,
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//---------------------------------------------------------------------------
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// AXIS CTRL Port
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//---------------------------------------------------------------------------
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input wire rfnoc_ctrl_clk,
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// CTRL port requests from framework
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input wire [31:0] s_rfnoc_ctrl_tdata,
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input wire s_rfnoc_ctrl_tlast,
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input wire s_rfnoc_ctrl_tvalid,
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output wire s_rfnoc_ctrl_tready,
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// CTRL port requests to framework
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output wire [31:0] m_rfnoc_ctrl_tdata,
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output wire m_rfnoc_ctrl_tlast,
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output wire m_rfnoc_ctrl_tvalid,
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input wire m_rfnoc_ctrl_tready
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);
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// These are the only supported values for now
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localparam ITEM_W = 32;
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localparam NIPC = 1;
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localparam NOC_ID = 32'hFF70_0000;
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`include "../../core/rfnoc_axis_ctrl_utils.vh"
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//---------------------------------------------------------------------------
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// Signal Declarations
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//---------------------------------------------------------------------------
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wire rfnoc_chdr_rst;
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wire ctrlport_req_wr;
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wire ctrlport_req_rd;
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wire [19:0] ctrlport_req_addr;
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wire [31:0] ctrlport_req_data;
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wire ctrlport_req_has_time;
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wire [63:0] ctrlport_req_time;
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wire ctrlport_resp_ack;
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wire [31:0] ctrlport_resp_data;
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wire [ITEM_W-1:0] axis_to_fft_tdata;
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wire axis_to_fft_tlast;
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wire axis_to_fft_tvalid;
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wire axis_to_fft_tready;
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wire [ITEM_W-1:0] axis_from_fft_tdata;
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wire axis_from_fft_tlast;
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wire axis_from_fft_tvalid;
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wire axis_from_fft_tready;
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wire [CHDR_W-1:0] m_axis_context_tdata;
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wire [ 3:0] m_axis_context_tuser;
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wire [ 0:0] m_axis_context_tlast;
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wire [ 0:0] m_axis_context_tvalid;
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wire [ 0:0] m_axis_context_tready;
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wire [CHDR_W-1:0] s_axis_context_tdata;
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wire [ 3:0] s_axis_context_tuser;
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wire [ 0:0] s_axis_context_tlast;
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wire [ 0:0] s_axis_context_tvalid;
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wire [ 0:0] s_axis_context_tready;
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wire ce_rst;
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// Cross the CHDR reset to the radio_clk domain
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pulse_synchronizer #(
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.MODE ("POSEDGE")
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) ctrl_rst_sync_i (
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.clk_a (rfnoc_chdr_clk),
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.rst_a (1'b0),
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.pulse_a (rfnoc_chdr_rst),
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.busy_a (),
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.clk_b (ce_clk),
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.pulse_b (ce_rst)
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);
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//---------------------------------------------------------------------------
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// NoC Shell
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//---------------------------------------------------------------------------
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noc_shell_fft #(
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.NOC_ID (NOC_ID ),
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.THIS_PORTID (THIS_PORTID),
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.CHDR_W (CHDR_W ),
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.CTRLPORT_SLV_EN(0 ),
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.CTRLPORT_MST_EN(1 ),
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.SYNC_CLKS (0 ),
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.NUM_DATA_I (1 ),
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.NUM_DATA_O (1 ),
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.ITEM_W (ITEM_W ),
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.NIPC (NIPC ),
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.PYLD_FIFO_SIZE (MTU ),
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.CTXT_FIFO_SIZE (1 ),
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.MTU (MTU )
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) noc_shell_fft_i (
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.rfnoc_chdr_clk (rfnoc_chdr_clk ),
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.rfnoc_chdr_rst (rfnoc_chdr_rst ),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
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.rfnoc_ctrl_rst ( ),
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.rfnoc_core_config (rfnoc_core_config ),
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.rfnoc_core_status (rfnoc_core_status ),
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.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata ),
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.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast ),
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.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid ),
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.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready ),
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.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata ),
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.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast ),
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.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid ),
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.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready ),
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.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata ),
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.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast ),
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.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid ),
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.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready ),
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.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata ),
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.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast ),
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.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid ),
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.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready ),
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.ctrlport_clk (ce_clk ),
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.ctrlport_rst (ce_rst ),
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.m_ctrlport_req_wr (ctrlport_req_wr ),
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.m_ctrlport_req_rd (ctrlport_req_rd ),
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.m_ctrlport_req_addr (ctrlport_req_addr ),
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.m_ctrlport_req_data (ctrlport_req_data ),
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.m_ctrlport_req_byte_en ( ),
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.m_ctrlport_req_has_time (ctrlport_req_has_time),
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.m_ctrlport_req_time (ctrlport_req_time ),
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.m_ctrlport_resp_ack (ctrlport_resp_ack ),
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.m_ctrlport_resp_status (AXIS_CTRL_STS_OKAY ),
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.m_ctrlport_resp_data (ctrlport_resp_data ),
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.s_ctrlport_req_wr (1'b0 ),
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.s_ctrlport_req_rd (1'b0 ),
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.s_ctrlport_req_addr (20'b0 ),
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.s_ctrlport_req_portid (10'b0 ),
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.s_ctrlport_req_rem_epid (16'b0 ),
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.s_ctrlport_req_rem_portid(10'b0 ),
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.s_ctrlport_req_data (32'b0 ),
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.s_ctrlport_req_byte_en (4'b0 ),
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.s_ctrlport_req_has_time (1'b0 ),
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.s_ctrlport_req_time (64'b0 ),
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.s_ctrlport_resp_ack ( ),
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.s_ctrlport_resp_status ( ),
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.s_ctrlport_resp_data ( ),
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.axis_data_clk (ce_clk ),
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.axis_data_rst (ce_rst ),
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.m_axis_payload_tdata (axis_to_fft_tdata ),
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.m_axis_payload_tkeep ( ),
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.m_axis_payload_tlast (axis_to_fft_tlast ),
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.m_axis_payload_tvalid (axis_to_fft_tvalid ),
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.m_axis_payload_tready (axis_to_fft_tready ),
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.s_axis_payload_tdata (axis_from_fft_tdata ),
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.s_axis_payload_tkeep ({1*NIPC{1'b1}} ),
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.s_axis_payload_tlast (axis_from_fft_tlast ),
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.s_axis_payload_tvalid (axis_from_fft_tvalid ),
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.s_axis_payload_tready (axis_from_fft_tready ),
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.m_axis_context_tdata (m_axis_context_tdata ),
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.m_axis_context_tuser (m_axis_context_tuser ),
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.m_axis_context_tlast (m_axis_context_tlast ),
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.m_axis_context_tvalid (m_axis_context_tvalid),
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.m_axis_context_tready (m_axis_context_tready),
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.s_axis_context_tdata (s_axis_context_tdata ),
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.s_axis_context_tuser (s_axis_context_tuser ),
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.s_axis_context_tlast (s_axis_context_tlast ),
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.s_axis_context_tvalid (s_axis_context_tvalid),
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.s_axis_context_tready (s_axis_context_tready)
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);
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// The input packets are the same configuration as the output packets, so
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// just use the header information for each incoming to create the header for
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// each outgoing packet. This is done by connecting m_axis_context to
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// directly to s_axis_context.
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assign s_axis_context_tdata = m_axis_context_tdata;
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assign s_axis_context_tuser = m_axis_context_tuser;
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assign s_axis_context_tlast = m_axis_context_tlast;
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assign s_axis_context_tvalid = m_axis_context_tvalid;
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assign m_axis_context_tready = s_axis_context_tready;
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wire [ 8-1:0] set_addr;
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wire [32-1:0] set_data;
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wire set_has_time;
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wire set_stb;
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wire [ 8-1:0] rb_addr;
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reg [64-1:0] rb_data;
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ctrlport_to_settings_bus # (
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.NUM_PORTS (1)
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) ctrlport_to_settings_bus_i (
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.ctrlport_clk (ce_clk),
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.ctrlport_rst (ce_rst),
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.s_ctrlport_req_wr (ctrlport_req_wr),
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.s_ctrlport_req_rd (ctrlport_req_rd),
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.s_ctrlport_req_addr (ctrlport_req_addr),
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.s_ctrlport_req_data (ctrlport_req_data),
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.s_ctrlport_req_has_time (ctrlport_req_has_time),
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.s_ctrlport_req_time (ctrlport_req_time),
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.s_ctrlport_resp_ack (ctrlport_resp_ack),
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.s_ctrlport_resp_data (ctrlport_resp_data),
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.set_data (set_data),
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.set_addr (set_addr),
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.set_stb (set_stb),
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.set_time (),
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.set_has_time (set_has_time),
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.rb_stb (1'b1),
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.rb_addr (rb_addr),
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.rb_data (rb_data));
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localparam MAX_FFT_SIZE_LOG2 = 11;
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localparam [31:0] SR_FFT_RESET = 131;
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localparam [31:0] SR_FFT_SIZE_LOG2 = 132;
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localparam [31:0] SR_MAGNITUDE_OUT = 133;
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localparam [31:0] SR_FFT_DIRECTION = 134;
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localparam [31:0] SR_FFT_SCALING = 135;
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localparam [31:0] SR_FFT_SHIFT_CONFIG = 136;
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// FFT Output
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localparam [1:0] COMPLEX_OUT = 0;
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localparam [1:0] MAG_OUT = 1;
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localparam [1:0] MAG_SQ_OUT = 2;
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// FFT Direction
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localparam [0:0] FFT_REVERSE = 0;
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localparam [0:0] FFT_FORWARD = 1;
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wire [1:0] magnitude_out;
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wire [31:0] fft_data_o_tdata;
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wire fft_data_o_tlast;
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wire fft_data_o_tvalid;
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wire fft_data_o_tready;
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wire [15:0] fft_data_o_tuser;
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wire [31:0] fft_shift_o_tdata;
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wire fft_shift_o_tlast;
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wire fft_shift_o_tvalid;
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wire fft_shift_o_tready;
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wire [31:0] fft_mag_i_tdata, fft_mag_o_tdata, fft_mag_o_tdata_int;
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wire fft_mag_i_tlast, fft_mag_o_tlast;
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wire fft_mag_i_tvalid, fft_mag_o_tvalid;
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wire fft_mag_i_tready, fft_mag_o_tready;
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wire [31:0] fft_mag_sq_i_tdata, fft_mag_sq_o_tdata;
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wire fft_mag_sq_i_tlast, fft_mag_sq_o_tlast;
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wire fft_mag_sq_i_tvalid, fft_mag_sq_o_tvalid;
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wire fft_mag_sq_i_tready, fft_mag_sq_o_tready;
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wire [31:0] fft_mag_round_i_tdata, fft_mag_round_o_tdata;
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wire fft_mag_round_i_tlast, fft_mag_round_o_tlast;
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wire fft_mag_round_i_tvalid, fft_mag_round_o_tvalid;
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wire fft_mag_round_i_tready, fft_mag_round_o_tready;
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// Settings Registers
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wire fft_reset;
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setting_reg #(
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.my_addr(SR_FFT_RESET), .awidth(8), .width(1))
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sr_fft_reset (
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.clk(ce_clk), .rst(ce_rst),
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.strobe(set_stb), .addr(set_addr), .in(set_data), .out(fft_reset), .changed());
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// Two instances of FFT size register, one for FFT core and one for FFT shift
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||||
localparam DEFAULT_FFT_SIZE = 8; // 256
|
||||
wire [7:0] fft_size_log2_tdata ,fft_core_size_log2_tdata;
|
||||
wire fft_size_log2_tvalid, fft_core_size_log2_tvalid, fft_size_log2_tready, fft_core_size_log2_tready;
|
||||
axi_setting_reg #(
|
||||
.ADDR(SR_FFT_SIZE_LOG2), .AWIDTH(8), .WIDTH(8), .DATA_AT_RESET(DEFAULT_FFT_SIZE), .VALID_AT_RESET(1))
|
||||
sr_fft_size_log2 (
|
||||
.clk(ce_clk), .reset(ce_rst),
|
||||
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
|
||||
.o_tdata(fft_size_log2_tdata), .o_tlast(), .o_tvalid(fft_size_log2_tvalid), .o_tready(fft_size_log2_tready));
|
||||
|
||||
axi_setting_reg #(
|
||||
.ADDR(SR_FFT_SIZE_LOG2), .AWIDTH(8), .WIDTH(8), .DATA_AT_RESET(DEFAULT_FFT_SIZE), .VALID_AT_RESET(1))
|
||||
sr_fft_size_log2_2 (
|
||||
.clk(ce_clk), .reset(ce_rst),
|
||||
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
|
||||
.o_tdata(fft_core_size_log2_tdata), .o_tlast(), .o_tvalid(fft_core_size_log2_tvalid), .o_tready(fft_core_size_log2_tready));
|
||||
|
||||
// Forward = 0, Reverse = 1
|
||||
localparam DEFAULT_FFT_DIRECTION = 0;
|
||||
wire fft_direction_tdata;
|
||||
wire fft_direction_tvalid, fft_direction_tready;
|
||||
axi_setting_reg #(
|
||||
.ADDR(SR_FFT_DIRECTION), .AWIDTH(8), .WIDTH(1), .DATA_AT_RESET(DEFAULT_FFT_DIRECTION), .VALID_AT_RESET(1))
|
||||
sr_fft_direction (
|
||||
.clk(ce_clk), .reset(ce_rst),
|
||||
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
|
||||
.o_tdata(fft_direction_tdata), .o_tlast(), .o_tvalid(fft_direction_tvalid), .o_tready(fft_direction_tready));
|
||||
|
||||
localparam [11:0] DEFAULT_FFT_SCALING = 12'b011010101010; // Conservative 1/N scaling
|
||||
wire [11:0] fft_scaling_tdata;
|
||||
wire fft_scaling_tvalid, fft_scaling_tready;
|
||||
axi_setting_reg #(
|
||||
.ADDR(SR_FFT_SCALING), .AWIDTH(8), .WIDTH(12), .DATA_AT_RESET(DEFAULT_FFT_SCALING), .VALID_AT_RESET(1))
|
||||
sr_fft_scaling (
|
||||
.clk(ce_clk), .reset(ce_rst),
|
||||
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
|
||||
.o_tdata(fft_scaling_tdata), .o_tlast(), .o_tvalid(fft_scaling_tvalid), .o_tready(fft_scaling_tready));
|
||||
|
||||
wire [1:0] fft_shift_config_tdata;
|
||||
wire fft_shift_config_tvalid, fft_shift_config_tready;
|
||||
axi_setting_reg #(
|
||||
.ADDR(SR_FFT_SHIFT_CONFIG), .AWIDTH(8), .WIDTH(2))
|
||||
sr_fft_shift_config (
|
||||
.clk(ce_clk), .reset(ce_rst),
|
||||
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
|
||||
.o_tdata(fft_shift_config_tdata), .o_tlast(), .o_tvalid(fft_shift_config_tvalid), .o_tready(fft_shift_config_tready));
|
||||
|
||||
// Synchronize writing configuration to the FFT core
|
||||
reg fft_config_ready;
|
||||
wire fft_config_write = fft_config_ready & axis_to_fft_tvalid & axis_to_fft_tready;
|
||||
always @(posedge ce_clk) begin
|
||||
if (ce_rst | fft_reset) begin
|
||||
fft_config_ready <= 1'b1;
|
||||
end else begin
|
||||
if (fft_config_write) begin
|
||||
fft_config_ready <= 1'b0;
|
||||
end else if (axis_to_fft_tlast) begin
|
||||
fft_config_ready <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [23:0] fft_config_tdata = {3'd0, fft_scaling_tdata, fft_direction_tdata, fft_core_size_log2_tdata};
|
||||
wire fft_config_tvalid = fft_config_write & (fft_scaling_tvalid | fft_direction_tvalid | fft_core_size_log2_tvalid);
|
||||
wire fft_config_tready;
|
||||
assign fft_core_size_log2_tready = fft_config_tready & fft_config_write;
|
||||
assign fft_direction_tready = fft_config_tready & fft_config_write;
|
||||
assign fft_scaling_tready = fft_config_tready & fft_config_write;
|
||||
axi_fft inst_axi_fft (
|
||||
.aclk(ce_clk), .aresetn(~(fft_reset)),
|
||||
.s_axis_data_tvalid(axis_to_fft_tvalid),
|
||||
.s_axis_data_tready(axis_to_fft_tready),
|
||||
.s_axis_data_tlast(axis_to_fft_tlast),
|
||||
.s_axis_data_tdata({axis_to_fft_tdata[15:0],axis_to_fft_tdata[31:16]}),
|
||||
.m_axis_data_tvalid(fft_data_o_tvalid),
|
||||
.m_axis_data_tready(fft_data_o_tready),
|
||||
.m_axis_data_tlast(fft_data_o_tlast),
|
||||
.m_axis_data_tdata({fft_data_o_tdata[15:0],fft_data_o_tdata[31:16]}),
|
||||
.m_axis_data_tuser(fft_data_o_tuser), // FFT index
|
||||
.s_axis_config_tdata(fft_config_tdata),
|
||||
.s_axis_config_tvalid(fft_config_tvalid),
|
||||
.s_axis_config_tready(fft_config_tready),
|
||||
.event_frame_started(),
|
||||
.event_tlast_unexpected(),
|
||||
.event_tlast_missing(),
|
||||
.event_status_channel_halt(),
|
||||
.event_data_in_channel_halt(),
|
||||
.event_data_out_channel_halt());
|
||||
|
||||
// Mux control signals
|
||||
assign fft_shift_o_tready = (magnitude_out == MAG_OUT) ? fft_mag_i_tready :
|
||||
(magnitude_out == MAG_SQ_OUT) ? fft_mag_sq_i_tready : axis_from_fft_tready;
|
||||
assign fft_mag_i_tvalid = (magnitude_out == MAG_OUT) ? fft_shift_o_tvalid : 1'b0;
|
||||
assign fft_mag_i_tlast = (magnitude_out == MAG_OUT) ? fft_shift_o_tlast : 1'b0;
|
||||
assign fft_mag_i_tdata = fft_shift_o_tdata;
|
||||
assign fft_mag_o_tready = (magnitude_out == MAG_OUT) ? fft_mag_round_i_tready : 1'b0;
|
||||
assign fft_mag_sq_i_tvalid = (magnitude_out == MAG_SQ_OUT) ? fft_shift_o_tvalid : 1'b0;
|
||||
assign fft_mag_sq_i_tlast = (magnitude_out == MAG_SQ_OUT) ? fft_shift_o_tlast : 1'b0;
|
||||
assign fft_mag_sq_i_tdata = fft_shift_o_tdata;
|
||||
assign fft_mag_sq_o_tready = (magnitude_out == MAG_SQ_OUT) ? fft_mag_round_i_tready : 1'b0;
|
||||
assign fft_mag_round_i_tvalid = (magnitude_out == MAG_OUT) ? fft_mag_o_tvalid :
|
||||
(magnitude_out == MAG_SQ_OUT) ? fft_mag_sq_o_tvalid : 1'b0;
|
||||
assign fft_mag_round_i_tlast = (magnitude_out == MAG_OUT) ? fft_mag_o_tlast :
|
||||
(magnitude_out == MAG_SQ_OUT) ? fft_mag_sq_o_tlast : 1'b0;
|
||||
assign fft_mag_round_i_tdata = (magnitude_out == MAG_OUT) ? fft_mag_o_tdata : fft_mag_sq_o_tdata;
|
||||
assign fft_mag_round_o_tready = axis_from_fft_tready;
|
||||
assign axis_from_fft_tvalid = (magnitude_out == MAG_OUT | magnitude_out == MAG_SQ_OUT) ? fft_mag_round_o_tvalid : fft_shift_o_tvalid;
|
||||
assign axis_from_fft_tlast = (magnitude_out == MAG_OUT | magnitude_out == MAG_SQ_OUT) ? fft_mag_round_o_tlast : fft_shift_o_tlast;
|
||||
assign axis_from_fft_tdata = (magnitude_out == MAG_OUT | magnitude_out == MAG_SQ_OUT) ? fft_mag_round_o_tdata : fft_shift_o_tdata;
|
||||
|
||||
// Conditionally synth magnitude / magnitude^2 logic
|
||||
generate
|
||||
if (EN_MAGNITUDE_OUT | EN_MAGNITUDE_APPROX_OUT | EN_MAGNITUDE_SQ_OUT) begin : generate_magnitude_out
|
||||
setting_reg #(
|
||||
.my_addr(SR_MAGNITUDE_OUT), .awidth(8), .width(2))
|
||||
sr_magnitude_out (
|
||||
.clk(ce_clk), .rst(ce_rst),
|
||||
.strobe(set_stb), .addr(set_addr), .in(set_data), .out(magnitude_out), .changed());
|
||||
end else begin : generate_magnitude_out_else
|
||||
// Magnitude calculation logic not included, so always bypass
|
||||
assign magnitude_out = 2'd0;
|
||||
end
|
||||
|
||||
if (EN_FFT_SHIFT) begin : generate_fft_shift
|
||||
fft_shift #(
|
||||
.MAX_FFT_SIZE_LOG2(MAX_FFT_SIZE_LOG2),
|
||||
.WIDTH(32))
|
||||
inst_fft_shift (
|
||||
.clk(ce_clk), .reset(ce_rst | fft_reset),
|
||||
.config_tdata(fft_shift_config_tdata),
|
||||
.config_tvalid(fft_shift_config_tvalid),
|
||||
.config_tready(fft_shift_config_tready),
|
||||
.fft_size_log2_tdata(fft_size_log2_tdata[$clog2(MAX_FFT_SIZE_LOG2)-1:0]),
|
||||
.fft_size_log2_tvalid(fft_size_log2_tvalid),
|
||||
.fft_size_log2_tready(fft_size_log2_tready),
|
||||
.i_tdata(fft_data_o_tdata),
|
||||
.i_tlast(fft_data_o_tlast),
|
||||
.i_tvalid(fft_data_o_tvalid),
|
||||
.i_tready(fft_data_o_tready),
|
||||
.i_tuser(fft_data_o_tuser[MAX_FFT_SIZE_LOG2-1:0]),
|
||||
.o_tdata(fft_shift_o_tdata),
|
||||
.o_tlast(fft_shift_o_tlast),
|
||||
.o_tvalid(fft_shift_o_tvalid),
|
||||
.o_tready(fft_shift_o_tready));
|
||||
end
|
||||
else begin : generate_fft_shift_else
|
||||
assign fft_shift_o_tdata = fft_data_o_tdata;
|
||||
assign fft_shift_o_tlast = fft_data_o_tlast;
|
||||
assign fft_shift_o_tvalid = fft_data_o_tvalid;
|
||||
assign fft_data_o_tready = fft_shift_o_tready;
|
||||
end
|
||||
|
||||
// More accurate magnitude calculation takes precedence if enabled
|
||||
if (EN_MAGNITUDE_OUT) begin : generate_complex_to_magphase
|
||||
complex_to_magphase
|
||||
inst_complex_to_magphase (
|
||||
.aclk(ce_clk), .aresetn(~(ce_rst | fft_reset)),
|
||||
.s_axis_cartesian_tvalid(fft_mag_i_tvalid),
|
||||
.s_axis_cartesian_tlast(fft_mag_i_tlast),
|
||||
.s_axis_cartesian_tready(fft_mag_i_tready),
|
||||
.s_axis_cartesian_tdata(fft_mag_i_tdata),
|
||||
.m_axis_dout_tvalid(fft_mag_o_tvalid),
|
||||
.m_axis_dout_tlast(fft_mag_o_tlast),
|
||||
.m_axis_dout_tdata(fft_mag_o_tdata_int),
|
||||
.m_axis_dout_tready(fft_mag_o_tready));
|
||||
assign fft_mag_o_tdata = {1'b0, fft_mag_o_tdata_int[15:0], 15'd0};
|
||||
end
|
||||
else if (EN_MAGNITUDE_APPROX_OUT) begin : generate_complex_to_mag_approx
|
||||
complex_to_mag_approx
|
||||
inst_complex_to_mag_approx (
|
||||
.clk(ce_clk), .reset(ce_rst | fft_reset), .clear(1'b0),
|
||||
.i_tvalid(fft_mag_i_tvalid),
|
||||
.i_tlast(fft_mag_i_tlast),
|
||||
.i_tready(fft_mag_i_tready),
|
||||
.i_tdata(fft_mag_i_tdata),
|
||||
.o_tvalid(fft_mag_o_tvalid),
|
||||
.o_tlast(fft_mag_o_tlast),
|
||||
.o_tready(fft_mag_o_tready),
|
||||
.o_tdata(fft_mag_o_tdata_int[15:0]));
|
||||
assign fft_mag_o_tdata = {1'b0, fft_mag_o_tdata_int[15:0], 15'd0};
|
||||
end
|
||||
else begin : generate_complex_to_mag_approx_else
|
||||
assign fft_mag_o_tdata = fft_mag_i_tdata;
|
||||
assign fft_mag_o_tlast = fft_mag_i_tlast;
|
||||
assign fft_mag_o_tvalid = fft_mag_i_tvalid;
|
||||
assign fft_mag_i_tready = fft_mag_o_tready;
|
||||
end
|
||||
|
||||
if (EN_MAGNITUDE_SQ_OUT) begin : generate_complex_to_magsq
|
||||
complex_to_magsq
|
||||
inst_complex_to_magsq (
|
||||
.clk(ce_clk), .reset(ce_rst | fft_reset), .clear(1'b0),
|
||||
.i_tvalid(fft_mag_sq_i_tvalid),
|
||||
.i_tlast(fft_mag_sq_i_tlast),
|
||||
.i_tready(fft_mag_sq_i_tready),
|
||||
.i_tdata(fft_mag_sq_i_tdata),
|
||||
.o_tvalid(fft_mag_sq_o_tvalid),
|
||||
.o_tlast(fft_mag_sq_o_tlast),
|
||||
.o_tready(fft_mag_sq_o_tready),
|
||||
.o_tdata(fft_mag_sq_o_tdata));
|
||||
end
|
||||
else begin : generate_complex_to_magsq_else
|
||||
assign fft_mag_sq_o_tdata = fft_mag_sq_i_tdata;
|
||||
assign fft_mag_sq_o_tlast = fft_mag_sq_i_tlast;
|
||||
assign fft_mag_sq_o_tvalid = fft_mag_sq_i_tvalid;
|
||||
assign fft_mag_sq_i_tready = fft_mag_sq_o_tready;
|
||||
end
|
||||
|
||||
// Convert to SC16
|
||||
if (EN_MAGNITUDE_OUT | EN_MAGNITUDE_APPROX_OUT | EN_MAGNITUDE_SQ_OUT) begin : generate_axi_round_and_clip
|
||||
axi_round_and_clip #(
|
||||
.WIDTH_IN(32),
|
||||
.WIDTH_OUT(16),
|
||||
.CLIP_BITS(1))
|
||||
inst_axi_round_and_clip (
|
||||
.clk(ce_clk), .reset(ce_rst | fft_reset),
|
||||
.i_tdata(fft_mag_round_i_tdata),
|
||||
.i_tlast(fft_mag_round_i_tlast),
|
||||
.i_tvalid(fft_mag_round_i_tvalid),
|
||||
.i_tready(fft_mag_round_i_tready),
|
||||
.o_tdata(fft_mag_round_o_tdata[31:16]),
|
||||
.o_tlast(fft_mag_round_o_tlast),
|
||||
.o_tvalid(fft_mag_round_o_tvalid),
|
||||
.o_tready(fft_mag_round_o_tready));
|
||||
assign fft_mag_round_o_tdata[15:0] = {16{16'd0}};
|
||||
end
|
||||
else begin : generate_axi_round_and_clip_else
|
||||
assign fft_mag_round_o_tdata = fft_mag_round_i_tdata;
|
||||
assign fft_mag_round_o_tlast = fft_mag_round_i_tlast;
|
||||
assign fft_mag_round_o_tvalid = fft_mag_round_i_tvalid;
|
||||
assign fft_mag_round_i_tready = fft_mag_round_o_tready;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Readback registers
|
||||
always @*
|
||||
case(rb_addr)
|
||||
3'd0 : rb_data <= {63'd0, fft_reset};
|
||||
3'd1 : rb_data <= {62'd0, magnitude_out};
|
||||
3'd2 : rb_data <= {fft_size_log2_tdata};
|
||||
3'd3 : rb_data <= {63'd0, fft_direction_tdata};
|
||||
3'd4 : rb_data <= {52'd0, fft_scaling_tdata};
|
||||
3'd5 : rb_data <= {62'd0, fft_shift_config_tdata};
|
||||
default : rb_data <= 64'h0BADC0DE0BADC0DE;
|
||||
endcase
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user