Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
This commit is contained in:
Martin Braun
co-authored by
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
Alex Williams
Andrej Rode
Ashish Chaudhari
Ben Hilburn
Ciro Nishiguchi
Daniel Jepson
Derek Kozel
EJ Kreinar
Humberto Jimenez
Ian Buckley
Jörg Hofrichter
Jon Kiser
Josh Blum
Jonathon Pendlum
Matt Ettus
Michael West
Moritz Fischer
Nick Foster
Nicolas Cuervo
Paul Butler
Paul David
Ryan Marlow
Sugandha Gupta
Sylvain Munaut
Trung Tran
Vidush Vishwanath
Wade Fife
parent
74893643ca
commit
6b67702ad7
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//
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// Copyright 2018 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axis_shift_register
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// Description:
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// This module implements a chain of flip-flops in connected
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// using AXI-Stream. It can be used in the following ways:
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// * As a AXI-Stream shift register. The tready path is
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// combinatorial from the output to the input so backpressure
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// is immediate. The same behavior makes this module non-ideal
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// to actually break timing critical paths.
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// * An AXI-Stream wrapper module for a multi-cycle operation
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// with clock-enables. This can most commonly be used with DSP
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// operations like filters. Enable the sideband datapath to
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// let the module handle handshaking while processing samples
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// outside it.
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//
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// Parameters:
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// - WIDTH: The bitwidth of a sample on the data bus.
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// - NSPC: The number of parallel samples per cycle to process. The
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// total width of the data bus will be WIDTH*NSPC.
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// - LATENCY: Number of stages in the shift register
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// - SIDEBAND_DATAPATH: If SIDEBAND_DATAPATH==1 then tdata is managed
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// outside this module and imported from s_sideband_data.
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// If SIDEBAND_DATAPATH=0, then tdata is managed internally and
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// the sideband signals are unused.
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// Useful when using this module to manage a DSP pipeline where the
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// data could be changing in each stage.
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// - GAPLESS: After the shift register has filled up, should gaps be
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// allowed? If set to 1, then if s_axis_tvalid goes low then the
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// pipeline will stall and all bits in stage_stb will immediately go low
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// to ensure all stages in the shift register have valid data.
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// NOTE: This GAPLESS=1 will not allow the final "LATENCY" samples
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// to exit the shift register.
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// - PIPELINE: Which ports to pipeline? {NONE, IN, OUT, INOUT}
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//
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// Signals:
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// - s_axis_* : Input sample stream (AXI-Stream)
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// - m_axis_* : Output sample stream (AXI-Stream)
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// - stage_stb : Transfer strobe for each stage
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// - stage_eop : Transfer end-of-packet out. bit[i] = stage[i]
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// - m_sideband_data : Sideband data out for external consumer
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// - m_sideband_keep : Sideband keep signal out for external consumer
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// - s_sideband_data : Sideband data in from external producer
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module axis_shift_register #(
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parameter WIDTH = 32,
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parameter NSPC = 1,
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parameter LATENCY = 3,
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parameter SIDEBAND_DATAPATH = 0,
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parameter GAPLESS = 0,
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parameter PIPELINE = "NONE"
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)(
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// Clock, reset and settings
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input wire clk, // Clock
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input wire reset, // Reset
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// Serial Data In (AXI-Stream)
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input wire [(WIDTH*NSPC)-1:0] s_axis_tdata, // Input stream tdata
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input wire [NSPC-1:0] s_axis_tkeep, // Input stream tkeep (used as a sample qualifier)
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input wire s_axis_tlast, // Input stream tlast
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input wire s_axis_tvalid, // Input stream tvalid
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output wire s_axis_tready, // Input stream tready
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// Serial Data Out (AXI-Stream)
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output wire [(WIDTH*NSPC)-1:0] m_axis_tdata, // Output stream tdata
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output wire [NSPC-1:0] m_axis_tkeep, // Output stream tkeep (used as a sample qualifier)
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output wire m_axis_tlast, // Output stream tlast
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output wire m_axis_tvalid, // Output stream tvalid
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input wire m_axis_tready, // Output stream tready
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// Signals for the sideband data path
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output wire [LATENCY-1:0] stage_stb, // Transfer strobe out. bit[i] = stage[i]
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output wire [LATENCY-1:0] stage_eop, // Transfer end-of-packet out. bit[i] = stage[i]
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output wire [(WIDTH*NSPC)-1:0] m_sideband_data, // Sideband data out for external consumer
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output wire [NSPC-1:0] m_sideband_keep, // Sideband keep signal out for external consumer
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input wire [(WIDTH*NSPC)-1:0] s_sideband_data // Sideband data in from external producer
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);
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// Shift register width depends on whether the datapath is internal
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localparam SHREG_WIDTH = SIDEBAND_DATAPATH[0] ? (NSPC + 1) : ((WIDTH*NSPC) + NSPC + 1);
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localparam SHREG_TLAST_LOC = SHREG_WIDTH-1;
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localparam SHREG_TKEEP_HI = SHREG_WIDTH-2;
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localparam SHREG_TKEEP_LO = SHREG_WIDTH-NSPC-1;
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//----------------------------------------------
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// Pipeline Logic
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// (fifo_flop2 is used because it breaks timing
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// path going both ways: valid and ready)
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//----------------------------------------------
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wire [(WIDTH*NSPC)-1:0] i_tdata, o_tdata;
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wire [NSPC-1:0] i_tkeep, o_tkeep;
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wire i_tlast, o_tlast;
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wire i_tvalid, o_tvalid;
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wire i_tready, o_tready;
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generate
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// Input pipeline register if requested
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if (PIPELINE == "IN" || PIPELINE == "INOUT") begin
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axi_fifo_flop2 #(.WIDTH((WIDTH*NSPC) + NSPC + 1)) in_pipe_i (
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.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata({s_axis_tlast, s_axis_tkeep, s_axis_tdata}),
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.i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready),
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.o_tdata({i_tlast, i_tkeep, i_tdata}), .o_tvalid(i_tvalid), .o_tready(i_tready),
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.space(), .occupied()
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);
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end else begin
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assign {i_tlast, i_tkeep, i_tdata} = {s_axis_tlast, s_axis_tkeep, s_axis_tdata};
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assign i_tvalid = s_axis_tvalid;
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assign s_axis_tready = i_tready;
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end
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// Output pipeline register if requested
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if (PIPELINE == "OUT" || PIPELINE == "INOUT") begin
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axi_fifo_flop2 #(.WIDTH((WIDTH*NSPC) + NSPC + 1)) out_pipe_i (
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.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata({o_tlast, o_tkeep, o_tdata}), .i_tvalid(o_tvalid), .i_tready(o_tready),
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.o_tdata({m_axis_tlast, m_axis_tkeep, m_axis_tdata}),
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.o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready),
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.space(), .occupied()
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);
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end else begin
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assign {m_axis_tlast, m_axis_tkeep, m_axis_tdata} = {o_tlast, o_tkeep, o_tdata};
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assign m_axis_tvalid = o_tvalid;
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assign o_tready = m_axis_tready;
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end
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endgenerate
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assign m_sideband_data = i_tdata;
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assign m_sideband_keep = i_tkeep;
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//----------------------------------------------
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// Shift register stages
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//----------------------------------------------
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genvar i;
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generate
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if (GAPLESS == 0) begin
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// Individual stage wires
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wire [SHREG_WIDTH-1:0] stg_tdata [0:LATENCY];
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wire stg_tvalid[0:LATENCY];
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wire stg_tready[0:LATENCY];
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// Shift register input
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assign stg_tdata[0] = SIDEBAND_DATAPATH[0] ? {i_tlast, i_tkeep} : {i_tlast, i_tkeep, i_tdata};
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assign stg_tvalid[0] = i_tvalid;
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assign i_tready = stg_tready[0];
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// Shift register output
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assign o_tlast = stg_tdata[LATENCY][SHREG_TLAST_LOC];
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assign o_tkeep = stg_tdata[LATENCY][SHREG_TKEEP_HI:SHREG_TKEEP_LO];
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assign o_tdata = SIDEBAND_DATAPATH[0] ? s_sideband_data : stg_tdata[LATENCY][(WIDTH*NSPC)-1:0];
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assign o_tvalid = stg_tvalid[LATENCY];
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assign stg_tready[LATENCY] = o_tready;
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for (i = 0; i < LATENCY; i=i+1) begin: stages
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axi_fifo_flop #(.WIDTH(SHREG_WIDTH)) reg_i (
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.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata(stg_tdata[i ]), .i_tvalid(stg_tvalid[i ]), .i_tready(stg_tready[i ]),
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.o_tdata(stg_tdata[i+1]), .o_tvalid(stg_tvalid[i+1]), .o_tready(stg_tready[i+1]),
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.occupied(), .space()
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);
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assign stage_stb[i] = stg_tvalid[i] & stg_tready[i];
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assign stage_eop[i] = stage_stb[i] & stg_tdata[i][SHREG_TLAST_LOC];
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end
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end else begin // if (GAPLESS == 0)
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wire [(WIDTH*NSPC)-1:0] o_tdata_fifo;
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wire [NSPC-1:0] o_tkeep_fifo;
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wire o_tlast_fifo, o_tvalid_fifo, o_tready_fifo;
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// Shift register to hold valids
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reg [LATENCY-1:0] stage_valid = {LATENCY{1'b0}};
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// Shift register to hold data/last
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reg [SHREG_WIDTH-1:0] stage_shreg[0:LATENCY-1];
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wire [SHREG_WIDTH-1:0] shreg_input = SIDEBAND_DATAPATH[0] ? {i_tlast, i_tkeep} : {i_tlast, i_tkeep, i_tdata};
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wire shreg_ce = i_tready & i_tvalid;
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assign i_tready = o_tready_fifo;
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assign o_tvalid_fifo = stage_valid[LATENCY-1] & shreg_ce;
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assign o_tlast_fifo = stage_shreg[LATENCY-1][SHREG_TLAST_LOC];
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assign o_tkeep_fifo = stage_shreg[LATENCY-1][SHREG_TKEEP_HI:SHREG_TKEEP_LO];
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assign o_tdata_fifo = SIDEBAND_DATAPATH[0] ? s_sideband_data : stage_shreg[LATENCY-1][(WIDTH*NSPC)-1:0];
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for (i = 0; i < LATENCY; i=i+1) begin
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// Initialize shift register
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initial begin
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stage_shreg[i] <= {SHREG_WIDTH{1'b0}};
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end
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// Shift register logic
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always @(posedge clk) begin
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if (reset) begin
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stage_shreg[i] <= {SHREG_WIDTH{1'b0}};
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stage_valid[i] <= 1'b0;
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end else if (shreg_ce) begin
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stage_shreg[i] <= (i == 0) ? shreg_input : stage_shreg[i-1];
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stage_valid[i] <= (i == 0) ? 1'b1 : stage_valid[i-1];
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end
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end
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// Outputs
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assign stage_stb[i] = ((i == 0) ? 1'b1 : stage_valid[i-1]) & shreg_ce;
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assign stage_eop[i] = stage_stb[i] & ((i == 0) ? i_tlast : stage_shreg[i-1][SHREG_TLAST_LOC]);
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end
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// The "gapless" logic violates AXI-Stream by having an o_tready -> o_tvalid dependency,
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// so we add a FIFO downstream to prevent deadlocks.
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axi_fifo #(.WIDTH((WIDTH*NSPC) + NSPC + 1), .SIZE($clog2(LATENCY))) out_fifo_i (
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.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata({o_tlast_fifo, o_tkeep_fifo, o_tdata_fifo}), .i_tvalid(o_tvalid_fifo), .i_tready(o_tready_fifo),
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.o_tdata({o_tlast, o_tkeep, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
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.space(), .occupied()
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);
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end
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endgenerate
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endmodule // axis_shift_register
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