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fpga: tools: Add ip target to simulation makefiles

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Allow building of just the IP by running "make ip" in simulation
directories.


Original-commit: 4dc2b7010c0f3e41758b8192636ef7672caae0f7
This commit is contained in:
Wade Fife
2021-06-17 08:16:59 -05:00
parent fd8c814f6f
commit 69a7abba4d
1 changed files with 5 additions and 2 deletions
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tools/make/viv_simulator.mak
+5 -2
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@@ -86,6 +86,9 @@ SETUP_AND_LAUNCH_MODELSIM = \
.SECONDEXPANSION: .SECONDEXPANSION:
##ip: Generate the IP required for this simulation
ip: $(DESIGN_SRCS)
##xsim: Run the simulation using the Xilinx Vivado Simulator ##xsim: Run the simulation using the Xilinx Vivado Simulator
xsim: .check_tool $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS) xsim: .check_tool $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS)
$(call SETUP_AND_LAUNCH_SIMULATION,XSim) $(call SETUP_AND_LAUNCH_SIMULATION,XSim)
@@ -111,7 +114,7 @@ modelsim: .check_tool vlint
# NOTE: VHDL files require a correct compile order. This script compiles files # NOTE: VHDL files require a correct compile order. This script compiles files
# in the order they are defined in $(DESIGN_SRC), then $SIM_SRC) # in the order they are defined in $(DESIGN_SRC), then $SIM_SRC)
##vlint: Run ModelSim compiler to lint files. ##vlint: Run ModelSim compiler to lint files
vlint: .check_tool $(COMPLIBDIR) $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS) vlint: .check_tool $(COMPLIBDIR) $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS)
$(call SETUP_AND_LAUNCH_VLINT) $(call SETUP_AND_LAUNCH_VLINT)
@@ -127,4 +130,4 @@ clean:: xclean vclean
help:: help::
@grep -h "##" $(abspath $(lastword $(MAKEFILE_LIST))) | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' @grep -h "##" $(abspath $(lastword $(MAKEFILE_LIST))) | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
.PHONY: xsim xsim_hls xclean vsim vlint vclean clean help .PHONY: ip xsim xsim_hls xclean vsim vlint vclean clean help