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fpga: Use PROTOVER and CHDR_W from RFNoC image builder

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This updates all RFNoC devices so that they get the RFNoC protocol
version and CHDR width in the same way, from the output generated by
the RFNoC image builder.


Original-commit: 6f038dc2f69b38e715206b2e700fdd3a1bbc638e
This commit is contained in:
Wade Fife
2022-03-29 14:45:04 -05:00
parent a0987ea0f8
commit 61ee0ddec3
13 changed files with 113 additions and 27 deletions
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top/n3xx/dboards/mg/n3xx.v
+18 -1
View File
@@ -315,6 +315,22 @@ module n3xx (
`endif
);
// Include the RFNoC image core header file
`ifdef RFNOC_IMAGE_CORE_HDR
`include `"`RFNOC_IMAGE_CORE_HDR`"
`else
ERROR_RFNOC_IMAGE_CORE_HDR_not_defined();
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
`endif
localparam CHDR_W = `CHDR_WIDTH;
localparam RFNOC_PROTOVER = `RFNOC_PROTOVER;
// This USRP currently only supports 64-bit CHDR width
if (CHDR_W != 64) begin : gen_chdr_w_error
CHDR_W_must_be_64_for_this_USRP();
end
localparam N_AXILITE_SLAVES = 4;
localparam REG_AWIDTH = 14; // log2(0x4000)
localparam QSFP_REG_AWIDTH = 17; // log2(0x20000)
@@ -332,7 +348,6 @@ module n3xx (
localparam NUM_DBOARDS = 1;
`endif
localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO;
localparam [15:0] RFNOC_PROTOVER = {8'd1, 8'd0};
// Internal connections to PS
// HP0 -- High Performance port 0, FPGA is the master
@@ -3517,6 +3532,8 @@ module n3xx (
.NUM_CHANNELS_PER_RADIO(NUM_CHANNELS_PER_RADIO),
.NUM_CHANNELS(NUM_CHANNELS),
.NUM_DBOARDS(NUM_DBOARDS),
.CHDR_W(CHDR_W),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
`ifdef USE_REPLAY
.USE_REPLAY(1)
`else
top/n3xx/dboards/rh/n3xx.v
+18 -1
View File
@@ -307,6 +307,22 @@ module n3xx (
output DBB_LED_TX
);
// Include the RFNoC image core header file
`ifdef RFNOC_IMAGE_CORE_HDR
`include `"`RFNOC_IMAGE_CORE_HDR`"
`else
ERROR_RFNOC_IMAGE_CORE_HDR_not_defined();
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
`endif
localparam CHDR_W = `CHDR_WIDTH;
localparam RFNOC_PROTOVER = `RFNOC_PROTOVER;
// This USRP currently only supports 64-bit CHDR width
if (CHDR_W != 64) begin : gen_chdr_w_error
CHDR_W_must_be_64_for_this_USRP();
end
localparam N_AXILITE_SLAVES = 4;
localparam REG_AWIDTH = 14; // log2(0x4000)
localparam QSFP_REG_AWIDTH = 17; // log2(0x20000)
@@ -320,7 +336,6 @@ module n3xx (
localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO;
localparam CHANNEL_WIDTH = 32;
// Internal connections to PS
// HP0 -- High Performance port 0, FPGA is the master
wire [31:0] S_AXI_HP0_AWADDR;
@@ -3447,6 +3462,8 @@ module n3xx (
.NUM_DBOARDS(NUM_DBOARDS),
.NUM_SPI_PER_DBOARD(4),
.USE_CORRECTION(1),
.CHDR_W(CHDR_W),
.RFNOC_PROTOVER(RFNOC_PROTOVER),
`ifdef USE_REPLAY
.USE_REPLAY(1)
`else