fpga: e320: Support advanced transport adapter

- Fix NODE_INST
- Fix RFNOC_PROTOVER
- Add option to use SystemVerilog transport adapter for raw UDP


Original-commit: 0114e108af63d9ac785649c8099a042299624943

top/e320/Makefile.e320.inc

@@ -33,6 +33,9 @@ include $(LIB_DIR)/xge_interface/Makefile.srcs
 include $(LIB_DIR)/dsp/Makefile.srcs
 include $(LIB_DIR)/io_cap_gen/Makefile.srcs
 include $(LIB_DIR)/rfnoc/Makefile.srcs
+include $(LIB_DIR)/axi4s_sv/Makefile.srcs
+include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
+
 # For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
 # DUC, and of course the radio. Any other block needs to use the
 # RFNOC_OOT_MAKEFILE_SRCS variable (see below).
@@ -56,8 +59,8 @@ TOP_SRCS = \
 e320.v \
 e320_core.v \
 e320_clocking.v \
-n3xx_sfp_wrapper.v \
-n3xx_mgt_io_core.v \
+e320_sfp_wrapper.v \
+e320_mgt_io_core.v \
 $(IMAGE_CORE)
 
 MB_XDC = \
@@ -117,6 +120,7 @@ $(RFNOC_FRAMEWORK_SRCS) \
 $(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
 $(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \
 $(RFNOC_BLOCK_RADIO_SRCS) \
+$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
 $(abspath $(MB_XDC))
 
 EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"