rfnoc: Update blocks to use autogenerated noc_shell
Original-commit: b746819769e6a960f8227981ea10c7ed9c3d826a
This commit is contained in:
Wade Fife
@@ -1,123 +1,110 @@
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//
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//
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// Copyright 2019 Ettus Research, A National Instruments Company
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// Copyright 2019 Ettus Research, A National Instruments Brand
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//
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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//
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// Module: noc_shell_axi_ram_fifo
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// Module: noc_shell_axi_ram_fifo
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//
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//
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// Description: A NoC Shell for the RFNoC AXI RAM FIFO. This NoC Shell
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// Description:
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// implements the control port interface but does nothing to the
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//
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// data path other than moving it to the requested clock domain.
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// This is a tool-generated NoC-shell for the axi_ram_fifo block.
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// See the RFNoC specification for more information about NoC shells.
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//
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// Parameters:
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//
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// THIS_PORTID : Control crossbar port to which this block is connected
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// CHDR_W : AXIS-CHDR data bus width
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// MTU : Maximum transmission unit (i.e., maximum packet size in
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//
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//
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`define MAX(X,Y) ((X) > (Y) ? (X) : (Y))
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`default_nettype none
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module noc_shell_axi_ram_fifo #(
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module noc_shell_axi_ram_fifo #(
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parameter [31:0] NOC_ID = 32'h0,
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parameter [9:0] THIS_PORTID = 10'd0,
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parameter [ 9:0] THIS_PORTID = 10'd0,
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parameter CHDR_W = 64,
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parameter CHDR_W = 64,
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parameter [5:0] MTU = 10,
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parameter DATA_W = 64,
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parameter NUM_PORTS = 2,
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parameter [ 5:0] CTRL_FIFO_SIZE = 0,
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parameter MEM_DATA_W = 64,
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parameter [ 0:0] CTRLPORT_MST_EN = 1,
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parameter MEM_ADDR_W = 30,
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parameter [ 0:0] CTRLPORT_SLV_EN = 1,
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parameter FIFO_ADDR_BASE = {30'h02000000, 30'h00000000},
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parameter [ 5:0] NUM_DATA_I = 1,
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parameter FIFO_ADDR_MASK = {30'h01FFFFFF, 30'h01FFFFFF},
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parameter [ 5:0] NUM_DATA_O = 1,
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parameter MEM_CLK_RATE = 300e6
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parameter [ 5:0] MTU = 10,
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parameter SYNC_DATA_CLOCKS = 0
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) (
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) (
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//---------------------------------------------------------------------------
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//---------------------
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// Framework Interface
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// Framework Interface
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//---------------------------------------------------------------------------
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//---------------------
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// RFNoC Framework Clocks
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input wire rfnoc_chdr_clk,
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input wire rfnoc_ctrl_clk,
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input wire mem_clk,
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// NoC Shell Generated Resets
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output wire rfnoc_chdr_rst,
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output wire rfnoc_ctrl_rst,
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output wire mem_rst,
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// RFNoC Framework Clocks and Resets
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input wire rfnoc_chdr_clk,
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output wire rfnoc_chdr_rst,
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input wire rfnoc_ctrl_clk,
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output wire rfnoc_ctrl_rst,
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// RFNoC Backend Interface
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// RFNoC Backend Interface
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input wire [ 511:0] rfnoc_core_config,
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input wire [511:0] rfnoc_core_config,
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output wire [ 511:0] rfnoc_core_status,
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output wire [511:0] rfnoc_core_status,
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// CHDR Input Ports (from framework)
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input wire [(CHDR_W*NUM_DATA_I)-1:0] s_rfnoc_chdr_tdata,
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input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tlast,
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input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tvalid,
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output wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tready,
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// CHDR Output Ports (to framework)
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output wire [(CHDR_W*NUM_DATA_O)-1:0] m_rfnoc_chdr_tdata,
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output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tlast,
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output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tvalid,
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input wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tready,
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// AXIS-Ctrl Input Port (from framework)
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input wire [ 31:0] s_rfnoc_ctrl_tdata,
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input wire s_rfnoc_ctrl_tlast,
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input wire s_rfnoc_ctrl_tvalid,
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output wire s_rfnoc_ctrl_tready,
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// AXIS-Ctrl Output Port (to framework)
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output wire [ 31:0] m_rfnoc_ctrl_tdata,
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output wire m_rfnoc_ctrl_tlast,
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output wire m_rfnoc_ctrl_tvalid,
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input wire m_rfnoc_ctrl_tready,
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//---------------------------------------------------------------------------
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// AXIS-CHDR Input Ports (from framework)
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// Client Control Port Interface
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input wire [(0+NUM_PORTS)*CHDR_W-1:0] s_rfnoc_chdr_tdata,
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//---------------------------------------------------------------------------
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input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tlast,
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input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tvalid,
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output wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tready,
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// AXIS-CHDR Output Ports (to framework)
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output wire [(0+NUM_PORTS)*CHDR_W-1:0] m_rfnoc_chdr_tdata,
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output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tlast,
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output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tvalid,
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input wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tready,
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// Clock
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// AXIS-Ctrl Control Input Port (from framework)
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input wire ctrlport_clk,
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input wire [31:0] s_rfnoc_ctrl_tdata,
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input wire ctrlport_rst,
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input wire s_rfnoc_ctrl_tlast,
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// Master
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input wire s_rfnoc_ctrl_tvalid,
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output wire m_ctrlport_req_wr,
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output wire s_rfnoc_ctrl_tready,
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output wire m_ctrlport_req_rd,
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// AXIS-Ctrl Control Output Port (to framework)
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output wire [19:0] m_ctrlport_req_addr,
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output wire [31:0] m_rfnoc_ctrl_tdata,
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output wire [31:0] m_ctrlport_req_data,
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output wire m_rfnoc_ctrl_tlast,
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output wire [ 3:0] m_ctrlport_req_byte_en,
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output wire m_rfnoc_ctrl_tvalid,
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output wire m_ctrlport_req_has_time,
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input wire m_rfnoc_ctrl_tready,
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output wire [63:0] m_ctrlport_req_time,
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input wire m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [31:0] m_ctrlport_resp_data,
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// Slave
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [ 9:0] s_ctrlport_req_portid,
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input wire [15:0] s_ctrlport_req_rem_epid,
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input wire [ 9:0] s_ctrlport_req_rem_portid,
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input wire [31:0] s_ctrlport_req_data,
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input wire [ 3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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output wire s_ctrlport_resp_ack,
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output wire [ 1:0] s_ctrlport_resp_status,
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output wire [31:0] s_ctrlport_resp_data,
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//---------------------------------------------------------------------------
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//---------------------
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// Client Data Interface
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// Client Interface
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//---------------------------------------------------------------------------
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//---------------------
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// Clock
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// CtrlPort Clock and Reset
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input wire axis_data_clk,
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output wire ctrlport_clk,
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input wire axis_data_rst,
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output wire ctrlport_rst,
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// CtrlPort Master
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output wire m_ctrlport_req_wr,
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output wire m_ctrlport_req_rd,
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output wire [19:0] m_ctrlport_req_addr,
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output wire [31:0] m_ctrlport_req_data,
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input wire m_ctrlport_resp_ack,
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input wire [31:0] m_ctrlport_resp_data,
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// Output data stream (to user logic)
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// AXIS-CHDR Clock and Reset
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output wire [ (NUM_DATA_I*DATA_W)-1:0] m_axis_tdata,
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output wire axis_chdr_clk,
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output wire [(NUM_DATA_I*`MAX(DATA_W/CHDR_W, 1))-1:0] m_axis_tkeep,
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output wire axis_chdr_rst,
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output wire [ NUM_DATA_I-1:0] m_axis_tlast,
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// Framework to User Logic: in
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output wire [ NUM_DATA_I-1:0] m_axis_tvalid,
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output wire [NUM_PORTS*CHDR_W-1:0] m_in_chdr_tdata,
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input wire [ NUM_DATA_I-1:0] m_axis_tready,
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output wire [NUM_PORTS-1:0] m_in_chdr_tlast,
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output wire [NUM_PORTS-1:0] m_in_chdr_tvalid,
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// Input data stream (from user logic)
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input wire [NUM_PORTS-1:0] m_in_chdr_tready,
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input wire [ (NUM_DATA_O*DATA_W)-1:0] s_axis_tdata,
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// User Logic to Framework: out
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input wire [(NUM_DATA_O*`MAX(DATA_W/CHDR_W, 1))-1:0] s_axis_tkeep,
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input wire [NUM_PORTS*CHDR_W-1:0] s_out_chdr_tdata,
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input wire [ NUM_DATA_O-1:0] s_axis_tlast,
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input wire [NUM_PORTS-1:0] s_out_chdr_tlast,
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input wire [ NUM_DATA_O-1:0] s_axis_tvalid,
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input wire [NUM_PORTS-1:0] s_out_chdr_tvalid,
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output wire [ NUM_DATA_O-1:0] s_axis_tready
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output wire [NUM_PORTS-1:0] s_out_chdr_tready
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);
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);
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// Backend Interface
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// Backend Interface
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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wire data_i_flush_en;
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wire data_i_flush_en;
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wire [31:0] data_i_flush_timeout;
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wire [31:0] data_i_flush_timeout;
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wire [63:0] data_i_flush_active;
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wire [63:0] data_i_flush_active;
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@@ -128,18 +115,18 @@ module noc_shell_axi_ram_fifo #(
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wire [63:0] data_o_flush_done;
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wire [63:0] data_o_flush_done;
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backend_iface #(
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backend_iface #(
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.NOC_ID (NOC_ID),
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.NOC_ID (32'hF1F00000),
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.NUM_DATA_I (NUM_DATA_I),
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.NUM_DATA_I (0+NUM_PORTS),
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.NUM_DATA_O (NUM_DATA_O),
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.NUM_DATA_O (0+NUM_PORTS),
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.CTRL_FIFOSIZE (CTRL_FIFO_SIZE),
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.CTRL_FIFOSIZE ($clog2(32)),
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.MTU (MTU)
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.MTU (MTU)
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) backend_iface_i (
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) backend_iface_i (
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_chdr_rst (rfnoc_chdr_rst),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
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.rfnoc_core_config (rfnoc_core_config),
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.rfnoc_core_config (rfnoc_core_config),
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.rfnoc_core_status (rfnoc_core_status),
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.rfnoc_core_status (rfnoc_core_status),
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.rfnoc_chdr_rst (rfnoc_chdr_rst),
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.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
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.data_i_flush_en (data_i_flush_en),
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.data_i_flush_en (data_i_flush_en),
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.data_i_flush_timeout (data_i_flush_timeout),
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.data_i_flush_timeout (data_i_flush_timeout),
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.data_i_flush_active (data_i_flush_active),
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.data_i_flush_active (data_i_flush_active),
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@@ -151,169 +138,132 @@ module noc_shell_axi_ram_fifo #(
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);
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);
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// Control Path
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// Reset Generation
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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ctrlport_endpoint #(
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wire mem_rst_pulse;
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.THIS_PORTID (THIS_PORTID ),
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.SYNC_CLKS (0 ),
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pulse_synchronizer #(.MODE ("POSEDGE")) pulse_synchronizer_mem (
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.AXIS_CTRL_MST_EN (CTRLPORT_SLV_EN),
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.clk_a(rfnoc_chdr_clk), .rst_a(1'b0), .pulse_a (rfnoc_chdr_rst), .busy_a (),
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.AXIS_CTRL_SLV_EN (CTRLPORT_MST_EN),
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.clk_b(mem_clk), .pulse_b (mem_rst_pulse)
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.SLAVE_FIFO_SIZE (CTRL_FIFO_SIZE )
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);
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) ctrlport_ep_i (
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
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pulse_stretch_min #(.LENGTH(32)) pulse_stretch_min_mem (
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.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
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.clk(mem_clk), .rst(1'b0),
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.ctrlport_clk (ctrlport_clk ),
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.pulse_in(mem_rst_pulse), .pulse_out(mem_rst)
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.ctrlport_rst (ctrlport_rst ),
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.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata ),
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.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast ),
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.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid ),
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.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready ),
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.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata ),
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.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast ),
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.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid ),
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.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready ),
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.m_ctrlport_req_wr (m_ctrlport_req_wr ),
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.m_ctrlport_req_rd (m_ctrlport_req_rd ),
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.m_ctrlport_req_addr (m_ctrlport_req_addr ),
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.m_ctrlport_req_data (m_ctrlport_req_data ),
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.m_ctrlport_req_byte_en (m_ctrlport_req_byte_en ),
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.m_ctrlport_req_has_time (m_ctrlport_req_has_time ),
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.m_ctrlport_req_time (m_ctrlport_req_time ),
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.m_ctrlport_resp_ack (m_ctrlport_resp_ack ),
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.m_ctrlport_resp_status (m_ctrlport_resp_status ),
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.m_ctrlport_resp_data (m_ctrlport_resp_data ),
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.s_ctrlport_req_wr (s_ctrlport_req_wr ),
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.s_ctrlport_req_rd (s_ctrlport_req_rd ),
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.s_ctrlport_req_addr (s_ctrlport_req_addr ),
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.s_ctrlport_req_portid (s_ctrlport_req_portid ),
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.s_ctrlport_req_rem_epid (s_ctrlport_req_rem_epid ),
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.s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
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.s_ctrlport_req_data (s_ctrlport_req_data ),
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.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en ),
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.s_ctrlport_req_has_time (s_ctrlport_req_has_time ),
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.s_ctrlport_req_time (s_ctrlport_req_time ),
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.s_ctrlport_resp_ack (s_ctrlport_resp_ack ),
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.s_ctrlport_resp_status (s_ctrlport_resp_status ),
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.s_ctrlport_resp_data (s_ctrlport_resp_data )
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);
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);
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// Data Path
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// Control Path
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// Set WORD_W to the smaller of DATA_W and CHDR_W. This will be our common
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assign ctrlport_clk = mem_clk;
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// word size between the CHDR and user data ports.
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assign ctrlport_rst = mem_rst;
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localparam WORD_W = DATA_W < CHDR_W ? DATA_W : CHDR_W;
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localparam KEEP_W = `MAX(DATA_W/CHDR_W, 1);
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ctrlport_endpoint #(
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.THIS_PORTID (THIS_PORTID),
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.SYNC_CLKS (0),
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.AXIS_CTRL_MST_EN (0),
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.AXIS_CTRL_SLV_EN (1),
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.SLAVE_FIFO_SIZE ($clog2(32))
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) ctrlport_endpoint_i (
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
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.ctrlport_clk (ctrlport_clk),
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.ctrlport_rst (ctrlport_rst),
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.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
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.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
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.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
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.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
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.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
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.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
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.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
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.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
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.m_ctrlport_req_wr (m_ctrlport_req_wr),
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.m_ctrlport_req_rd (m_ctrlport_req_rd),
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.m_ctrlport_req_addr (m_ctrlport_req_addr),
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.m_ctrlport_req_data (m_ctrlport_req_data),
|
||||||
|
.m_ctrlport_req_byte_en (),
|
||||||
|
.m_ctrlport_req_has_time (),
|
||||||
|
.m_ctrlport_req_time (),
|
||||||
|
.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
|
||||||
|
.m_ctrlport_resp_status (2'b0),
|
||||||
|
.m_ctrlport_resp_data (m_ctrlport_resp_data),
|
||||||
|
.s_ctrlport_req_wr (1'b0),
|
||||||
|
.s_ctrlport_req_rd (1'b0),
|
||||||
|
.s_ctrlport_req_addr (20'b0),
|
||||||
|
.s_ctrlport_req_portid (10'b0),
|
||||||
|
.s_ctrlport_req_rem_epid (16'b0),
|
||||||
|
.s_ctrlport_req_rem_portid (10'b0),
|
||||||
|
.s_ctrlport_req_data (32'b0),
|
||||||
|
.s_ctrlport_req_byte_en (4'hF),
|
||||||
|
.s_ctrlport_req_has_time (1'b0),
|
||||||
|
.s_ctrlport_req_time (64'b0),
|
||||||
|
.s_ctrlport_resp_ack (),
|
||||||
|
.s_ctrlport_resp_status (),
|
||||||
|
.s_ctrlport_resp_data ()
|
||||||
|
);
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Data Path
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
genvar i;
|
genvar i;
|
||||||
|
|
||||||
for (i = 0; i < NUM_DATA_I; i = i + 1) begin : gen_in
|
assign axis_chdr_clk = rfnoc_chdr_clk;
|
||||||
wire [CHDR_W-1:0] temp_in_tdata;
|
assign axis_chdr_rst = rfnoc_chdr_rst;
|
||||||
wire temp_in_tlast;
|
|
||||||
wire temp_in_tvalid;
|
//---------------------
|
||||||
wire temp_in_tready;
|
// Input Data Paths
|
||||||
|
//---------------------
|
||||||
|
|
||||||
axis_packet_flush #(
|
for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_input_in
|
||||||
.WIDTH (CHDR_W),
|
chdr_to_chdr_data #(
|
||||||
.FLUSH_PARTIAL_PKTS (0),
|
.CHDR_W (CHDR_W)
|
||||||
.TIMEOUT_W (32),
|
) chdr_to_chdr_data_in_in (
|
||||||
.PIPELINE ("IN")
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
) in_packet_flush_i (
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
.clk (rfnoc_chdr_clk),
|
.s_axis_chdr_tdata (s_rfnoc_chdr_tdata[(0+i)*CHDR_W+:CHDR_W]),
|
||||||
.reset (rfnoc_chdr_rst),
|
.s_axis_chdr_tlast (s_rfnoc_chdr_tlast[0+i]),
|
||||||
.enable (data_i_flush_en),
|
.s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[0+i]),
|
||||||
.timeout (data_i_flush_timeout),
|
.s_axis_chdr_tready (s_rfnoc_chdr_tready[0+i]),
|
||||||
.flushing (data_i_flush_active[i]),
|
.m_axis_chdr_tdata (m_in_chdr_tdata[i*CHDR_W+:CHDR_W]),
|
||||||
.done (data_i_flush_done[i]),
|
.m_axis_chdr_tlast (m_in_chdr_tlast[i]),
|
||||||
.s_axis_tdata (s_rfnoc_chdr_tdata[i*CHDR_W +: CHDR_W]),
|
.m_axis_chdr_tvalid (m_in_chdr_tvalid[i]),
|
||||||
.s_axis_tlast (s_rfnoc_chdr_tlast[i]),
|
.m_axis_chdr_tready (m_in_chdr_tready[i]),
|
||||||
.s_axis_tvalid (s_rfnoc_chdr_tvalid[i]),
|
.flush_en (data_i_flush_en),
|
||||||
.s_axis_tready (s_rfnoc_chdr_tready[i]),
|
.flush_timeout (data_i_flush_timeout),
|
||||||
.m_axis_tdata (temp_in_tdata),
|
.flush_active (data_i_flush_active[0+i]),
|
||||||
.m_axis_tlast (temp_in_tlast),
|
.flush_done (data_i_flush_done[0+i])
|
||||||
.m_axis_tvalid (temp_in_tvalid),
|
|
||||||
.m_axis_tready (temp_in_tready)
|
|
||||||
);
|
|
||||||
|
|
||||||
axis_width_conv #(
|
|
||||||
.WORD_W (WORD_W),
|
|
||||||
.IN_WORDS (CHDR_W/WORD_W),
|
|
||||||
.OUT_WORDS (DATA_W/WORD_W),
|
|
||||||
.SYNC_CLKS (SYNC_DATA_CLOCKS),
|
|
||||||
.PIPELINE ("NONE")
|
|
||||||
) in_width_conv_i (
|
|
||||||
.s_axis_aclk (rfnoc_chdr_clk),
|
|
||||||
.s_axis_rst (rfnoc_chdr_rst),
|
|
||||||
.s_axis_tdata (temp_in_tdata),
|
|
||||||
.s_axis_tkeep ({CHDR_W/WORD_W{1'b1}}),
|
|
||||||
.s_axis_tlast (temp_in_tlast),
|
|
||||||
.s_axis_tvalid (temp_in_tvalid),
|
|
||||||
.s_axis_tready (temp_in_tready),
|
|
||||||
.m_axis_aclk (axis_data_clk),
|
|
||||||
.m_axis_rst (axis_data_rst),
|
|
||||||
.m_axis_tdata (m_axis_tdata[i*DATA_W +: DATA_W]),
|
|
||||||
.m_axis_tkeep (m_axis_tkeep[i*KEEP_W +: KEEP_W]),
|
|
||||||
.m_axis_tlast (m_axis_tlast[i]),
|
|
||||||
.m_axis_tvalid (m_axis_tvalid[i]),
|
|
||||||
.m_axis_tready (m_axis_tready[i])
|
|
||||||
);
|
);
|
||||||
end
|
end
|
||||||
|
|
||||||
|
//---------------------
|
||||||
|
// Output Data Paths
|
||||||
|
//---------------------
|
||||||
|
|
||||||
for (i = 0; i < NUM_DATA_O; i = i + 1) begin : gen_out
|
for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_output_out
|
||||||
wire [ CHDR_W-1:0] temp_out_tdata;
|
chdr_to_chdr_data #(
|
||||||
wire [CHDR_W/WORD_W-1:0] temp_out_tkeep;
|
.CHDR_W (CHDR_W)
|
||||||
wire temp_out_tlast;
|
) chdr_to_chdr_data_out_out (
|
||||||
wire temp_out_tvalid;
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
wire temp_out_tready;
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
|
.m_axis_chdr_tdata (m_rfnoc_chdr_tdata[(0+i)*CHDR_W+:CHDR_W]),
|
||||||
axis_width_conv #(
|
.m_axis_chdr_tlast (m_rfnoc_chdr_tlast[0+i]),
|
||||||
.WORD_W (WORD_W),
|
.m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[0+i]),
|
||||||
.IN_WORDS (DATA_W/WORD_W),
|
.m_axis_chdr_tready (m_rfnoc_chdr_tready[0+i]),
|
||||||
.OUT_WORDS (CHDR_W/WORD_W),
|
.s_axis_chdr_tdata (s_out_chdr_tdata[i*CHDR_W+:CHDR_W]),
|
||||||
.SYNC_CLKS (SYNC_DATA_CLOCKS),
|
.s_axis_chdr_tlast (s_out_chdr_tlast[i]),
|
||||||
.PIPELINE ("NONE")
|
.s_axis_chdr_tvalid (s_out_chdr_tvalid[i]),
|
||||||
) out_width_conv_i (
|
.s_axis_chdr_tready (s_out_chdr_tready[i]),
|
||||||
.s_axis_aclk (axis_data_clk),
|
.flush_en (data_o_flush_en),
|
||||||
.s_axis_rst (axis_data_rst),
|
.flush_timeout (data_o_flush_timeout),
|
||||||
.s_axis_tdata (s_axis_tdata[i*DATA_W +: DATA_W]),
|
.flush_active (data_o_flush_active[0+i]),
|
||||||
.s_axis_tkeep (s_axis_tkeep[i*KEEP_W +: KEEP_W]),
|
.flush_done (data_o_flush_done[0+i])
|
||||||
.s_axis_tlast (s_axis_tlast[i]),
|
|
||||||
.s_axis_tvalid (s_axis_tvalid[i]),
|
|
||||||
.s_axis_tready (s_axis_tready[i]),
|
|
||||||
.m_axis_aclk (rfnoc_chdr_clk),
|
|
||||||
.m_axis_rst (rfnoc_chdr_rst),
|
|
||||||
.m_axis_tdata (temp_out_tdata),
|
|
||||||
.m_axis_tkeep (),
|
|
||||||
.m_axis_tlast (temp_out_tlast),
|
|
||||||
.m_axis_tvalid (temp_out_tvalid),
|
|
||||||
.m_axis_tready (temp_out_tready)
|
|
||||||
);
|
);
|
||||||
|
|
||||||
axis_packet_flush #(
|
|
||||||
.WIDTH (CHDR_W),
|
|
||||||
.FLUSH_PARTIAL_PKTS (0),
|
|
||||||
.TIMEOUT_W (32),
|
|
||||||
.PIPELINE ("OUT")
|
|
||||||
) out_packet_flush_i (
|
|
||||||
.clk (rfnoc_chdr_clk),
|
|
||||||
.reset (rfnoc_chdr_rst),
|
|
||||||
.enable (data_o_flush_en),
|
|
||||||
.timeout (data_o_flush_timeout),
|
|
||||||
.flushing (data_o_flush_active[i]),
|
|
||||||
.done (data_o_flush_done[i]),
|
|
||||||
.s_axis_tdata (temp_out_tdata),
|
|
||||||
.s_axis_tlast (temp_out_tlast),
|
|
||||||
.s_axis_tvalid (temp_out_tvalid),
|
|
||||||
.s_axis_tready (temp_out_tready),
|
|
||||||
.m_axis_tdata (m_rfnoc_chdr_tdata[i*CHDR_W +: CHDR_W]),
|
|
||||||
.m_axis_tlast (m_rfnoc_chdr_tlast[i]),
|
|
||||||
.m_axis_tvalid (m_rfnoc_chdr_tvalid[i]),
|
|
||||||
.m_axis_tready (m_rfnoc_chdr_tready[i])
|
|
||||||
);
|
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
||||||
endmodule
|
endmodule // noc_shell_axi_ram_fifo
|
||||||
|
|
||||||
|
|
||||||
|
`default_nettype wire
|
||||||
|
|||||||
@@ -182,13 +182,15 @@ module rfnoc_block_axi_ram_fifo #(
|
|||||||
|
|
||||||
`include "axi_ram_fifo_regs.vh"
|
`include "axi_ram_fifo_regs.vh"
|
||||||
|
|
||||||
localparam NOC_ID = 'hF1F0_0000;
|
|
||||||
|
|
||||||
// If the memory width is larger than the CHDR width, then we need to use
|
// If the memory width is larger than the CHDR width, then we need to use
|
||||||
// tkeep to track which CHDR words are valid as they go through the FIFO.
|
// tkeep to track which CHDR words are valid as they go through the FIFO.
|
||||||
// Calculate the TKEEP width here. Set to 1 if it's not needed.
|
// Calculate the TKEEP width here. Set to 1 if it's not needed.
|
||||||
localparam KEEP_W = (MEM_DATA_W/CHDR_W) > 1 ? (MEM_DATA_W/CHDR_W) : 1;
|
localparam KEEP_W = (MEM_DATA_W/CHDR_W) > 1 ? (MEM_DATA_W/CHDR_W) : 1;
|
||||||
|
|
||||||
|
// Set WORD_W to the smaller of MEM_DATA_W and CHDR_W. This will be our
|
||||||
|
// common word size when resizing between CHDR and memory words.
|
||||||
|
localparam WORD_W = (MEM_DATA_W < CHDR_W) ? MEM_DATA_W : CHDR_W;
|
||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// Parameter Checks
|
// Parameter Checks
|
||||||
@@ -205,7 +207,7 @@ module rfnoc_block_axi_ram_fifo #(
|
|||||||
// NoC Shell
|
// NoC Shell
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
wire rfnoc_chdr_rst;
|
wire mem_rst;
|
||||||
|
|
||||||
wire ctrlport_req_wr;
|
wire ctrlport_req_wr;
|
||||||
wire ctrlport_req_rd;
|
wire ctrlport_req_rd;
|
||||||
@@ -214,110 +216,74 @@ module rfnoc_block_axi_ram_fifo #(
|
|||||||
wire ctrlport_resp_ack;
|
wire ctrlport_resp_ack;
|
||||||
wire [31:0] ctrlport_resp_data;
|
wire [31:0] ctrlport_resp_data;
|
||||||
|
|
||||||
wire [NUM_PORTS*MEM_DATA_W-1:0] m_axis_data_tdata;
|
wire axis_chdr_clk;
|
||||||
wire [ NUM_PORTS*KEEP_W-1:0] m_axis_data_tkeep;
|
wire axis_chdr_rst;
|
||||||
wire [ NUM_PORTS-1:0] m_axis_data_tlast;
|
|
||||||
wire [ NUM_PORTS-1:0] m_axis_data_tvalid;
|
|
||||||
wire [ NUM_PORTS-1:0] m_axis_data_tready;
|
|
||||||
|
|
||||||
wire [NUM_PORTS*MEM_DATA_W-1:0] s_axis_data_tdata;
|
wire [NUM_PORTS*CHDR_W-1:0] m_axis_chdr_tdata;
|
||||||
wire [ NUM_PORTS*KEEP_W-1:0] s_axis_data_tkeep;
|
wire [ NUM_PORTS-1:0] m_axis_chdr_tlast;
|
||||||
wire [ NUM_PORTS-1:0] s_axis_data_tlast;
|
wire [ NUM_PORTS-1:0] m_axis_chdr_tvalid;
|
||||||
wire [ NUM_PORTS-1:0] s_axis_data_tvalid;
|
wire [ NUM_PORTS-1:0] m_axis_chdr_tready;
|
||||||
wire [ NUM_PORTS-1:0] s_axis_data_tready;
|
|
||||||
|
wire [NUM_PORTS*CHDR_W-1:0] s_axis_chdr_tdata;
|
||||||
|
wire [ NUM_PORTS-1:0] s_axis_chdr_tlast;
|
||||||
|
wire [ NUM_PORTS-1:0] s_axis_chdr_tvalid;
|
||||||
|
wire [ NUM_PORTS-1:0] s_axis_chdr_tready;
|
||||||
|
|
||||||
noc_shell_axi_ram_fifo #(
|
noc_shell_axi_ram_fifo #(
|
||||||
.NOC_ID (NOC_ID),
|
.THIS_PORTID (THIS_PORTID),
|
||||||
.THIS_PORTID (THIS_PORTID),
|
.CHDR_W (CHDR_W),
|
||||||
.CHDR_W (CHDR_W),
|
.NUM_PORTS (NUM_PORTS),
|
||||||
.DATA_W (MEM_DATA_W),
|
.MTU (MTU)
|
||||||
.CTRL_FIFO_SIZE (5),
|
|
||||||
.CTRLPORT_MST_EN (1),
|
|
||||||
.CTRLPORT_SLV_EN (0),
|
|
||||||
.NUM_DATA_I (NUM_PORTS),
|
|
||||||
.NUM_DATA_O (NUM_PORTS),
|
|
||||||
.MTU (MTU),
|
|
||||||
.SYNC_DATA_CLOCKS (0)
|
|
||||||
) noc_shell_axi_ram_fifo_i (
|
) noc_shell_axi_ram_fifo_i (
|
||||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
.mem_clk (mem_clk),
|
||||||
.rfnoc_ctrl_rst (),
|
.rfnoc_chdr_rst (),
|
||||||
.rfnoc_core_config (rfnoc_core_config),
|
.rfnoc_ctrl_rst (),
|
||||||
.rfnoc_core_status (rfnoc_core_status),
|
.mem_rst (mem_rst),
|
||||||
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
|
.rfnoc_core_config (rfnoc_core_config),
|
||||||
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
|
.rfnoc_core_status (rfnoc_core_status),
|
||||||
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
|
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
|
||||||
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
|
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
|
||||||
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
|
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
|
||||||
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
|
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
|
||||||
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
|
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
|
||||||
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
|
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
|
||||||
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
|
||||||
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
|
||||||
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
||||||
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
||||||
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
||||||
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
||||||
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
||||||
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
||||||
.ctrlport_clk (mem_clk),
|
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
||||||
.ctrlport_rst (axi_rst),
|
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
||||||
.m_ctrlport_req_wr (ctrlport_req_wr),
|
.ctrlport_clk (),
|
||||||
.m_ctrlport_req_rd (ctrlport_req_rd),
|
.ctrlport_rst (),
|
||||||
.m_ctrlport_req_addr (ctrlport_req_addr),
|
.m_ctrlport_req_wr (ctrlport_req_wr),
|
||||||
.m_ctrlport_req_data (ctrlport_req_data),
|
.m_ctrlport_req_rd (ctrlport_req_rd),
|
||||||
.m_ctrlport_req_byte_en (),
|
.m_ctrlport_req_addr (ctrlport_req_addr),
|
||||||
.m_ctrlport_req_has_time (),
|
.m_ctrlport_req_data (ctrlport_req_data),
|
||||||
.m_ctrlport_req_time (),
|
.m_ctrlport_resp_ack (ctrlport_resp_ack),
|
||||||
.m_ctrlport_resp_ack (ctrlport_resp_ack),
|
.m_ctrlport_resp_data (ctrlport_resp_data),
|
||||||
.m_ctrlport_resp_status (2'b0),
|
.axis_chdr_clk (axis_chdr_clk),
|
||||||
.m_ctrlport_resp_data (ctrlport_resp_data),
|
.axis_chdr_rst (axis_chdr_rst),
|
||||||
.s_ctrlport_req_wr (1'b0),
|
.m_in_chdr_tdata (m_axis_chdr_tdata),
|
||||||
.s_ctrlport_req_rd (1'b0),
|
.m_in_chdr_tlast (m_axis_chdr_tlast),
|
||||||
.s_ctrlport_req_addr (20'b0),
|
.m_in_chdr_tvalid (m_axis_chdr_tvalid),
|
||||||
.s_ctrlport_req_portid (10'b0),
|
.m_in_chdr_tready (m_axis_chdr_tready),
|
||||||
.s_ctrlport_req_rem_epid (16'b0),
|
.s_out_chdr_tdata (s_axis_chdr_tdata),
|
||||||
.s_ctrlport_req_rem_portid (10'b0),
|
.s_out_chdr_tlast (s_axis_chdr_tlast),
|
||||||
.s_ctrlport_req_data (32'b0),
|
.s_out_chdr_tvalid (s_axis_chdr_tvalid),
|
||||||
.s_ctrlport_req_byte_en (4'b0),
|
.s_out_chdr_tready (s_axis_chdr_tready)
|
||||||
.s_ctrlport_req_has_time (1'b0),
|
|
||||||
.s_ctrlport_req_time (64'b0),
|
|
||||||
.s_ctrlport_resp_ack (),
|
|
||||||
.s_ctrlport_resp_status (),
|
|
||||||
.s_ctrlport_resp_data (),
|
|
||||||
.axis_data_clk (mem_clk),
|
|
||||||
.axis_data_rst (axi_rst),
|
|
||||||
.m_axis_tdata (m_axis_data_tdata),
|
|
||||||
.m_axis_tkeep (m_axis_data_tkeep),
|
|
||||||
.m_axis_tlast (m_axis_data_tlast),
|
|
||||||
.m_axis_tvalid (m_axis_data_tvalid),
|
|
||||||
.m_axis_tready (m_axis_data_tready),
|
|
||||||
.s_axis_tdata (s_axis_data_tdata),
|
|
||||||
.s_axis_tkeep (s_axis_data_tkeep),
|
|
||||||
.s_axis_tlast (s_axis_data_tlast),
|
|
||||||
.s_axis_tvalid (s_axis_data_tvalid),
|
|
||||||
.s_axis_tready (s_axis_data_tready)
|
|
||||||
);
|
);
|
||||||
|
|
||||||
wire rfnoc_chdr_rst_mem_clk;
|
|
||||||
reg mem_rst_block;
|
reg mem_rst_block;
|
||||||
|
|
||||||
// Cross the CHDR reset to the mem_clk domain
|
|
||||||
pulse_synchronizer #(
|
|
||||||
.MODE ("POSEDGE")
|
|
||||||
) ctrl_rst_sync_i (
|
|
||||||
.clk_a (rfnoc_chdr_clk),
|
|
||||||
.rst_a (1'b0),
|
|
||||||
.pulse_a (rfnoc_chdr_rst),
|
|
||||||
.busy_a (),
|
|
||||||
.clk_b (mem_clk),
|
|
||||||
.pulse_b (rfnoc_chdr_rst_mem_clk)
|
|
||||||
);
|
|
||||||
|
|
||||||
// Combine the resets in a glitch-free manner
|
// Combine the resets in a glitch-free manner
|
||||||
always @(posedge mem_clk) begin
|
always @(posedge mem_clk) begin
|
||||||
mem_rst_block <= axi_rst | rfnoc_chdr_rst_mem_clk;
|
mem_rst_block <= axi_rst | mem_rst;
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
||||||
@@ -363,12 +329,83 @@ module rfnoc_block_axi_ram_fifo #(
|
|||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// FIFO Instances
|
// AXI RAM Port Instances
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
genvar i;
|
genvar i;
|
||||||
for (i = 0; i < NUM_PORTS; i = i + 1) begin : gen_ram_fifos
|
for (i = 0; i < NUM_PORTS; i = i + 1) begin : gen_ram_fifos
|
||||||
|
|
||||||
|
wire [MEM_DATA_W-1:0] m_axis_mem_tdata;
|
||||||
|
wire [ KEEP_W-1:0] m_axis_mem_tkeep;
|
||||||
|
wire m_axis_mem_tlast;
|
||||||
|
wire m_axis_mem_tvalid;
|
||||||
|
wire m_axis_mem_tready;
|
||||||
|
|
||||||
|
wire [MEM_DATA_W-1:0] s_axis_mem_tdata;
|
||||||
|
wire [ KEEP_W-1:0] s_axis_mem_tkeep;
|
||||||
|
wire s_axis_mem_tlast;
|
||||||
|
wire s_axis_mem_tvalid;
|
||||||
|
wire s_axis_mem_tready;
|
||||||
|
|
||||||
|
//-------------------------------------------------------------------------
|
||||||
|
// Width Conversion
|
||||||
|
//-------------------------------------------------------------------------
|
||||||
|
//
|
||||||
|
// Resize Data between CHDR_W and MEM_DATA_W. Cross between rfnoc_chdr_clk
|
||||||
|
// and mem_clk.
|
||||||
|
//
|
||||||
|
//-------------------------------------------------------------------------
|
||||||
|
|
||||||
|
axis_width_conv #(
|
||||||
|
.WORD_W (WORD_W),
|
||||||
|
.IN_WORDS (CHDR_W/WORD_W),
|
||||||
|
.OUT_WORDS (MEM_DATA_W/WORD_W),
|
||||||
|
.SYNC_CLKS (0),
|
||||||
|
.PIPELINE ("NONE")
|
||||||
|
) axis_width_conv_to_mem_i (
|
||||||
|
.s_axis_aclk (axis_chdr_clk),
|
||||||
|
.s_axis_rst (axis_chdr_rst),
|
||||||
|
.s_axis_tdata (m_axis_chdr_tdata[i*CHDR_W +: CHDR_W]),
|
||||||
|
.s_axis_tkeep ({CHDR_W/WORD_W{1'b1}}),
|
||||||
|
.s_axis_tlast (m_axis_chdr_tlast[i]),
|
||||||
|
.s_axis_tvalid (m_axis_chdr_tvalid[i]),
|
||||||
|
.s_axis_tready (m_axis_chdr_tready[i]),
|
||||||
|
.m_axis_aclk (mem_clk),
|
||||||
|
.m_axis_rst (mem_rst),
|
||||||
|
.m_axis_tdata (m_axis_mem_tdata),
|
||||||
|
.m_axis_tkeep (m_axis_mem_tkeep),
|
||||||
|
.m_axis_tlast (m_axis_mem_tlast),
|
||||||
|
.m_axis_tvalid (m_axis_mem_tvalid),
|
||||||
|
.m_axis_tready (m_axis_mem_tready)
|
||||||
|
);
|
||||||
|
|
||||||
|
axis_width_conv #(
|
||||||
|
.WORD_W (WORD_W),
|
||||||
|
.IN_WORDS (MEM_DATA_W/WORD_W),
|
||||||
|
.OUT_WORDS (CHDR_W/WORD_W),
|
||||||
|
.SYNC_CLKS (0),
|
||||||
|
.PIPELINE ("NONE")
|
||||||
|
) axis_width_conv_to_chdr_i (
|
||||||
|
.s_axis_aclk (mem_clk),
|
||||||
|
.s_axis_rst (mem_rst),
|
||||||
|
.s_axis_tdata (s_axis_mem_tdata),
|
||||||
|
.s_axis_tkeep (s_axis_mem_tkeep),
|
||||||
|
.s_axis_tlast (s_axis_mem_tlast),
|
||||||
|
.s_axis_tvalid (s_axis_mem_tvalid),
|
||||||
|
.s_axis_tready (s_axis_mem_tready),
|
||||||
|
.m_axis_aclk (axis_chdr_clk),
|
||||||
|
.m_axis_rst (axis_chdr_rst),
|
||||||
|
.m_axis_tdata (s_axis_chdr_tdata[i*CHDR_W +: CHDR_W]),
|
||||||
|
.m_axis_tkeep (),
|
||||||
|
.m_axis_tlast (s_axis_chdr_tlast[i]),
|
||||||
|
.m_axis_tvalid (s_axis_chdr_tvalid[i]),
|
||||||
|
.m_axis_tready (s_axis_chdr_tready[i])
|
||||||
|
);
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// AXI RAM FIFO Instance
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
wire [MEM_ADDR_W-1:0] m_axi_awaddr_int;
|
wire [MEM_ADDR_W-1:0] m_axi_awaddr_int;
|
||||||
wire [MEM_ADDR_W-1:0] m_axi_araddr_int;
|
wire [MEM_ADDR_W-1:0] m_axi_araddr_int;
|
||||||
|
|
||||||
@@ -408,18 +445,18 @@ module rfnoc_block_axi_ram_fifo #(
|
|||||||
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
||||||
|
|
||||||
// AXI-Stream Input
|
// AXI-Stream Input
|
||||||
.s_tdata (m_axis_data_tdata[MEM_DATA_W*i +: MEM_DATA_W]),
|
.s_tdata (m_axis_mem_tdata),
|
||||||
.s_tkeep (m_axis_data_tkeep[KEEP_W*i +: KEEP_W]),
|
.s_tkeep (m_axis_mem_tkeep),
|
||||||
.s_tlast (m_axis_data_tlast[i]),
|
.s_tlast (m_axis_mem_tlast),
|
||||||
.s_tvalid (m_axis_data_tvalid[i]),
|
.s_tvalid (m_axis_mem_tvalid),
|
||||||
.s_tready (m_axis_data_tready[i]),
|
.s_tready (m_axis_mem_tready),
|
||||||
//
|
//
|
||||||
// AXI-Stream Output
|
// AXI-Stream Output
|
||||||
.m_tdata (s_axis_data_tdata[MEM_DATA_W*i +: MEM_DATA_W]),
|
.m_tdata (s_axis_mem_tdata),
|
||||||
.m_tkeep (s_axis_data_tkeep[KEEP_W*i +: KEEP_W]),
|
.m_tkeep (s_axis_mem_tkeep),
|
||||||
.m_tlast (s_axis_data_tlast[i]),
|
.m_tlast (s_axis_mem_tlast),
|
||||||
.m_tvalid (s_axis_data_tvalid[i]),
|
.m_tvalid (s_axis_mem_tvalid),
|
||||||
.m_tready (s_axis_data_tready[i]),
|
.m_tready (s_axis_mem_tready),
|
||||||
|
|
||||||
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
||||||
// AXI4 Memory Interface
|
// AXI4 Memory Interface
|
||||||
|
|||||||
@@ -45,6 +45,7 @@ module rfnoc_block_axi_ram_fifo_tb #(
|
|||||||
localparam int STALL_PROB = 25; // BFM stall probability
|
localparam int STALL_PROB = 25; // BFM stall probability
|
||||||
|
|
||||||
// Block configuration
|
// Block configuration
|
||||||
|
localparam int NOC_ID = 'hF1F0_0000;
|
||||||
localparam int THIS_PORTID = 'h123;
|
localparam int THIS_PORTID = 'h123;
|
||||||
localparam int MTU = 12;
|
localparam int MTU = 12;
|
||||||
localparam int NUM_HB = 3;
|
localparam int NUM_HB = 3;
|
||||||
@@ -74,7 +75,7 @@ module rfnoc_block_axi_ram_fifo_tb #(
|
|||||||
rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
|
rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
|
||||||
sim_clock_gen #(.PERIOD(CTRL_CLK_PER), .AUTOSTART(0))
|
sim_clock_gen #(.PERIOD(CTRL_CLK_PER), .AUTOSTART(0))
|
||||||
rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
|
rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
|
||||||
sim_clock_gen #(.PERIOD(MEM_CLK_PER), .AUOSTART(0))
|
sim_clock_gen #(.PERIOD(MEM_CLK_PER), .AUTOSTART(0))
|
||||||
mem_clk_gen (.clk(mem_clk), .rst(mem_rst));
|
mem_clk_gen (.clk(mem_clk), .rst(mem_rst));
|
||||||
|
|
||||||
|
|
||||||
@@ -379,7 +380,7 @@ module rfnoc_block_axi_ram_fifo_tb #(
|
|||||||
|
|
||||||
task test_block_info();
|
task test_block_info();
|
||||||
test.start_test("Verify Block Info", 2us);
|
test.start_test("Verify Block Info", 2us);
|
||||||
`ASSERT_ERROR(blk_ctrl.get_noc_id() == rfnoc_block_axi_ram_fifo_i.NOC_ID, "Incorrect NOC_ID Value");
|
`ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I Value");
|
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O Value");
|
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
|
`ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
|
||||||
|
|||||||
@@ -1,132 +1,115 @@
|
|||||||
//
|
//
|
||||||
// Copyright 2019 Ettus Research, A National Instruments Company
|
// Copyright 2019 Ettus Research, A National Instruments Brand
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||||
//
|
//
|
||||||
// Module: noc_shell_ddc
|
// Module: noc_shell_ddc
|
||||||
//
|
//
|
||||||
// Description: A NoC Shell for RFNoC. This should eventually be replaced
|
// Description:
|
||||||
// by an auto-generated NoC Shell.
|
//
|
||||||
|
// This is a tool-generated NoC-shell for the ddc block.
|
||||||
|
// See the RFNoC specification for more information about NoC shells.
|
||||||
|
//
|
||||||
|
// Parameters:
|
||||||
|
//
|
||||||
|
// THIS_PORTID : Control crossbar port to which this block is connected
|
||||||
|
// CHDR_W : AXIS-CHDR data bus width
|
||||||
|
// MTU : Maximum transmission unit (i.e., maximum packet size in
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
|
||||||
module noc_shell_ddc #(
|
module noc_shell_ddc #(
|
||||||
parameter [31:0] NOC_ID = 32'h0,
|
parameter [9:0] THIS_PORTID = 10'd0,
|
||||||
parameter [ 9:0] THIS_PORTID = 10'd0,
|
parameter CHDR_W = 64,
|
||||||
parameter CHDR_W = 64,
|
parameter [5:0] MTU = 10,
|
||||||
parameter [ 0:0] CTRLPORT_SLV_EN = 1,
|
parameter NUM_PORTS = 1,
|
||||||
parameter [ 0:0] CTRLPORT_MST_EN = 1,
|
parameter NUM_HB = 3,
|
||||||
parameter [ 5:0] CTRL_FIFO_SIZE = 6,
|
parameter CIC_MAX_DECIM = 255
|
||||||
parameter [ 5:0] NUM_DATA_I = 1,
|
) (
|
||||||
parameter [ 5:0] NUM_DATA_O = 1,
|
//---------------------
|
||||||
parameter ITEM_W = 32,
|
|
||||||
parameter NIPC = 2,
|
|
||||||
parameter PYLD_FIFO_SIZE = 10,
|
|
||||||
parameter MTU = 10
|
|
||||||
)(
|
|
||||||
//---------------------------------------------------------------------------
|
|
||||||
// Framework Interface
|
// Framework Interface
|
||||||
//---------------------------------------------------------------------------
|
//---------------------
|
||||||
|
|
||||||
|
// RFNoC Framework Clocks
|
||||||
|
input wire rfnoc_chdr_clk,
|
||||||
|
input wire rfnoc_ctrl_clk,
|
||||||
|
input wire ce_clk,
|
||||||
|
|
||||||
|
// NoC Shell Generated Resets
|
||||||
|
output wire rfnoc_chdr_rst,
|
||||||
|
output wire rfnoc_ctrl_rst,
|
||||||
|
output wire ce_rst,
|
||||||
|
|
||||||
// RFNoC Framework Clocks and Resets
|
|
||||||
input wire rfnoc_chdr_clk,
|
|
||||||
output wire rfnoc_chdr_rst,
|
|
||||||
input wire rfnoc_ctrl_clk,
|
|
||||||
output wire rfnoc_ctrl_rst,
|
|
||||||
// RFNoC Backend Interface
|
// RFNoC Backend Interface
|
||||||
input wire [ 511:0] rfnoc_core_config,
|
input wire [511:0] rfnoc_core_config,
|
||||||
output wire [ 511:0] rfnoc_core_status,
|
output wire [511:0] rfnoc_core_status,
|
||||||
// CHDR Input Ports (from framework)
|
|
||||||
input wire [(CHDR_W*NUM_DATA_I)-1:0] s_rfnoc_chdr_tdata,
|
|
||||||
input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tlast,
|
|
||||||
input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tvalid,
|
|
||||||
output wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tready,
|
|
||||||
// CHDR Output Ports (to framework)
|
|
||||||
output wire [(CHDR_W*NUM_DATA_O)-1:0] m_rfnoc_chdr_tdata,
|
|
||||||
output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tlast,
|
|
||||||
output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tvalid,
|
|
||||||
input wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tready,
|
|
||||||
// AXIS-Ctrl Input Port (from framework)
|
|
||||||
input wire [ 31:0] s_rfnoc_ctrl_tdata,
|
|
||||||
input wire s_rfnoc_ctrl_tlast,
|
|
||||||
input wire s_rfnoc_ctrl_tvalid,
|
|
||||||
output wire s_rfnoc_ctrl_tready,
|
|
||||||
// AXIS-Ctrl Output Port (to framework)
|
|
||||||
output wire [ 31:0] m_rfnoc_ctrl_tdata,
|
|
||||||
output wire m_rfnoc_ctrl_tlast,
|
|
||||||
output wire m_rfnoc_ctrl_tvalid,
|
|
||||||
input wire m_rfnoc_ctrl_tready,
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
// AXIS-CHDR Input Ports (from framework)
|
||||||
// Client Control Port Interface
|
input wire [(0+NUM_PORTS)*CHDR_W-1:0] s_rfnoc_chdr_tdata,
|
||||||
//---------------------------------------------------------------------------
|
input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tlast,
|
||||||
|
input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tvalid,
|
||||||
|
output wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tready,
|
||||||
|
// AXIS-CHDR Output Ports (to framework)
|
||||||
|
output wire [(0+NUM_PORTS)*CHDR_W-1:0] m_rfnoc_chdr_tdata,
|
||||||
|
output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tlast,
|
||||||
|
output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tvalid,
|
||||||
|
input wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tready,
|
||||||
|
|
||||||
// Clock
|
// AXIS-Ctrl Control Input Port (from framework)
|
||||||
input wire ctrlport_clk,
|
input wire [31:0] s_rfnoc_ctrl_tdata,
|
||||||
input wire ctrlport_rst,
|
input wire s_rfnoc_ctrl_tlast,
|
||||||
// Master
|
input wire s_rfnoc_ctrl_tvalid,
|
||||||
output wire m_ctrlport_req_wr,
|
output wire s_rfnoc_ctrl_tready,
|
||||||
output wire m_ctrlport_req_rd,
|
// AXIS-Ctrl Control Output Port (to framework)
|
||||||
output wire [19:0] m_ctrlport_req_addr,
|
output wire [31:0] m_rfnoc_ctrl_tdata,
|
||||||
output wire [31:0] m_ctrlport_req_data,
|
output wire m_rfnoc_ctrl_tlast,
|
||||||
output wire [ 3:0] m_ctrlport_req_byte_en,
|
output wire m_rfnoc_ctrl_tvalid,
|
||||||
output wire m_ctrlport_req_has_time,
|
input wire m_rfnoc_ctrl_tready,
|
||||||
output wire [63:0] m_ctrlport_req_time,
|
|
||||||
input wire m_ctrlport_resp_ack,
|
|
||||||
input wire [ 1:0] m_ctrlport_resp_status,
|
|
||||||
input wire [31:0] m_ctrlport_resp_data,
|
|
||||||
// Slave
|
|
||||||
input wire s_ctrlport_req_wr,
|
|
||||||
input wire s_ctrlport_req_rd,
|
|
||||||
input wire [19:0] s_ctrlport_req_addr,
|
|
||||||
input wire [ 9:0] s_ctrlport_req_portid,
|
|
||||||
input wire [15:0] s_ctrlport_req_rem_epid,
|
|
||||||
input wire [ 9:0] s_ctrlport_req_rem_portid,
|
|
||||||
input wire [31:0] s_ctrlport_req_data,
|
|
||||||
input wire [ 3:0] s_ctrlport_req_byte_en,
|
|
||||||
input wire s_ctrlport_req_has_time,
|
|
||||||
input wire [63:0] s_ctrlport_req_time,
|
|
||||||
output wire s_ctrlport_resp_ack,
|
|
||||||
output wire [ 1:0] s_ctrlport_resp_status,
|
|
||||||
output wire [31:0] s_ctrlport_resp_data,
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------
|
||||||
// Client Data Interface
|
// Client Interface
|
||||||
//---------------------------------------------------------------------------
|
//---------------------
|
||||||
|
|
||||||
// Clock
|
// CtrlPort Clock and Reset
|
||||||
input wire axis_data_clk,
|
output wire ctrlport_clk,
|
||||||
input wire axis_data_rst,
|
output wire ctrlport_rst,
|
||||||
|
// CtrlPort Master
|
||||||
|
output wire m_ctrlport_req_wr,
|
||||||
|
output wire m_ctrlport_req_rd,
|
||||||
|
output wire [19:0] m_ctrlport_req_addr,
|
||||||
|
output wire [31:0] m_ctrlport_req_data,
|
||||||
|
output wire m_ctrlport_req_has_time,
|
||||||
|
output wire [63:0] m_ctrlport_req_time,
|
||||||
|
input wire m_ctrlport_resp_ack,
|
||||||
|
input wire [31:0] m_ctrlport_resp_data,
|
||||||
|
|
||||||
// Output data stream (to user logic)
|
// AXI-Stream Data Clock and Reset
|
||||||
output wire [(NUM_DATA_I*ITEM_W*NIPC)-1:0] m_axis_tdata,
|
output wire axis_data_clk,
|
||||||
output wire [ (NUM_DATA_I*NIPC)-1:0] m_axis_tkeep,
|
output wire axis_data_rst,
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_tlast,
|
// Data Stream to User Logic: in
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_tvalid,
|
output wire [NUM_PORTS*32*1-1:0] m_in_axis_tdata,
|
||||||
input wire [ NUM_DATA_I-1:0] m_axis_tready,
|
output wire [NUM_PORTS*1-1:0] m_in_axis_tkeep,
|
||||||
// Sideband information
|
output wire [NUM_PORTS-1:0] m_in_axis_tlast,
|
||||||
output wire [ (NUM_DATA_I*64)-1:0] m_axis_ttimestamp,
|
output wire [NUM_PORTS-1:0] m_in_axis_tvalid,
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_thas_time,
|
input wire [NUM_PORTS-1:0] m_in_axis_tready,
|
||||||
output wire [ (NUM_DATA_I*16)-1:0] m_axis_tlength,
|
output wire [NUM_PORTS*64-1:0] m_in_axis_ttimestamp,
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_teov,
|
output wire [NUM_PORTS-1:0] m_in_axis_thas_time,
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_teob,
|
output wire [NUM_PORTS*16-1:0] m_in_axis_tlength,
|
||||||
|
output wire [NUM_PORTS-1:0] m_in_axis_teov,
|
||||||
// Input data stream (from user logic)
|
output wire [NUM_PORTS-1:0] m_in_axis_teob,
|
||||||
input wire [(NUM_DATA_O*ITEM_W*NIPC)-1:0] s_axis_tdata,
|
// Data Stream to User Logic: out
|
||||||
input wire [ (NUM_DATA_O*NIPC)-1:0] s_axis_tkeep,
|
input wire [NUM_PORTS*32*1-1:0] s_out_axis_tdata,
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_tlast,
|
input wire [NUM_PORTS*1-1:0] s_out_axis_tkeep,
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_tvalid,
|
input wire [NUM_PORTS-1:0] s_out_axis_tlast,
|
||||||
output wire [ NUM_DATA_O-1:0] s_axis_tready,
|
input wire [NUM_PORTS-1:0] s_out_axis_tvalid,
|
||||||
// Sideband info (sampled on the first cycle of the packet)
|
output wire [NUM_PORTS-1:0] s_out_axis_tready,
|
||||||
input wire [ (NUM_DATA_O*64)-1:0] s_axis_ttimestamp,
|
input wire [NUM_PORTS*64-1:0] s_out_axis_ttimestamp,
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_thas_time,
|
input wire [NUM_PORTS-1:0] s_out_axis_thas_time,
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_teov,
|
input wire [NUM_PORTS-1:0] s_out_axis_teov,
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_teob
|
input wire [NUM_PORTS-1:0] s_out_axis_teob
|
||||||
);
|
);
|
||||||
|
|
||||||
localparam SNK_INFO_FIFO_SIZE = 4;
|
|
||||||
localparam SNK_PYLD_FIFO_SIZE = PYLD_FIFO_SIZE;
|
|
||||||
localparam SRC_INFO_FIFO_SIZE = 4;
|
|
||||||
localparam SRC_PYLD_FIFO_SIZE = (MTU > PYLD_FIFO_SIZE) ? MTU : PYLD_FIFO_SIZE;
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// Backend Interface
|
// Backend Interface
|
||||||
@@ -142,18 +125,18 @@ module noc_shell_ddc #(
|
|||||||
wire [63:0] data_o_flush_done;
|
wire [63:0] data_o_flush_done;
|
||||||
|
|
||||||
backend_iface #(
|
backend_iface #(
|
||||||
.NOC_ID (NOC_ID),
|
.NOC_ID (32'hDDC00000),
|
||||||
.NUM_DATA_I (NUM_DATA_I),
|
.NUM_DATA_I (0+NUM_PORTS),
|
||||||
.NUM_DATA_O (NUM_DATA_O),
|
.NUM_DATA_O (0+NUM_PORTS),
|
||||||
.CTRL_FIFOSIZE (CTRL_FIFO_SIZE),
|
.CTRL_FIFOSIZE ($clog2(64)),
|
||||||
.MTU (MTU)
|
.MTU (MTU)
|
||||||
) backend_iface_i (
|
) backend_iface_i (
|
||||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
||||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||||
.rfnoc_core_config (rfnoc_core_config),
|
.rfnoc_core_config (rfnoc_core_config),
|
||||||
.rfnoc_core_status (rfnoc_core_status),
|
.rfnoc_core_status (rfnoc_core_status),
|
||||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
|
||||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
|
||||||
.data_i_flush_en (data_i_flush_en),
|
.data_i_flush_en (data_i_flush_en),
|
||||||
.data_i_flush_timeout (data_i_flush_timeout),
|
.data_i_flush_timeout (data_i_flush_timeout),
|
||||||
.data_i_flush_active (data_i_flush_active),
|
.data_i_flush_active (data_i_flush_active),
|
||||||
@@ -164,52 +147,71 @@ module noc_shell_ddc #(
|
|||||||
.data_o_flush_done (data_o_flush_done)
|
.data_o_flush_done (data_o_flush_done)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Reset Generation
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
wire ce_rst_pulse;
|
||||||
|
|
||||||
|
pulse_synchronizer #(.MODE ("POSEDGE")) pulse_synchronizer_ce (
|
||||||
|
.clk_a(rfnoc_chdr_clk), .rst_a(1'b0), .pulse_a (rfnoc_chdr_rst), .busy_a (),
|
||||||
|
.clk_b(ce_clk), .pulse_b (ce_rst_pulse)
|
||||||
|
);
|
||||||
|
|
||||||
|
pulse_stretch_min #(.LENGTH(32)) pulse_stretch_min_ce (
|
||||||
|
.clk(ce_clk), .rst(1'b0),
|
||||||
|
.pulse_in(ce_rst_pulse), .pulse_out(ce_rst)
|
||||||
|
);
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// Control Path
|
// Control Path
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
assign ctrlport_clk = ce_clk;
|
||||||
|
assign ctrlport_rst = ce_rst;
|
||||||
|
|
||||||
ctrlport_endpoint #(
|
ctrlport_endpoint #(
|
||||||
.THIS_PORTID (THIS_PORTID ),
|
.THIS_PORTID (THIS_PORTID),
|
||||||
.SYNC_CLKS (0 ),
|
.SYNC_CLKS (0),
|
||||||
.AXIS_CTRL_MST_EN (CTRLPORT_SLV_EN),
|
.AXIS_CTRL_MST_EN (0),
|
||||||
.AXIS_CTRL_SLV_EN (CTRLPORT_MST_EN),
|
.AXIS_CTRL_SLV_EN (1),
|
||||||
.SLAVE_FIFO_SIZE (CTRL_FIFO_SIZE )
|
.SLAVE_FIFO_SIZE ($clog2(64))
|
||||||
) ctrlport_ep_i (
|
) ctrlport_endpoint_i (
|
||||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||||
.ctrlport_clk (ctrlport_clk ),
|
.ctrlport_clk (ctrlport_clk),
|
||||||
.ctrlport_rst (ctrlport_rst ),
|
.ctrlport_rst (ctrlport_rst),
|
||||||
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata ),
|
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
||||||
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast ),
|
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
||||||
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid ),
|
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
||||||
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready ),
|
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
||||||
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata ),
|
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
||||||
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast ),
|
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
||||||
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid ),
|
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
||||||
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready ),
|
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
||||||
.m_ctrlport_req_wr (m_ctrlport_req_wr ),
|
.m_ctrlport_req_wr (m_ctrlport_req_wr),
|
||||||
.m_ctrlport_req_rd (m_ctrlport_req_rd ),
|
.m_ctrlport_req_rd (m_ctrlport_req_rd),
|
||||||
.m_ctrlport_req_addr (m_ctrlport_req_addr ),
|
.m_ctrlport_req_addr (m_ctrlport_req_addr),
|
||||||
.m_ctrlport_req_data (m_ctrlport_req_data ),
|
.m_ctrlport_req_data (m_ctrlport_req_data),
|
||||||
.m_ctrlport_req_byte_en (m_ctrlport_req_byte_en ),
|
.m_ctrlport_req_byte_en (),
|
||||||
.m_ctrlport_req_has_time (m_ctrlport_req_has_time ),
|
.m_ctrlport_req_has_time (m_ctrlport_req_has_time),
|
||||||
.m_ctrlport_req_time (m_ctrlport_req_time ),
|
.m_ctrlport_req_time (m_ctrlport_req_time),
|
||||||
.m_ctrlport_resp_ack (m_ctrlport_resp_ack ),
|
.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
|
||||||
.m_ctrlport_resp_status (m_ctrlport_resp_status ),
|
.m_ctrlport_resp_status (2'b0),
|
||||||
.m_ctrlport_resp_data (m_ctrlport_resp_data ),
|
.m_ctrlport_resp_data (m_ctrlport_resp_data),
|
||||||
.s_ctrlport_req_wr (s_ctrlport_req_wr ),
|
.s_ctrlport_req_wr (1'b0),
|
||||||
.s_ctrlport_req_rd (s_ctrlport_req_rd ),
|
.s_ctrlport_req_rd (1'b0),
|
||||||
.s_ctrlport_req_addr (s_ctrlport_req_addr ),
|
.s_ctrlport_req_addr (20'b0),
|
||||||
.s_ctrlport_req_portid (s_ctrlport_req_portid ),
|
.s_ctrlport_req_portid (10'b0),
|
||||||
.s_ctrlport_req_rem_epid (s_ctrlport_req_rem_epid ),
|
.s_ctrlport_req_rem_epid (16'b0),
|
||||||
.s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
|
.s_ctrlport_req_rem_portid (10'b0),
|
||||||
.s_ctrlport_req_data (s_ctrlport_req_data ),
|
.s_ctrlport_req_data (32'b0),
|
||||||
.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en ),
|
.s_ctrlport_req_byte_en (4'hF),
|
||||||
.s_ctrlport_req_has_time (s_ctrlport_req_has_time ),
|
.s_ctrlport_req_has_time (1'b0),
|
||||||
.s_ctrlport_req_time (s_ctrlport_req_time ),
|
.s_ctrlport_req_time (64'b0),
|
||||||
.s_ctrlport_resp_ack (s_ctrlport_resp_ack ),
|
.s_ctrlport_resp_ack (),
|
||||||
.s_ctrlport_resp_status (s_ctrlport_resp_status ),
|
.s_ctrlport_resp_status (),
|
||||||
.s_ctrlport_resp_data (s_ctrlport_resp_data )
|
.s_ctrlport_resp_data ()
|
||||||
);
|
);
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -217,75 +219,87 @@ module noc_shell_ddc #(
|
|||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
genvar i;
|
genvar i;
|
||||||
generate
|
|
||||||
|
|
||||||
for (i = 0; i < NUM_DATA_I; i = i + 1) begin: chdr_to_data
|
assign axis_data_clk = ce_clk;
|
||||||
chdr_to_axis_data #(
|
assign axis_data_rst = ce_rst;
|
||||||
.CHDR_W (CHDR_W),
|
|
||||||
.ITEM_W (ITEM_W),
|
//---------------------
|
||||||
.NIPC (NIPC),
|
// Input Data Paths
|
||||||
.SYNC_CLKS (0),
|
//---------------------
|
||||||
.INFO_FIFO_SIZE (SNK_INFO_FIFO_SIZE),
|
|
||||||
.PYLD_FIFO_SIZE (SNK_PYLD_FIFO_SIZE)
|
|
||||||
) chdr_to_axis_data_i (
|
|
||||||
.axis_chdr_clk (rfnoc_chdr_clk),
|
|
||||||
.axis_chdr_rst (rfnoc_chdr_rst),
|
|
||||||
.axis_data_clk (axis_data_clk),
|
|
||||||
.axis_data_rst (axis_data_rst),
|
|
||||||
.s_axis_chdr_tdata (s_rfnoc_chdr_tdata [(i*CHDR_W)+:CHDR_W]),
|
|
||||||
.s_axis_chdr_tlast (s_rfnoc_chdr_tlast [i]),
|
|
||||||
.s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid [i]),
|
|
||||||
.s_axis_chdr_tready (s_rfnoc_chdr_tready [i]),
|
|
||||||
.m_axis_tdata (m_axis_tdata [i*ITEM_W*NIPC +: ITEM_W*NIPC]),
|
|
||||||
.m_axis_tkeep (m_axis_tkeep [i*NIPC +: NIPC]),
|
|
||||||
.m_axis_tlast (m_axis_tlast [i]),
|
|
||||||
.m_axis_tvalid (m_axis_tvalid [i]),
|
|
||||||
.m_axis_tready (m_axis_tready [i]),
|
|
||||||
.m_axis_ttimestamp (m_axis_ttimestamp [i*64 +: 64]),
|
|
||||||
.m_axis_thas_time (m_axis_thas_time [i]),
|
|
||||||
.m_axis_tlength (m_axis_tlength [i*16 +: 16]),
|
|
||||||
.m_axis_teov (m_axis_teov [i]),
|
|
||||||
.m_axis_teob (m_axis_teob [i]),
|
|
||||||
.flush_en (data_i_flush_en),
|
|
||||||
.flush_timeout (data_i_flush_timeout),
|
|
||||||
.flush_active (data_i_flush_active [i]),
|
|
||||||
.flush_done (data_i_flush_done [i])
|
|
||||||
);
|
|
||||||
end
|
|
||||||
|
|
||||||
for (i = 0; i < NUM_DATA_O; i = i + 1) begin: data_to_chdr
|
for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_input_in
|
||||||
axis_data_to_chdr #(
|
chdr_to_axis_data #(
|
||||||
.CHDR_W (CHDR_W),
|
.CHDR_W (CHDR_W),
|
||||||
.ITEM_W (ITEM_W),
|
.ITEM_W (32),
|
||||||
.NIPC (NIPC),
|
.NIPC (1),
|
||||||
.SYNC_CLKS (0),
|
.SYNC_CLKS (0),
|
||||||
.INFO_FIFO_SIZE (4),
|
.INFO_FIFO_SIZE ($clog2(32)),
|
||||||
.PYLD_FIFO_SIZE (SRC_INFO_FIFO_SIZE),
|
.PYLD_FIFO_SIZE ($clog2(MTU))
|
||||||
.MTU (SRC_PYLD_FIFO_SIZE)
|
) chdr_to_axis_data_in_in (
|
||||||
) axis_data_to_chdr_i (
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
.axis_chdr_clk (rfnoc_chdr_clk),
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
.axis_chdr_rst (rfnoc_chdr_rst),
|
.axis_data_clk (axis_data_clk),
|
||||||
.axis_data_clk (axis_data_clk),
|
.axis_data_rst (axis_data_rst),
|
||||||
.axis_data_rst (axis_data_rst),
|
.s_axis_chdr_tdata (s_rfnoc_chdr_tdata[((0+i)*CHDR_W)+:CHDR_W]),
|
||||||
.m_axis_chdr_tdata (m_rfnoc_chdr_tdata [i*CHDR_W +: CHDR_W]),
|
.s_axis_chdr_tlast (s_rfnoc_chdr_tlast[0+i]),
|
||||||
.m_axis_chdr_tlast (m_rfnoc_chdr_tlast [i]),
|
.s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[0+i]),
|
||||||
.m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid [i]),
|
.s_axis_chdr_tready (s_rfnoc_chdr_tready[0+i]),
|
||||||
.m_axis_chdr_tready (m_rfnoc_chdr_tready [i]),
|
.m_axis_tdata (m_in_axis_tdata[(32*1)*i+:(32*1)]),
|
||||||
.s_axis_tdata (s_axis_tdata [i*ITEM_W*NIPC +: ITEM_W*NIPC]),
|
.m_axis_tkeep (m_in_axis_tkeep[1*i+:1]),
|
||||||
.s_axis_tkeep (s_axis_tkeep [i*NIPC +: NIPC]),
|
.m_axis_tlast (m_in_axis_tlast[i]),
|
||||||
.s_axis_tlast (s_axis_tlast [i]),
|
.m_axis_tvalid (m_in_axis_tvalid[i]),
|
||||||
.s_axis_tvalid (s_axis_tvalid [i]),
|
.m_axis_tready (m_in_axis_tready[i]),
|
||||||
.s_axis_tready (s_axis_tready [i]),
|
.m_axis_ttimestamp (m_in_axis_ttimestamp[64*i+:64]),
|
||||||
.s_axis_ttimestamp (s_axis_ttimestamp [i*64 +: 64]),
|
.m_axis_thas_time (m_in_axis_thas_time[i]),
|
||||||
.s_axis_thas_time (s_axis_thas_time [i]),
|
.m_axis_tlength (m_in_axis_tlength[i*16+:16]),
|
||||||
.s_axis_teov (s_axis_teov [i]),
|
.m_axis_teov (m_in_axis_teov[i]),
|
||||||
.s_axis_teob (s_axis_teob [i]),
|
.m_axis_teob (m_in_axis_teob[i]),
|
||||||
.flush_en (data_o_flush_en),
|
.flush_en (data_i_flush_en),
|
||||||
.flush_timeout (data_o_flush_timeout),
|
.flush_timeout (data_i_flush_timeout),
|
||||||
.flush_active (data_o_flush_active [i]),
|
.flush_active (data_i_flush_active[0+i]),
|
||||||
.flush_done (data_o_flush_done [i])
|
.flush_done (data_i_flush_done[0+i])
|
||||||
);
|
);
|
||||||
end
|
end
|
||||||
endgenerate
|
|
||||||
|
|
||||||
endmodule
|
//---------------------
|
||||||
|
// Output Data Paths
|
||||||
|
//---------------------
|
||||||
|
|
||||||
|
for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_output_out
|
||||||
|
axis_data_to_chdr #(
|
||||||
|
.CHDR_W (CHDR_W),
|
||||||
|
.ITEM_W (32),
|
||||||
|
.NIPC (1),
|
||||||
|
.SYNC_CLKS (0),
|
||||||
|
.INFO_FIFO_SIZE ($clog2(32)),
|
||||||
|
.PYLD_FIFO_SIZE ($clog2(MTU)),
|
||||||
|
.MTU (MTU)
|
||||||
|
) axis_data_to_chdr_out_out (
|
||||||
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
|
.axis_data_clk (axis_data_clk),
|
||||||
|
.axis_data_rst (axis_data_rst),
|
||||||
|
.m_axis_chdr_tdata (m_rfnoc_chdr_tdata[(0+i)*CHDR_W+:CHDR_W]),
|
||||||
|
.m_axis_chdr_tlast (m_rfnoc_chdr_tlast[0+i]),
|
||||||
|
.m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[0+i]),
|
||||||
|
.m_axis_chdr_tready (m_rfnoc_chdr_tready[0+i]),
|
||||||
|
.s_axis_tdata (s_out_axis_tdata[(32*1)*i+:(32*1)]),
|
||||||
|
.s_axis_tkeep (s_out_axis_tkeep[1*i+:1]),
|
||||||
|
.s_axis_tlast (s_out_axis_tlast[i]),
|
||||||
|
.s_axis_tvalid (s_out_axis_tvalid[i]),
|
||||||
|
.s_axis_tready (s_out_axis_tready[i]),
|
||||||
|
.s_axis_ttimestamp (s_out_axis_ttimestamp[64*i+:64]),
|
||||||
|
.s_axis_thas_time (s_out_axis_thas_time[i]),
|
||||||
|
.s_axis_teov (s_out_axis_teov[i]),
|
||||||
|
.s_axis_teob (s_out_axis_teob[i]),
|
||||||
|
.flush_en (data_o_flush_en),
|
||||||
|
.flush_timeout (data_o_flush_timeout),
|
||||||
|
.flush_active (data_o_flush_active[0+i]),
|
||||||
|
.flush_done (data_o_flush_done[0+i])
|
||||||
|
);
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule // noc_shell_ddc
|
||||||
|
|
||||||
|
|
||||||
|
`default_nettype wire
|
||||||
|
|||||||
@@ -14,8 +14,6 @@
|
|||||||
// NUM_PORTS : Number of DDCs to instantiate
|
// NUM_PORTS : Number of DDCs to instantiate
|
||||||
// MTU : Maximum transmission unit (i.e., maximum packet size) in
|
// MTU : Maximum transmission unit (i.e., maximum packet size) in
|
||||||
// CHDR words is 2**MTU.
|
// CHDR words is 2**MTU.
|
||||||
// CTRL_FIFO_SIZE : Size of the Control Port slave FIFO. This affects the
|
|
||||||
// number of outstanding commands that can be pending.
|
|
||||||
// NUM_HB : Number of half-band decimation blocks to include (0-3)
|
// NUM_HB : Number of half-band decimation blocks to include (0-3)
|
||||||
// CIC_MAX_DECIM : Maximum decimation to support in the CIC filter
|
// CIC_MAX_DECIM : Maximum decimation to support in the CIC filter
|
||||||
//
|
//
|
||||||
@@ -25,7 +23,6 @@ module rfnoc_block_ddc #(
|
|||||||
parameter CHDR_W = 64,
|
parameter CHDR_W = 64,
|
||||||
parameter NUM_PORTS = 2,
|
parameter NUM_PORTS = 2,
|
||||||
parameter MTU = 10,
|
parameter MTU = 10,
|
||||||
parameter CTRL_FIFO_SIZE = 6,
|
|
||||||
parameter NUM_HB = 3,
|
parameter NUM_HB = 3,
|
||||||
parameter CIC_MAX_DECIM = 255
|
parameter CIC_MAX_DECIM = 255
|
||||||
) (
|
) (
|
||||||
@@ -75,8 +72,6 @@ module rfnoc_block_ddc #(
|
|||||||
localparam ITEM_W = 32;
|
localparam ITEM_W = 32;
|
||||||
localparam NIPC = 1;
|
localparam NIPC = 1;
|
||||||
|
|
||||||
localparam NOC_ID = 'hDDC0_0000;
|
|
||||||
|
|
||||||
localparam COMPAT_MAJOR = 16'h0;
|
localparam COMPAT_MAJOR = 16'h0;
|
||||||
localparam COMPAT_MINOR = 16'h0;
|
localparam COMPAT_MINOR = 16'h0;
|
||||||
|
|
||||||
@@ -88,8 +83,6 @@ module rfnoc_block_ddc #(
|
|||||||
// Signal Declarations
|
// Signal Declarations
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
wire rfnoc_chdr_rst;
|
|
||||||
|
|
||||||
wire ctrlport_req_wr;
|
wire ctrlport_req_wr;
|
||||||
wire ctrlport_req_rd;
|
wire ctrlport_req_rd;
|
||||||
wire [19:0] ctrlport_req_addr;
|
wire [19:0] ctrlport_req_addr;
|
||||||
@@ -118,103 +111,74 @@ module rfnoc_block_ddc #(
|
|||||||
wire [ NUM_PORTS*64-1:0] s_axis_data_ttimestamp;
|
wire [ NUM_PORTS*64-1:0] s_axis_data_ttimestamp;
|
||||||
wire [ NUM_PORTS-1:0] s_axis_data_thas_time;
|
wire [ NUM_PORTS-1:0] s_axis_data_thas_time;
|
||||||
|
|
||||||
wire ddc_rst;
|
|
||||||
|
|
||||||
// Cross the CHDR reset to the ce_clk domain
|
|
||||||
synchronizer ddc_rst_sync_i (
|
|
||||||
.clk (ce_clk),
|
|
||||||
.rst (1'b0),
|
|
||||||
.in (rfnoc_chdr_rst),
|
|
||||||
.out (ddc_rst)
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// NoC Shell
|
// NoC Shell
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
wire ce_rst;
|
||||||
|
|
||||||
noc_shell_ddc #(
|
noc_shell_ddc #(
|
||||||
.NOC_ID (NOC_ID),
|
.THIS_PORTID (THIS_PORTID),
|
||||||
.THIS_PORTID (THIS_PORTID),
|
.CHDR_W (CHDR_W),
|
||||||
.CHDR_W (CHDR_W),
|
.MTU (MTU),
|
||||||
.CTRLPORT_SLV_EN (0),
|
.NUM_PORTS (NUM_PORTS)
|
||||||
.CTRLPORT_MST_EN (1),
|
|
||||||
.CTRL_FIFO_SIZE (CTRL_FIFO_SIZE),
|
|
||||||
.NUM_DATA_I (NUM_PORTS),
|
|
||||||
.NUM_DATA_O (NUM_PORTS),
|
|
||||||
.ITEM_W (ITEM_W),
|
|
||||||
.NIPC (NIPC),
|
|
||||||
.PYLD_FIFO_SIZE (MTU),
|
|
||||||
.MTU (MTU)
|
|
||||||
) noc_shell_ddc_i (
|
) noc_shell_ddc_i (
|
||||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
.ce_clk (ce_clk),
|
||||||
.rfnoc_ctrl_rst (),
|
.rfnoc_chdr_rst (),
|
||||||
.rfnoc_core_config (rfnoc_core_config),
|
.rfnoc_ctrl_rst (),
|
||||||
.rfnoc_core_status (rfnoc_core_status),
|
.ce_rst (ce_rst),
|
||||||
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
|
.rfnoc_core_config (rfnoc_core_config),
|
||||||
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
|
.rfnoc_core_status (rfnoc_core_status),
|
||||||
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
|
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
|
||||||
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
|
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
|
||||||
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
|
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
|
||||||
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
|
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
|
||||||
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
|
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
|
||||||
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
|
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
|
||||||
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
|
||||||
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
|
||||||
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
||||||
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
||||||
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
||||||
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
||||||
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
||||||
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
||||||
.ctrlport_clk (ce_clk),
|
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
||||||
.ctrlport_rst (ddc_rst),
|
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
||||||
.m_ctrlport_req_wr (ctrlport_req_wr),
|
.ctrlport_clk (),
|
||||||
.m_ctrlport_req_rd (ctrlport_req_rd),
|
.ctrlport_rst (),
|
||||||
.m_ctrlport_req_addr (ctrlport_req_addr),
|
.m_ctrlport_req_wr (ctrlport_req_wr),
|
||||||
.m_ctrlport_req_data (ctrlport_req_data),
|
.m_ctrlport_req_rd (ctrlport_req_rd),
|
||||||
.m_ctrlport_req_byte_en (),
|
.m_ctrlport_req_addr (ctrlport_req_addr),
|
||||||
.m_ctrlport_req_has_time (ctrlport_req_has_time),
|
.m_ctrlport_req_data (ctrlport_req_data),
|
||||||
.m_ctrlport_req_time (ctrlport_req_time),
|
.m_ctrlport_req_has_time (ctrlport_req_has_time),
|
||||||
.m_ctrlport_resp_ack (ctrlport_resp_ack),
|
.m_ctrlport_req_time (ctrlport_req_time),
|
||||||
.m_ctrlport_resp_status (AXIS_CTRL_STS_OKAY),
|
.m_ctrlport_resp_ack (ctrlport_resp_ack),
|
||||||
.m_ctrlport_resp_data (ctrlport_resp_data),
|
.m_ctrlport_resp_data (ctrlport_resp_data),
|
||||||
.s_ctrlport_req_wr (1'b0),
|
.axis_data_clk (),
|
||||||
.s_ctrlport_req_rd (1'b0),
|
.axis_data_rst (),
|
||||||
.s_ctrlport_req_addr (20'b0),
|
.m_in_axis_tdata (m_axis_data_tdata),
|
||||||
.s_ctrlport_req_portid (10'b0),
|
.m_in_axis_tkeep (),
|
||||||
.s_ctrlport_req_rem_epid (16'b0),
|
.m_in_axis_tlast (m_axis_data_tlast),
|
||||||
.s_ctrlport_req_rem_portid (10'b0),
|
.m_in_axis_tvalid (m_axis_data_tvalid),
|
||||||
.s_ctrlport_req_data (32'b0),
|
.m_in_axis_tready (m_axis_data_tready),
|
||||||
.s_ctrlport_req_byte_en (4'b0),
|
.m_in_axis_ttimestamp (m_axis_data_ttimestamp),
|
||||||
.s_ctrlport_req_has_time (1'b0),
|
.m_in_axis_thas_time (m_axis_data_thas_time),
|
||||||
.s_ctrlport_req_time (64'b0),
|
.m_in_axis_tlength (m_axis_data_tlength),
|
||||||
.s_ctrlport_resp_ack (),
|
.m_in_axis_teov (),
|
||||||
.s_ctrlport_resp_status (),
|
.m_in_axis_teob (m_axis_data_teob),
|
||||||
.s_ctrlport_resp_data (),
|
.s_out_axis_tdata (s_axis_data_tdata),
|
||||||
.axis_data_clk (ce_clk),
|
.s_out_axis_tkeep ({NUM_PORTS*NIPC{1'b1}}),
|
||||||
.axis_data_rst (ddc_rst),
|
.s_out_axis_tlast (s_axis_data_tlast),
|
||||||
.m_axis_tdata (m_axis_data_tdata),
|
.s_out_axis_tvalid (s_axis_data_tvalid),
|
||||||
.m_axis_tkeep (),
|
.s_out_axis_tready (s_axis_data_tready),
|
||||||
.m_axis_tlast (m_axis_data_tlast),
|
.s_out_axis_ttimestamp (s_axis_data_ttimestamp),
|
||||||
.m_axis_tvalid (m_axis_data_tvalid),
|
.s_out_axis_thas_time (s_axis_data_thas_time),
|
||||||
.m_axis_tready (m_axis_data_tready),
|
.s_out_axis_teov ({NUM_PORTS{1'b0}}),
|
||||||
.m_axis_ttimestamp (m_axis_data_ttimestamp),
|
.s_out_axis_teob (s_axis_data_teob)
|
||||||
.m_axis_thas_time (m_axis_data_thas_time),
|
|
||||||
.m_axis_tlength (m_axis_data_tlength),
|
|
||||||
.m_axis_teov (),
|
|
||||||
.m_axis_teob (m_axis_data_teob),
|
|
||||||
.s_axis_tdata (s_axis_data_tdata),
|
|
||||||
.s_axis_tkeep ({NUM_PORTS*NIPC{1'b1}}),
|
|
||||||
.s_axis_tlast (s_axis_data_tlast),
|
|
||||||
.s_axis_tvalid (s_axis_data_tvalid),
|
|
||||||
.s_axis_tready (s_axis_data_tready),
|
|
||||||
.s_axis_ttimestamp (s_axis_data_ttimestamp),
|
|
||||||
.s_axis_thas_time (s_axis_data_thas_time),
|
|
||||||
.s_axis_teov ({NUM_PORTS{1'b0}}),
|
|
||||||
.s_axis_teob (s_axis_data_teob)
|
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
@@ -240,7 +204,7 @@ module rfnoc_block_ddc #(
|
|||||||
.NUM_PORTS (NUM_PORTS)
|
.NUM_PORTS (NUM_PORTS)
|
||||||
) ctrlport_to_settings_bus_i (
|
) ctrlport_to_settings_bus_i (
|
||||||
.ctrlport_clk (ce_clk),
|
.ctrlport_clk (ce_clk),
|
||||||
.ctrlport_rst (ddc_rst),
|
.ctrlport_rst (ce_rst),
|
||||||
.s_ctrlport_req_wr (ctrlport_req_wr),
|
.s_ctrlport_req_wr (ctrlport_req_wr),
|
||||||
.s_ctrlport_req_rd (ctrlport_req_rd),
|
.s_ctrlport_req_rd (ctrlport_req_rd),
|
||||||
.s_ctrlport_req_addr (ctrlport_req_addr),
|
.s_ctrlport_req_addr (ctrlport_req_addr),
|
||||||
@@ -256,7 +220,9 @@ module rfnoc_block_ddc #(
|
|||||||
.set_has_time (set_has_time),
|
.set_has_time (set_has_time),
|
||||||
.rb_stb (rb_stb),
|
.rb_stb (rb_stb),
|
||||||
.rb_addr (rb_addr),
|
.rb_addr (rb_addr),
|
||||||
.rb_data (rb_data));
|
.rb_data (rb_data),
|
||||||
|
.timestamp (64'b0)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -333,7 +299,7 @@ module rfnoc_block_ddc #(
|
|||||||
.SR_TAG_ADDRS(SR_FREQ_ADDR))
|
.SR_TAG_ADDRS(SR_FREQ_ADDR))
|
||||||
axi_tag_time (
|
axi_tag_time (
|
||||||
.clk(ce_clk),
|
.clk(ce_clk),
|
||||||
.reset(ddc_rst),
|
.reset(ce_rst),
|
||||||
.clear(clear_tx_seqnum[i]),
|
.clear(clear_tx_seqnum[i]),
|
||||||
.tick_rate(16'd1),
|
.tick_rate(16'd1),
|
||||||
.timed_cmd_fifo_full(timed_cmd_fifo_full),
|
.timed_cmd_fifo_full(timed_cmd_fifo_full),
|
||||||
@@ -370,7 +336,7 @@ module rfnoc_block_ddc #(
|
|||||||
.SR_M_ADDR(SR_M_ADDR),
|
.SR_M_ADDR(SR_M_ADDR),
|
||||||
.SR_CONFIG_ADDR(SR_CONFIG_ADDR))
|
.SR_CONFIG_ADDR(SR_CONFIG_ADDR))
|
||||||
axi_rate_change (
|
axi_rate_change (
|
||||||
.clk(ce_clk), .reset(ddc_rst), .clear(clear_tx_seqnum[i]), .clear_user(clear_user),
|
.clk(ce_clk), .reset(ce_rst), .clear(clear_tx_seqnum[i]), .clear_user(clear_user),
|
||||||
.src_sid(src_sid[16*i+15:16*i]), .dst_sid(next_dst_sid[16*i+15:16*i]),
|
.src_sid(src_sid[16*i+15:16*i]), .dst_sid(next_dst_sid[16*i+15:16*i]),
|
||||||
.set_stb(out_set_stb), .set_addr(out_set_addr), .set_data(out_set_data),
|
.set_stb(out_set_stb), .set_addr(out_set_addr), .set_data(out_set_data),
|
||||||
.i_tdata({m_axis_tagged_tag,m_axis_tagged_tdata}), .i_tlast(m_axis_tagged_tlast),
|
.i_tdata({m_axis_tagged_tag,m_axis_tagged_tdata}), .i_tlast(m_axis_tagged_tlast),
|
||||||
@@ -403,7 +369,7 @@ module rfnoc_block_ddc #(
|
|||||||
.NUM_HB(NUM_HB),
|
.NUM_HB(NUM_HB),
|
||||||
.CIC_MAX_DECIM(CIC_MAX_DECIM))
|
.CIC_MAX_DECIM(CIC_MAX_DECIM))
|
||||||
ddc (
|
ddc (
|
||||||
.clk(ce_clk), .reset(ddc_rst),
|
.clk(ce_clk), .reset(ce_rst),
|
||||||
.clear(clear_user | clear_tx_seqnum[i]), // Use AXI Rate Change's clear user to reset block to initial state after EOB
|
.clear(clear_user | clear_tx_seqnum[i]), // Use AXI Rate Change's clear user to reset block to initial state after EOB
|
||||||
.set_stb(out_set_stb), .set_addr(out_set_addr), .set_data(out_set_data),
|
.set_stb(out_set_stb), .set_addr(out_set_addr), .set_data(out_set_data),
|
||||||
.timed_set_stb(timed_set_stb), .timed_set_addr(timed_set_addr), .timed_set_data(timed_set_data),
|
.timed_set_stb(timed_set_stb), .timed_set_addr(timed_set_addr), .timed_set_data(timed_set_data),
|
||||||
|
|||||||
@@ -40,6 +40,7 @@ module rfnoc_block_ddc_tb();
|
|||||||
localparam int NUM_PORTS = 1;
|
localparam int NUM_PORTS = 1;
|
||||||
localparam int NUM_HB = 3;
|
localparam int NUM_HB = 3;
|
||||||
localparam int CIC_MAX_DECIM = 255;
|
localparam int CIC_MAX_DECIM = 255;
|
||||||
|
localparam int NOC_ID = 32'hDDC00000;
|
||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -297,7 +298,7 @@ module rfnoc_block_ddc_tb();
|
|||||||
//-------------------------------------------------------------------------
|
//-------------------------------------------------------------------------
|
||||||
|
|
||||||
test.start_test("Verify Block Info", 2us);
|
test.start_test("Verify Block Info", 2us);
|
||||||
`ASSERT_ERROR(blk_ctrl.get_noc_id() == rfnoc_block_ddc_i.NOC_ID, "Incorrect NOC_ID Value");
|
`ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I Value");
|
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O Value");
|
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
|
`ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
|
||||||
|
|||||||
@@ -5,7 +5,7 @@
|
|||||||
#
|
#
|
||||||
|
|
||||||
RFNOC_BLOCK_DUC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_duc/, \
|
RFNOC_BLOCK_DUC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_duc/, \
|
||||||
../rfnoc_block_ddc/noc_shell_ddc.v \
|
noc_shell_duc.v \
|
||||||
rfnoc_block_duc_regs.vh \
|
rfnoc_block_duc_regs.vh \
|
||||||
rfnoc_block_duc.v \
|
rfnoc_block_duc.v \
|
||||||
))
|
))
|
||||||
|
|||||||
@@ -0,0 +1,305 @@
|
|||||||
|
//
|
||||||
|
// Copyright 2019 Ettus Research, A National Instruments Brand
|
||||||
|
//
|
||||||
|
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||||
|
//
|
||||||
|
// Module: noc_shell_duc
|
||||||
|
//
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// This is a tool-generated NoC-shell for the duc block.
|
||||||
|
// See the RFNoC specification for more information about NoC shells.
|
||||||
|
//
|
||||||
|
// Parameters:
|
||||||
|
//
|
||||||
|
// THIS_PORTID : Control crossbar port to which this block is connected
|
||||||
|
// CHDR_W : AXIS-CHDR data bus width
|
||||||
|
// MTU : Maximum transmission unit (i.e., maximum packet size in
|
||||||
|
//
|
||||||
|
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
|
||||||
|
module noc_shell_duc #(
|
||||||
|
parameter [9:0] THIS_PORTID = 10'd0,
|
||||||
|
parameter CHDR_W = 64,
|
||||||
|
parameter [5:0] MTU = 10,
|
||||||
|
parameter NUM_PORTS = 1,
|
||||||
|
parameter NUM_HB = 3,
|
||||||
|
parameter CIC_MAX_INTERP = 255
|
||||||
|
) (
|
||||||
|
//---------------------
|
||||||
|
// Framework Interface
|
||||||
|
//---------------------
|
||||||
|
|
||||||
|
// RFNoC Framework Clocks
|
||||||
|
input wire rfnoc_chdr_clk,
|
||||||
|
input wire rfnoc_ctrl_clk,
|
||||||
|
input wire ce_clk,
|
||||||
|
|
||||||
|
// NoC Shell Generated Resets
|
||||||
|
output wire rfnoc_chdr_rst,
|
||||||
|
output wire rfnoc_ctrl_rst,
|
||||||
|
output wire ce_rst,
|
||||||
|
|
||||||
|
// RFNoC Backend Interface
|
||||||
|
input wire [511:0] rfnoc_core_config,
|
||||||
|
output wire [511:0] rfnoc_core_status,
|
||||||
|
|
||||||
|
// AXIS-CHDR Input Ports (from framework)
|
||||||
|
input wire [(0+NUM_PORTS)*CHDR_W-1:0] s_rfnoc_chdr_tdata,
|
||||||
|
input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tlast,
|
||||||
|
input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tvalid,
|
||||||
|
output wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tready,
|
||||||
|
// AXIS-CHDR Output Ports (to framework)
|
||||||
|
output wire [(0+NUM_PORTS)*CHDR_W-1:0] m_rfnoc_chdr_tdata,
|
||||||
|
output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tlast,
|
||||||
|
output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tvalid,
|
||||||
|
input wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tready,
|
||||||
|
|
||||||
|
// AXIS-Ctrl Control Input Port (from framework)
|
||||||
|
input wire [31:0] s_rfnoc_ctrl_tdata,
|
||||||
|
input wire s_rfnoc_ctrl_tlast,
|
||||||
|
input wire s_rfnoc_ctrl_tvalid,
|
||||||
|
output wire s_rfnoc_ctrl_tready,
|
||||||
|
// AXIS-Ctrl Control Output Port (to framework)
|
||||||
|
output wire [31:0] m_rfnoc_ctrl_tdata,
|
||||||
|
output wire m_rfnoc_ctrl_tlast,
|
||||||
|
output wire m_rfnoc_ctrl_tvalid,
|
||||||
|
input wire m_rfnoc_ctrl_tready,
|
||||||
|
|
||||||
|
//---------------------
|
||||||
|
// Client Interface
|
||||||
|
//---------------------
|
||||||
|
|
||||||
|
// CtrlPort Clock and Reset
|
||||||
|
output wire ctrlport_clk,
|
||||||
|
output wire ctrlport_rst,
|
||||||
|
// CtrlPort Master
|
||||||
|
output wire m_ctrlport_req_wr,
|
||||||
|
output wire m_ctrlport_req_rd,
|
||||||
|
output wire [19:0] m_ctrlport_req_addr,
|
||||||
|
output wire [31:0] m_ctrlport_req_data,
|
||||||
|
output wire m_ctrlport_req_has_time,
|
||||||
|
output wire [63:0] m_ctrlport_req_time,
|
||||||
|
input wire m_ctrlport_resp_ack,
|
||||||
|
input wire [31:0] m_ctrlport_resp_data,
|
||||||
|
|
||||||
|
// AXI-Stream Data Clock and Reset
|
||||||
|
output wire axis_data_clk,
|
||||||
|
output wire axis_data_rst,
|
||||||
|
// Data Stream to User Logic: in
|
||||||
|
output wire [NUM_PORTS*32*1-1:0] m_in_axis_tdata,
|
||||||
|
output wire [NUM_PORTS*1-1:0] m_in_axis_tkeep,
|
||||||
|
output wire [NUM_PORTS-1:0] m_in_axis_tlast,
|
||||||
|
output wire [NUM_PORTS-1:0] m_in_axis_tvalid,
|
||||||
|
input wire [NUM_PORTS-1:0] m_in_axis_tready,
|
||||||
|
output wire [NUM_PORTS*64-1:0] m_in_axis_ttimestamp,
|
||||||
|
output wire [NUM_PORTS-1:0] m_in_axis_thas_time,
|
||||||
|
output wire [NUM_PORTS*16-1:0] m_in_axis_tlength,
|
||||||
|
output wire [NUM_PORTS-1:0] m_in_axis_teov,
|
||||||
|
output wire [NUM_PORTS-1:0] m_in_axis_teob,
|
||||||
|
// Data Stream to User Logic: out
|
||||||
|
input wire [NUM_PORTS*32*1-1:0] s_out_axis_tdata,
|
||||||
|
input wire [NUM_PORTS*1-1:0] s_out_axis_tkeep,
|
||||||
|
input wire [NUM_PORTS-1:0] s_out_axis_tlast,
|
||||||
|
input wire [NUM_PORTS-1:0] s_out_axis_tvalid,
|
||||||
|
output wire [NUM_PORTS-1:0] s_out_axis_tready,
|
||||||
|
input wire [NUM_PORTS*64-1:0] s_out_axis_ttimestamp,
|
||||||
|
input wire [NUM_PORTS-1:0] s_out_axis_thas_time,
|
||||||
|
input wire [NUM_PORTS-1:0] s_out_axis_teov,
|
||||||
|
input wire [NUM_PORTS-1:0] s_out_axis_teob
|
||||||
|
);
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Backend Interface
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
wire data_i_flush_en;
|
||||||
|
wire [31:0] data_i_flush_timeout;
|
||||||
|
wire [63:0] data_i_flush_active;
|
||||||
|
wire [63:0] data_i_flush_done;
|
||||||
|
wire data_o_flush_en;
|
||||||
|
wire [31:0] data_o_flush_timeout;
|
||||||
|
wire [63:0] data_o_flush_active;
|
||||||
|
wire [63:0] data_o_flush_done;
|
||||||
|
|
||||||
|
backend_iface #(
|
||||||
|
.NOC_ID (32'hD0C00000),
|
||||||
|
.NUM_DATA_I (0+NUM_PORTS),
|
||||||
|
.NUM_DATA_O (0+NUM_PORTS),
|
||||||
|
.CTRL_FIFOSIZE ($clog2(64)),
|
||||||
|
.MTU (MTU)
|
||||||
|
) backend_iface_i (
|
||||||
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
||||||
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||||
|
.rfnoc_core_config (rfnoc_core_config),
|
||||||
|
.rfnoc_core_status (rfnoc_core_status),
|
||||||
|
.data_i_flush_en (data_i_flush_en),
|
||||||
|
.data_i_flush_timeout (data_i_flush_timeout),
|
||||||
|
.data_i_flush_active (data_i_flush_active),
|
||||||
|
.data_i_flush_done (data_i_flush_done),
|
||||||
|
.data_o_flush_en (data_o_flush_en),
|
||||||
|
.data_o_flush_timeout (data_o_flush_timeout),
|
||||||
|
.data_o_flush_active (data_o_flush_active),
|
||||||
|
.data_o_flush_done (data_o_flush_done)
|
||||||
|
);
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Reset Generation
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
wire ce_rst_pulse;
|
||||||
|
|
||||||
|
pulse_synchronizer #(.MODE ("POSEDGE")) pulse_synchronizer_ce (
|
||||||
|
.clk_a(rfnoc_chdr_clk), .rst_a(1'b0), .pulse_a (rfnoc_chdr_rst), .busy_a (),
|
||||||
|
.clk_b(ce_clk), .pulse_b (ce_rst_pulse)
|
||||||
|
);
|
||||||
|
|
||||||
|
pulse_stretch_min #(.LENGTH(32)) pulse_stretch_min_ce (
|
||||||
|
.clk(ce_clk), .rst(1'b0),
|
||||||
|
.pulse_in(ce_rst_pulse), .pulse_out(ce_rst)
|
||||||
|
);
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Control Path
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
assign ctrlport_clk = ce_clk;
|
||||||
|
assign ctrlport_rst = ce_rst;
|
||||||
|
|
||||||
|
ctrlport_endpoint #(
|
||||||
|
.THIS_PORTID (THIS_PORTID),
|
||||||
|
.SYNC_CLKS (0),
|
||||||
|
.AXIS_CTRL_MST_EN (0),
|
||||||
|
.AXIS_CTRL_SLV_EN (1),
|
||||||
|
.SLAVE_FIFO_SIZE ($clog2(64))
|
||||||
|
) ctrlport_endpoint_i (
|
||||||
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||||
|
.ctrlport_clk (ctrlport_clk),
|
||||||
|
.ctrlport_rst (ctrlport_rst),
|
||||||
|
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
||||||
|
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
||||||
|
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
||||||
|
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
||||||
|
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
||||||
|
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
||||||
|
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
||||||
|
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
||||||
|
.m_ctrlport_req_wr (m_ctrlport_req_wr),
|
||||||
|
.m_ctrlport_req_rd (m_ctrlport_req_rd),
|
||||||
|
.m_ctrlport_req_addr (m_ctrlport_req_addr),
|
||||||
|
.m_ctrlport_req_data (m_ctrlport_req_data),
|
||||||
|
.m_ctrlport_req_byte_en (),
|
||||||
|
.m_ctrlport_req_has_time (m_ctrlport_req_has_time),
|
||||||
|
.m_ctrlport_req_time (m_ctrlport_req_time),
|
||||||
|
.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
|
||||||
|
.m_ctrlport_resp_status (2'b0),
|
||||||
|
.m_ctrlport_resp_data (m_ctrlport_resp_data),
|
||||||
|
.s_ctrlport_req_wr (1'b0),
|
||||||
|
.s_ctrlport_req_rd (1'b0),
|
||||||
|
.s_ctrlport_req_addr (20'b0),
|
||||||
|
.s_ctrlport_req_portid (10'b0),
|
||||||
|
.s_ctrlport_req_rem_epid (16'b0),
|
||||||
|
.s_ctrlport_req_rem_portid (10'b0),
|
||||||
|
.s_ctrlport_req_data (32'b0),
|
||||||
|
.s_ctrlport_req_byte_en (4'hF),
|
||||||
|
.s_ctrlport_req_has_time (1'b0),
|
||||||
|
.s_ctrlport_req_time (64'b0),
|
||||||
|
.s_ctrlport_resp_ack (),
|
||||||
|
.s_ctrlport_resp_status (),
|
||||||
|
.s_ctrlport_resp_data ()
|
||||||
|
);
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Data Path
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
genvar i;
|
||||||
|
|
||||||
|
assign axis_data_clk = ce_clk;
|
||||||
|
assign axis_data_rst = ce_rst;
|
||||||
|
|
||||||
|
//---------------------
|
||||||
|
// Input Data Paths
|
||||||
|
//---------------------
|
||||||
|
|
||||||
|
for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_input_in
|
||||||
|
chdr_to_axis_data #(
|
||||||
|
.CHDR_W (CHDR_W),
|
||||||
|
.ITEM_W (32),
|
||||||
|
.NIPC (1),
|
||||||
|
.SYNC_CLKS (0),
|
||||||
|
.INFO_FIFO_SIZE ($clog2(32)),
|
||||||
|
.PYLD_FIFO_SIZE ($clog2(MTU))
|
||||||
|
) chdr_to_axis_data_in_in (
|
||||||
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
|
.axis_data_clk (axis_data_clk),
|
||||||
|
.axis_data_rst (axis_data_rst),
|
||||||
|
.s_axis_chdr_tdata (s_rfnoc_chdr_tdata[((0+i)*CHDR_W)+:CHDR_W]),
|
||||||
|
.s_axis_chdr_tlast (s_rfnoc_chdr_tlast[0+i]),
|
||||||
|
.s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[0+i]),
|
||||||
|
.s_axis_chdr_tready (s_rfnoc_chdr_tready[0+i]),
|
||||||
|
.m_axis_tdata (m_in_axis_tdata[(32*1)*i+:(32*1)]),
|
||||||
|
.m_axis_tkeep (m_in_axis_tkeep[1*i+:1]),
|
||||||
|
.m_axis_tlast (m_in_axis_tlast[i]),
|
||||||
|
.m_axis_tvalid (m_in_axis_tvalid[i]),
|
||||||
|
.m_axis_tready (m_in_axis_tready[i]),
|
||||||
|
.m_axis_ttimestamp (m_in_axis_ttimestamp[64*i+:64]),
|
||||||
|
.m_axis_thas_time (m_in_axis_thas_time[i]),
|
||||||
|
.m_axis_tlength (m_in_axis_tlength[i*16+:16]),
|
||||||
|
.m_axis_teov (m_in_axis_teov[i]),
|
||||||
|
.m_axis_teob (m_in_axis_teob[i]),
|
||||||
|
.flush_en (data_i_flush_en),
|
||||||
|
.flush_timeout (data_i_flush_timeout),
|
||||||
|
.flush_active (data_i_flush_active[0+i]),
|
||||||
|
.flush_done (data_i_flush_done[0+i])
|
||||||
|
);
|
||||||
|
end
|
||||||
|
|
||||||
|
//---------------------
|
||||||
|
// Output Data Paths
|
||||||
|
//---------------------
|
||||||
|
|
||||||
|
for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_output_out
|
||||||
|
axis_data_to_chdr #(
|
||||||
|
.CHDR_W (CHDR_W),
|
||||||
|
.ITEM_W (32),
|
||||||
|
.NIPC (1),
|
||||||
|
.SYNC_CLKS (0),
|
||||||
|
.INFO_FIFO_SIZE ($clog2(32)),
|
||||||
|
.PYLD_FIFO_SIZE ($clog2(MTU)),
|
||||||
|
.MTU (MTU)
|
||||||
|
) axis_data_to_chdr_out_out (
|
||||||
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
|
.axis_data_clk (axis_data_clk),
|
||||||
|
.axis_data_rst (axis_data_rst),
|
||||||
|
.m_axis_chdr_tdata (m_rfnoc_chdr_tdata[(0+i)*CHDR_W+:CHDR_W]),
|
||||||
|
.m_axis_chdr_tlast (m_rfnoc_chdr_tlast[0+i]),
|
||||||
|
.m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[0+i]),
|
||||||
|
.m_axis_chdr_tready (m_rfnoc_chdr_tready[0+i]),
|
||||||
|
.s_axis_tdata (s_out_axis_tdata[(32*1)*i+:(32*1)]),
|
||||||
|
.s_axis_tkeep (s_out_axis_tkeep[1*i+:1]),
|
||||||
|
.s_axis_tlast (s_out_axis_tlast[i]),
|
||||||
|
.s_axis_tvalid (s_out_axis_tvalid[i]),
|
||||||
|
.s_axis_tready (s_out_axis_tready[i]),
|
||||||
|
.s_axis_ttimestamp (s_out_axis_ttimestamp[64*i+:64]),
|
||||||
|
.s_axis_thas_time (s_out_axis_thas_time[i]),
|
||||||
|
.s_axis_teov (s_out_axis_teov[i]),
|
||||||
|
.s_axis_teob (s_out_axis_teob[i]),
|
||||||
|
.flush_en (data_o_flush_en),
|
||||||
|
.flush_timeout (data_o_flush_timeout),
|
||||||
|
.flush_active (data_o_flush_active[0+i]),
|
||||||
|
.flush_done (data_o_flush_done[0+i])
|
||||||
|
);
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule // noc_shell_duc
|
||||||
|
|
||||||
|
|
||||||
|
`default_nettype wire
|
||||||
@@ -14,8 +14,6 @@
|
|||||||
// NUM_PORTS : Number of DUC signal processing chains
|
// NUM_PORTS : Number of DUC signal processing chains
|
||||||
// MTU : Maximum transmission unit (i.e., maximum packet size) in
|
// MTU : Maximum transmission unit (i.e., maximum packet size) in
|
||||||
// CHDR words is 2**MTU.
|
// CHDR words is 2**MTU.
|
||||||
// CTRL_FIFO_SIZE : Size of the Control Port slave FIFO. This affects the
|
|
||||||
// number of outstanding commands that can be pending.
|
|
||||||
// NUM_HB : Number of half-band filter blocks to include (0-3)
|
// NUM_HB : Number of half-band filter blocks to include (0-3)
|
||||||
// CIC_MAX_INTERP : Maximum interpolation to support in the CIC filter
|
// CIC_MAX_INTERP : Maximum interpolation to support in the CIC filter
|
||||||
//
|
//
|
||||||
@@ -25,7 +23,6 @@ module rfnoc_block_duc #(
|
|||||||
parameter CHDR_W = 64,
|
parameter CHDR_W = 64,
|
||||||
parameter NUM_PORTS = 2,
|
parameter NUM_PORTS = 2,
|
||||||
parameter MTU = 10,
|
parameter MTU = 10,
|
||||||
parameter CTRL_FIFO_SIZE = 6,
|
|
||||||
parameter NUM_HB = 2,
|
parameter NUM_HB = 2,
|
||||||
parameter CIC_MAX_INTERP = 128
|
parameter CIC_MAX_INTERP = 128
|
||||||
) (
|
) (
|
||||||
@@ -75,8 +72,6 @@ module rfnoc_block_duc #(
|
|||||||
localparam ITEM_W = 32;
|
localparam ITEM_W = 32;
|
||||||
localparam NIPC = 1;
|
localparam NIPC = 1;
|
||||||
|
|
||||||
localparam NOC_ID = 'hD0C0_0000;
|
|
||||||
|
|
||||||
localparam COMPAT_MAJOR = 16'h0;
|
localparam COMPAT_MAJOR = 16'h0;
|
||||||
localparam COMPAT_MINOR = 16'h0;
|
localparam COMPAT_MINOR = 16'h0;
|
||||||
|
|
||||||
@@ -88,8 +83,6 @@ module rfnoc_block_duc #(
|
|||||||
// Signal Declarations
|
// Signal Declarations
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
wire rfnoc_chdr_rst;
|
|
||||||
|
|
||||||
wire ctrlport_req_wr;
|
wire ctrlport_req_wr;
|
||||||
wire ctrlport_req_rd;
|
wire ctrlport_req_rd;
|
||||||
wire [19:0] ctrlport_req_addr;
|
wire [19:0] ctrlport_req_addr;
|
||||||
@@ -118,104 +111,74 @@ module rfnoc_block_duc #(
|
|||||||
wire [ NUM_PORTS*64-1:0] s_axis_data_ttimestamp;
|
wire [ NUM_PORTS*64-1:0] s_axis_data_ttimestamp;
|
||||||
wire [ NUM_PORTS-1:0] s_axis_data_thas_time;
|
wire [ NUM_PORTS-1:0] s_axis_data_thas_time;
|
||||||
|
|
||||||
wire duc_rst;
|
|
||||||
|
|
||||||
// Cross the CHDR reset to the ce_clk domain
|
|
||||||
synchronizer duc_rst_sync_i (
|
|
||||||
.clk (ce_clk),
|
|
||||||
.rst (1'b0),
|
|
||||||
.in (rfnoc_chdr_rst),
|
|
||||||
.out (duc_rst)
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// NoC Shell
|
// NoC Shell
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
// TODO: Replace noc_shell_radio with a customized block
|
wire ce_rst;
|
||||||
noc_shell_ddc #(
|
|
||||||
.NOC_ID (NOC_ID),
|
noc_shell_duc #(
|
||||||
.THIS_PORTID (THIS_PORTID),
|
.THIS_PORTID (THIS_PORTID),
|
||||||
.CHDR_W (CHDR_W),
|
.CHDR_W (CHDR_W),
|
||||||
.CTRLPORT_SLV_EN (0),
|
.MTU (MTU),
|
||||||
.CTRLPORT_MST_EN (1),
|
.NUM_PORTS (NUM_PORTS)
|
||||||
.CTRL_FIFO_SIZE (CTRL_FIFO_SIZE),
|
) noc_shell_duc_i (
|
||||||
.NUM_DATA_I (NUM_PORTS),
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||||
.NUM_DATA_O (NUM_PORTS),
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
.ITEM_W (ITEM_W),
|
.ce_clk (ce_clk),
|
||||||
.NIPC (NIPC),
|
.rfnoc_chdr_rst (),
|
||||||
.PYLD_FIFO_SIZE (MTU),
|
.rfnoc_ctrl_rst (),
|
||||||
.MTU (MTU)
|
.ce_rst (ce_rst),
|
||||||
) noc_shell_ddc_i (
|
.rfnoc_core_config (rfnoc_core_config),
|
||||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
.rfnoc_core_status (rfnoc_core_status),
|
||||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
|
||||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
|
||||||
.rfnoc_ctrl_rst (),
|
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
|
||||||
.rfnoc_core_config (rfnoc_core_config),
|
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
|
||||||
.rfnoc_core_status (rfnoc_core_status),
|
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
|
||||||
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
|
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
|
||||||
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
|
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
|
||||||
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
|
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
|
||||||
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
|
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
||||||
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
|
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
||||||
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
|
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
||||||
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
|
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
||||||
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
|
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
||||||
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
||||||
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
||||||
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
||||||
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
.ctrlport_clk (),
|
||||||
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
.ctrlport_rst (),
|
||||||
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
.m_ctrlport_req_wr (ctrlport_req_wr),
|
||||||
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
.m_ctrlport_req_rd (ctrlport_req_rd),
|
||||||
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
.m_ctrlport_req_addr (ctrlport_req_addr),
|
||||||
.ctrlport_clk (ce_clk),
|
.m_ctrlport_req_data (ctrlport_req_data),
|
||||||
.ctrlport_rst (duc_rst),
|
.m_ctrlport_req_has_time (ctrlport_req_has_time),
|
||||||
.m_ctrlport_req_wr (ctrlport_req_wr),
|
.m_ctrlport_req_time (ctrlport_req_time),
|
||||||
.m_ctrlport_req_rd (ctrlport_req_rd),
|
.m_ctrlport_resp_ack (ctrlport_resp_ack),
|
||||||
.m_ctrlport_req_addr (ctrlport_req_addr),
|
.m_ctrlport_resp_data (ctrlport_resp_data),
|
||||||
.m_ctrlport_req_data (ctrlport_req_data),
|
.axis_data_clk (),
|
||||||
.m_ctrlport_req_byte_en (),
|
.axis_data_rst (),
|
||||||
.m_ctrlport_req_has_time (ctrlport_req_has_time),
|
.m_in_axis_tdata (m_axis_data_tdata),
|
||||||
.m_ctrlport_req_time (ctrlport_req_time),
|
.m_in_axis_tkeep (),
|
||||||
.m_ctrlport_resp_ack (ctrlport_resp_ack),
|
.m_in_axis_tlast (m_axis_data_tlast),
|
||||||
.m_ctrlport_resp_status (AXIS_CTRL_STS_OKAY),
|
.m_in_axis_tvalid (m_axis_data_tvalid),
|
||||||
.m_ctrlport_resp_data (ctrlport_resp_data),
|
.m_in_axis_tready (m_axis_data_tready),
|
||||||
.s_ctrlport_req_wr (1'b0),
|
.m_in_axis_ttimestamp (m_axis_data_ttimestamp),
|
||||||
.s_ctrlport_req_rd (1'b0),
|
.m_in_axis_thas_time (m_axis_data_thas_time),
|
||||||
.s_ctrlport_req_addr (20'b0),
|
.m_in_axis_tlength (m_axis_data_tlength),
|
||||||
.s_ctrlport_req_portid (10'b0),
|
.m_in_axis_teov (),
|
||||||
.s_ctrlport_req_rem_epid (16'b0),
|
.m_in_axis_teob (m_axis_data_teob),
|
||||||
.s_ctrlport_req_rem_portid (10'b0),
|
.s_out_axis_tdata (s_axis_data_tdata),
|
||||||
.s_ctrlport_req_data (32'b0),
|
.s_out_axis_tkeep ({NUM_PORTS*NIPC{1'b1}}),
|
||||||
.s_ctrlport_req_byte_en (4'b0),
|
.s_out_axis_tlast (s_axis_data_tlast),
|
||||||
.s_ctrlport_req_has_time (1'b0),
|
.s_out_axis_tvalid (s_axis_data_tvalid),
|
||||||
.s_ctrlport_req_time (64'b0),
|
.s_out_axis_tready (s_axis_data_tready),
|
||||||
.s_ctrlport_resp_ack (),
|
.s_out_axis_ttimestamp (s_axis_data_ttimestamp),
|
||||||
.s_ctrlport_resp_status (),
|
.s_out_axis_thas_time (s_axis_data_thas_time),
|
||||||
.s_ctrlport_resp_data (),
|
.s_out_axis_teov ({NUM_PORTS{1'b0}}),
|
||||||
.axis_data_clk (ce_clk),
|
.s_out_axis_teob (s_axis_data_teob)
|
||||||
.axis_data_rst (duc_rst),
|
|
||||||
.m_axis_tdata (m_axis_data_tdata),
|
|
||||||
.m_axis_tkeep (),
|
|
||||||
.m_axis_tlast (m_axis_data_tlast),
|
|
||||||
.m_axis_tvalid (m_axis_data_tvalid),
|
|
||||||
.m_axis_tready (m_axis_data_tready),
|
|
||||||
.m_axis_ttimestamp (m_axis_data_ttimestamp),
|
|
||||||
.m_axis_thas_time (m_axis_data_thas_time),
|
|
||||||
.m_axis_tlength (m_axis_data_tlength),
|
|
||||||
.m_axis_teov (),
|
|
||||||
.m_axis_teob (m_axis_data_teob),
|
|
||||||
.s_axis_tdata (s_axis_data_tdata),
|
|
||||||
.s_axis_tkeep ({NUM_PORTS*NIPC{1'b1}}),
|
|
||||||
.s_axis_tlast (s_axis_data_tlast),
|
|
||||||
.s_axis_tvalid (s_axis_data_tvalid),
|
|
||||||
.s_axis_tready (s_axis_data_tready),
|
|
||||||
.s_axis_ttimestamp (s_axis_data_ttimestamp),
|
|
||||||
.s_axis_thas_time (s_axis_data_thas_time),
|
|
||||||
.s_axis_teov ({NUM_PORTS{1'b0}}),
|
|
||||||
.s_axis_teob (s_axis_data_teob)
|
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
@@ -240,7 +203,7 @@ module rfnoc_block_duc #(
|
|||||||
.NUM_PORTS (NUM_PORTS)
|
.NUM_PORTS (NUM_PORTS)
|
||||||
) ctrlport_to_settings_bus_i (
|
) ctrlport_to_settings_bus_i (
|
||||||
.ctrlport_clk (ce_clk),
|
.ctrlport_clk (ce_clk),
|
||||||
.ctrlport_rst (duc_rst),
|
.ctrlport_rst (ce_rst),
|
||||||
.s_ctrlport_req_wr (ctrlport_req_wr),
|
.s_ctrlport_req_wr (ctrlport_req_wr),
|
||||||
.s_ctrlport_req_rd (ctrlport_req_rd),
|
.s_ctrlport_req_rd (ctrlport_req_rd),
|
||||||
.s_ctrlport_req_addr (ctrlport_req_addr),
|
.s_ctrlport_req_addr (ctrlport_req_addr),
|
||||||
@@ -256,7 +219,9 @@ module rfnoc_block_duc #(
|
|||||||
.set_has_time (set_has_time),
|
.set_has_time (set_has_time),
|
||||||
.rb_stb ({NUM_PORTS{1'b1}}),
|
.rb_stb ({NUM_PORTS{1'b1}}),
|
||||||
.rb_addr (rb_addr),
|
.rb_addr (rb_addr),
|
||||||
.rb_data (rb_data));
|
.rb_data (rb_data),
|
||||||
|
.timestamp (64'b0)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -328,7 +293,7 @@ module rfnoc_block_duc #(
|
|||||||
.SR_FREQ_ADDR(SR_FREQ_ADDR),
|
.SR_FREQ_ADDR(SR_FREQ_ADDR),
|
||||||
.SR_SCALE_IQ_ADDR(SR_SCALE_IQ_ADDR))
|
.SR_SCALE_IQ_ADDR(SR_SCALE_IQ_ADDR))
|
||||||
dds_timed (
|
dds_timed (
|
||||||
.clk(ce_clk), .reset(duc_rst), .clear(clear_tx_seqnum[i]),
|
.clk(ce_clk), .reset(ce_rst), .clear(clear_tx_seqnum[i]),
|
||||||
.timed_cmd_fifo_full(),
|
.timed_cmd_fifo_full(),
|
||||||
.set_stb(set_stb_int), .set_addr(set_addr_int), .set_data(set_data_int),
|
.set_stb(set_stb_int), .set_addr(set_addr_int), .set_data(set_data_int),
|
||||||
.set_time(set_time_int), .set_has_time(set_has_time_int),
|
.set_time(set_time_int), .set_has_time(set_has_time_int),
|
||||||
@@ -353,7 +318,7 @@ module rfnoc_block_duc #(
|
|||||||
.SR_M_ADDR(SR_M_ADDR),
|
.SR_M_ADDR(SR_M_ADDR),
|
||||||
.SR_CONFIG_ADDR(SR_CONFIG_ADDR))
|
.SR_CONFIG_ADDR(SR_CONFIG_ADDR))
|
||||||
axi_rate_change (
|
axi_rate_change (
|
||||||
.clk(ce_clk), .reset(duc_rst), .clear(clear_tx_seqnum[i]), .clear_user(clear_user),
|
.clk(ce_clk), .reset(ce_rst), .clear(clear_tx_seqnum[i]), .clear_user(clear_user),
|
||||||
.src_sid(src_sid[16*i+15:16*i]), .dst_sid(next_dst_sid[16*i+15:16*i]),
|
.src_sid(src_sid[16*i+15:16*i]), .dst_sid(next_dst_sid[16*i+15:16*i]),
|
||||||
.set_stb(set_stb_int), .set_addr(set_addr_int), .set_data(set_data_int),
|
.set_stb(set_stb_int), .set_addr(set_addr_int), .set_data(set_data_int),
|
||||||
.i_tdata(m_axis_data_tdata[ITEM_W*i+:ITEM_W]), .i_tlast(m_axis_data_tlast[i]), .i_tvalid(m_axis_data_tvalid[i]),
|
.i_tdata(m_axis_data_tdata[ITEM_W*i+:ITEM_W]), .i_tlast(m_axis_data_tlast[i]), .i_tvalid(m_axis_data_tvalid[i]),
|
||||||
@@ -376,7 +341,7 @@ module rfnoc_block_duc #(
|
|||||||
.NUM_HB(NUM_HB),
|
.NUM_HB(NUM_HB),
|
||||||
.CIC_MAX_INTERP(CIC_MAX_INTERP))
|
.CIC_MAX_INTERP(CIC_MAX_INTERP))
|
||||||
duc (
|
duc (
|
||||||
.clk(ce_clk), .reset(duc_rst), .clear(clear_duc),
|
.clk(ce_clk), .reset(ce_rst), .clear(clear_duc),
|
||||||
.set_stb(set_stb_int), .set_addr(set_addr_int), .set_data(set_data_int),
|
.set_stb(set_stb_int), .set_addr(set_addr_int), .set_data(set_data_int),
|
||||||
.i_tdata(sample_tdata), .i_tuser(128'b0), .i_tvalid(sample_tvalid), .i_tready(sample_tready),
|
.i_tdata(sample_tdata), .i_tuser(128'b0), .i_tvalid(sample_tvalid), .i_tready(sample_tready),
|
||||||
.o_tdata(sample_duc_tdata), .o_tuser(), .o_tvalid(sample_duc_tvalid), .o_tready(sample_duc_tready));
|
.o_tdata(sample_duc_tdata), .o_tuser(), .o_tvalid(sample_duc_tvalid), .o_tready(sample_duc_tready));
|
||||||
|
|||||||
@@ -40,6 +40,7 @@ module rfnoc_block_duc_tb();
|
|||||||
localparam int NUM_PORTS = 1;
|
localparam int NUM_PORTS = 1;
|
||||||
localparam int NUM_HB = 3;
|
localparam int NUM_HB = 3;
|
||||||
localparam int CIC_MAX_INTERP = 128;
|
localparam int CIC_MAX_INTERP = 128;
|
||||||
|
localparam int NOC_ID = 32'hD0C00000;
|
||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -304,7 +305,7 @@ module rfnoc_block_duc_tb();
|
|||||||
//-------------------------------------------------------------------------
|
//-------------------------------------------------------------------------
|
||||||
|
|
||||||
test.start_test("Verify Block Info", 2us);
|
test.start_test("Verify Block Info", 2us);
|
||||||
`ASSERT_ERROR(blk_ctrl.get_noc_id() == rfnoc_block_duc_i.NOC_ID, "Incorrect NOC_ID value");
|
`ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I value");
|
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O value");
|
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU value");
|
`ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU value");
|
||||||
|
|||||||
@@ -1,131 +1,117 @@
|
|||||||
//
|
//
|
||||||
// Copyright 2019 Ettus Research, A National Instruments Company
|
// Copyright 2019 Ettus Research, A National Instruments Brand
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||||
//
|
//
|
||||||
// Module: noc_shell_fft
|
// Module: noc_shell_fft
|
||||||
//
|
//
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// This is a tool-generated NoC-shell for the fft block.
|
||||||
|
// See the RFNoC specification for more information about NoC shells.
|
||||||
|
//
|
||||||
|
// Parameters:
|
||||||
|
//
|
||||||
|
// THIS_PORTID : Control crossbar port to which this block is connected
|
||||||
|
// CHDR_W : AXIS-CHDR data bus width
|
||||||
|
// MTU : Maximum transmission unit (i.e., maximum packet size in
|
||||||
|
//
|
||||||
|
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
|
||||||
module noc_shell_fft #(
|
module noc_shell_fft #(
|
||||||
parameter [31:0] NOC_ID = 32 'h0,
|
parameter [9:0] THIS_PORTID = 10'd0,
|
||||||
parameter [ 9:0] THIS_PORTID = 10 'd0,
|
parameter CHDR_W = 64,
|
||||||
parameter CHDR_W = 64,
|
parameter [5:0] MTU = 10,
|
||||||
parameter [ 0:0] CTRLPORT_SLV_EN = 1,
|
parameter EN_MAGNITUDE_OUT = 0,
|
||||||
parameter [ 0:0] CTRLPORT_MST_EN = 1,
|
parameter EN_MAGNITUDE_APPROX_OUT = 1,
|
||||||
parameter SYNC_CLKS = 0,
|
parameter EN_MAGNITUDE_SQ_OUT = 1,
|
||||||
parameter [ 5:0] NUM_DATA_I = 1,
|
parameter EN_FFT_SHIFT = 1
|
||||||
parameter [ 5:0] NUM_DATA_O = 1,
|
|
||||||
parameter ITEM_W = 32,
|
|
||||||
parameter NIPC = 2,
|
|
||||||
parameter PYLD_FIFO_SIZE = 5,
|
|
||||||
parameter CTXT_FIFO_SIZE = 5,
|
|
||||||
parameter MTU = 10
|
|
||||||
) (
|
) (
|
||||||
//---------------------------------------------------------------------------
|
//---------------------
|
||||||
// Framework Interface
|
// Framework Interface
|
||||||
//---------------------------------------------------------------------------
|
//---------------------
|
||||||
|
|
||||||
|
// RFNoC Framework Clocks
|
||||||
|
input wire rfnoc_chdr_clk,
|
||||||
|
input wire rfnoc_ctrl_clk,
|
||||||
|
input wire ce_clk,
|
||||||
|
|
||||||
|
// NoC Shell Generated Resets
|
||||||
|
output wire rfnoc_chdr_rst,
|
||||||
|
output wire rfnoc_ctrl_rst,
|
||||||
|
output wire ce_rst,
|
||||||
|
|
||||||
// RFNoC Framework Clocks and Resets
|
|
||||||
input wire rfnoc_chdr_clk,
|
|
||||||
output wire rfnoc_chdr_rst,
|
|
||||||
input wire rfnoc_ctrl_clk,
|
|
||||||
output wire rfnoc_ctrl_rst,
|
|
||||||
// RFNoC Backend Interface
|
// RFNoC Backend Interface
|
||||||
input wire [ 511:0] rfnoc_core_config,
|
input wire [511:0] rfnoc_core_config,
|
||||||
output wire [ 511:0] rfnoc_core_status,
|
output wire [511:0] rfnoc_core_status,
|
||||||
// CHDR Input Ports (from framework)
|
|
||||||
input wire [(CHDR_W*NUM_DATA_I)-1:0] s_rfnoc_chdr_tdata,
|
|
||||||
input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tlast,
|
|
||||||
input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tvalid,
|
|
||||||
output wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tready,
|
|
||||||
// CHDR Output Ports (to framework)
|
|
||||||
output wire [(CHDR_W*NUM_DATA_O)-1:0] m_rfnoc_chdr_tdata,
|
|
||||||
output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tlast,
|
|
||||||
output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tvalid,
|
|
||||||
input wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tready,
|
|
||||||
// AXIS-Ctrl Input Port (from framework)
|
|
||||||
input wire [ 31:0] s_rfnoc_ctrl_tdata,
|
|
||||||
input wire s_rfnoc_ctrl_tlast,
|
|
||||||
input wire s_rfnoc_ctrl_tvalid,
|
|
||||||
output wire s_rfnoc_ctrl_tready,
|
|
||||||
// AXIS-Ctrl Output Port (to framework)
|
|
||||||
output wire [ 31:0] m_rfnoc_ctrl_tdata,
|
|
||||||
output wire m_rfnoc_ctrl_tlast,
|
|
||||||
output wire m_rfnoc_ctrl_tvalid,
|
|
||||||
input wire m_rfnoc_ctrl_tready,
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
// AXIS-CHDR Input Ports (from framework)
|
||||||
// Client Control Port Interface
|
input wire [(1)*CHDR_W-1:0] s_rfnoc_chdr_tdata,
|
||||||
//---------------------------------------------------------------------------
|
input wire [(1)-1:0] s_rfnoc_chdr_tlast,
|
||||||
|
input wire [(1)-1:0] s_rfnoc_chdr_tvalid,
|
||||||
|
output wire [(1)-1:0] s_rfnoc_chdr_tready,
|
||||||
|
// AXIS-CHDR Output Ports (to framework)
|
||||||
|
output wire [(1)*CHDR_W-1:0] m_rfnoc_chdr_tdata,
|
||||||
|
output wire [(1)-1:0] m_rfnoc_chdr_tlast,
|
||||||
|
output wire [(1)-1:0] m_rfnoc_chdr_tvalid,
|
||||||
|
input wire [(1)-1:0] m_rfnoc_chdr_tready,
|
||||||
|
|
||||||
// Clock
|
// AXIS-Ctrl Control Input Port (from framework)
|
||||||
input wire ctrlport_clk,
|
input wire [31:0] s_rfnoc_ctrl_tdata,
|
||||||
input wire ctrlport_rst,
|
input wire s_rfnoc_ctrl_tlast,
|
||||||
// Master
|
input wire s_rfnoc_ctrl_tvalid,
|
||||||
output wire m_ctrlport_req_wr,
|
output wire s_rfnoc_ctrl_tready,
|
||||||
output wire m_ctrlport_req_rd,
|
// AXIS-Ctrl Control Output Port (to framework)
|
||||||
output wire [19:0] m_ctrlport_req_addr,
|
output wire [31:0] m_rfnoc_ctrl_tdata,
|
||||||
output wire [31:0] m_ctrlport_req_data,
|
output wire m_rfnoc_ctrl_tlast,
|
||||||
output wire [ 3:0] m_ctrlport_req_byte_en,
|
output wire m_rfnoc_ctrl_tvalid,
|
||||||
output wire m_ctrlport_req_has_time,
|
input wire m_rfnoc_ctrl_tready,
|
||||||
output wire [63:0] m_ctrlport_req_time,
|
|
||||||
input wire m_ctrlport_resp_ack,
|
|
||||||
input wire [ 1:0] m_ctrlport_resp_status,
|
|
||||||
input wire [31:0] m_ctrlport_resp_data,
|
|
||||||
// Slave
|
|
||||||
input wire s_ctrlport_req_wr,
|
|
||||||
input wire s_ctrlport_req_rd,
|
|
||||||
input wire [19:0] s_ctrlport_req_addr,
|
|
||||||
input wire [ 9:0] s_ctrlport_req_portid,
|
|
||||||
input wire [15:0] s_ctrlport_req_rem_epid,
|
|
||||||
input wire [ 9:0] s_ctrlport_req_rem_portid,
|
|
||||||
input wire [31:0] s_ctrlport_req_data,
|
|
||||||
input wire [ 3:0] s_ctrlport_req_byte_en,
|
|
||||||
input wire s_ctrlport_req_has_time,
|
|
||||||
input wire [63:0] s_ctrlport_req_time,
|
|
||||||
output wire s_ctrlport_resp_ack,
|
|
||||||
output wire [ 1:0] s_ctrlport_resp_status,
|
|
||||||
output wire [31:0] s_ctrlport_resp_data,
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------
|
||||||
// Client Data Interface
|
// Client Interface
|
||||||
//---------------------------------------------------------------------------
|
//---------------------
|
||||||
|
|
||||||
// Clock
|
// CtrlPort Clock and Reset
|
||||||
input wire axis_data_clk,
|
output wire ctrlport_clk,
|
||||||
input wire axis_data_rst,
|
output wire ctrlport_rst,
|
||||||
|
// CtrlPort Master
|
||||||
|
output wire m_ctrlport_req_wr,
|
||||||
|
output wire m_ctrlport_req_rd,
|
||||||
|
output wire [19:0] m_ctrlport_req_addr,
|
||||||
|
output wire [31:0] m_ctrlport_req_data,
|
||||||
|
input wire m_ctrlport_resp_ack,
|
||||||
|
input wire [31:0] m_ctrlport_resp_data,
|
||||||
|
|
||||||
// Output data stream (to user logic)
|
// AXI-Stream Payload Context Clock and Reset
|
||||||
output wire [(NUM_DATA_I*ITEM_W*NIPC)-1:0] m_axis_payload_tdata,
|
output wire axis_data_clk,
|
||||||
output wire [ (NUM_DATA_I*NIPC)-1:0] m_axis_payload_tkeep,
|
output wire axis_data_rst,
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_payload_tlast,
|
// Payload Stream to User Logic: in_0
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_payload_tvalid,
|
output wire [32*1-1:0] m_in_0_payload_tdata,
|
||||||
input wire [ NUM_DATA_I-1:0] m_axis_payload_tready,
|
output wire [1-1:0] m_in_0_payload_tkeep,
|
||||||
|
output wire m_in_0_payload_tlast,
|
||||||
// Input data stream (from user logic)
|
output wire m_in_0_payload_tvalid,
|
||||||
input wire [(NUM_DATA_O*ITEM_W*NIPC)-1:0] s_axis_payload_tdata,
|
input wire m_in_0_payload_tready,
|
||||||
input wire [ (NUM_DATA_O*NIPC)-1:0] s_axis_payload_tkeep,
|
// Context Stream to User Logic: in_0
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_payload_tlast,
|
output wire [CHDR_W-1:0] m_in_0_context_tdata,
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_payload_tvalid,
|
output wire [3:0] m_in_0_context_tuser,
|
||||||
output wire [ NUM_DATA_O-1:0] s_axis_payload_tready,
|
output wire m_in_0_context_tlast,
|
||||||
|
output wire m_in_0_context_tvalid,
|
||||||
// Output context stream (to user logic)
|
input wire m_in_0_context_tready,
|
||||||
output wire [(NUM_DATA_I*CHDR_W)-1:0] m_axis_context_tdata,
|
// Payload Stream from User Logic: out_0
|
||||||
output wire [ (4*NUM_DATA_I)-1:0] m_axis_context_tuser,
|
input wire [32*1-1:0] s_out_0_payload_tdata,
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_context_tlast,
|
input wire [0:0] s_out_0_payload_tkeep,
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_context_tvalid,
|
input wire s_out_0_payload_tlast,
|
||||||
input wire [ NUM_DATA_I-1:0] m_axis_context_tready,
|
input wire s_out_0_payload_tvalid,
|
||||||
|
output wire s_out_0_payload_tready,
|
||||||
// Input context stream (from user logic)
|
// Context Stream from User Logic: out_0
|
||||||
input wire [(NUM_DATA_O*CHDR_W)-1:0] s_axis_context_tdata,
|
input wire [CHDR_W-1:0] s_out_0_context_tdata,
|
||||||
input wire [ (4*NUM_DATA_O)-1:0] s_axis_context_tuser,
|
input wire [3:0] s_out_0_context_tuser,
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_context_tlast,
|
input wire s_out_0_context_tlast,
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_context_tvalid,
|
input wire s_out_0_context_tvalid,
|
||||||
output wire [ NUM_DATA_O-1:0] s_axis_context_tready
|
output wire s_out_0_context_tready
|
||||||
);
|
);
|
||||||
|
|
||||||
localparam CTRL_FIFO_SIZE = 5;
|
|
||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// Backend Interface
|
// Backend Interface
|
||||||
@@ -141,18 +127,18 @@ module noc_shell_fft #(
|
|||||||
wire [63:0] data_o_flush_done;
|
wire [63:0] data_o_flush_done;
|
||||||
|
|
||||||
backend_iface #(
|
backend_iface #(
|
||||||
.NOC_ID (NOC_ID),
|
.NOC_ID (32'hFF700000),
|
||||||
.NUM_DATA_I (NUM_DATA_I),
|
.NUM_DATA_I (1),
|
||||||
.NUM_DATA_O (NUM_DATA_O),
|
.NUM_DATA_O (1),
|
||||||
.CTRL_FIFOSIZE (CTRL_FIFO_SIZE),
|
.CTRL_FIFOSIZE ($clog2(32)),
|
||||||
.MTU (MTU)
|
.MTU (MTU)
|
||||||
) backend_iface_i (
|
) backend_iface_i (
|
||||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
||||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||||
.rfnoc_core_config (rfnoc_core_config),
|
.rfnoc_core_config (rfnoc_core_config),
|
||||||
.rfnoc_core_status (rfnoc_core_status),
|
.rfnoc_core_status (rfnoc_core_status),
|
||||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
|
||||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
|
||||||
.data_i_flush_en (data_i_flush_en),
|
.data_i_flush_en (data_i_flush_en),
|
||||||
.data_i_flush_timeout (data_i_flush_timeout),
|
.data_i_flush_timeout (data_i_flush_timeout),
|
||||||
.data_i_flush_active (data_i_flush_active),
|
.data_i_flush_active (data_i_flush_active),
|
||||||
@@ -163,52 +149,71 @@ module noc_shell_fft #(
|
|||||||
.data_o_flush_done (data_o_flush_done)
|
.data_o_flush_done (data_o_flush_done)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Reset Generation
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
wire ce_rst_pulse;
|
||||||
|
|
||||||
|
pulse_synchronizer #(.MODE ("POSEDGE")) pulse_synchronizer_ce (
|
||||||
|
.clk_a(rfnoc_chdr_clk), .rst_a(1'b0), .pulse_a (rfnoc_chdr_rst), .busy_a (),
|
||||||
|
.clk_b(ce_clk), .pulse_b (ce_rst_pulse)
|
||||||
|
);
|
||||||
|
|
||||||
|
pulse_stretch_min #(.LENGTH(32)) pulse_stretch_min_ce (
|
||||||
|
.clk(ce_clk), .rst(1'b0),
|
||||||
|
.pulse_in(ce_rst_pulse), .pulse_out(ce_rst)
|
||||||
|
);
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// Control Path
|
// Control Path
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
assign ctrlport_clk = ce_clk;
|
||||||
|
assign ctrlport_rst = ce_rst;
|
||||||
|
|
||||||
ctrlport_endpoint #(
|
ctrlport_endpoint #(
|
||||||
.THIS_PORTID (THIS_PORTID ),
|
.THIS_PORTID (THIS_PORTID),
|
||||||
.SYNC_CLKS (0 ),
|
.SYNC_CLKS (0),
|
||||||
.AXIS_CTRL_MST_EN (CTRLPORT_SLV_EN),
|
.AXIS_CTRL_MST_EN (0),
|
||||||
.AXIS_CTRL_SLV_EN (CTRLPORT_MST_EN),
|
.AXIS_CTRL_SLV_EN (1),
|
||||||
.SLAVE_FIFO_SIZE (CTRL_FIFO_SIZE )
|
.SLAVE_FIFO_SIZE ($clog2(32))
|
||||||
) ctrlport_ep_i (
|
) ctrlport_endpoint_i (
|
||||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||||
.ctrlport_clk (ctrlport_clk ),
|
.ctrlport_clk (ctrlport_clk),
|
||||||
.ctrlport_rst (ctrlport_rst ),
|
.ctrlport_rst (ctrlport_rst),
|
||||||
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata ),
|
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
||||||
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast ),
|
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
||||||
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid ),
|
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
||||||
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready ),
|
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
||||||
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata ),
|
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
||||||
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast ),
|
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
||||||
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid ),
|
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
||||||
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready ),
|
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
||||||
.m_ctrlport_req_wr (m_ctrlport_req_wr ),
|
.m_ctrlport_req_wr (m_ctrlport_req_wr),
|
||||||
.m_ctrlport_req_rd (m_ctrlport_req_rd ),
|
.m_ctrlport_req_rd (m_ctrlport_req_rd),
|
||||||
.m_ctrlport_req_addr (m_ctrlport_req_addr ),
|
.m_ctrlport_req_addr (m_ctrlport_req_addr),
|
||||||
.m_ctrlport_req_data (m_ctrlport_req_data ),
|
.m_ctrlport_req_data (m_ctrlport_req_data),
|
||||||
.m_ctrlport_req_byte_en (m_ctrlport_req_byte_en ),
|
.m_ctrlport_req_byte_en (),
|
||||||
.m_ctrlport_req_has_time (m_ctrlport_req_has_time ),
|
.m_ctrlport_req_has_time (),
|
||||||
.m_ctrlport_req_time (m_ctrlport_req_time ),
|
.m_ctrlport_req_time (),
|
||||||
.m_ctrlport_resp_ack (m_ctrlport_resp_ack ),
|
.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
|
||||||
.m_ctrlport_resp_status (m_ctrlport_resp_status ),
|
.m_ctrlport_resp_status (2'b0),
|
||||||
.m_ctrlport_resp_data (m_ctrlport_resp_data ),
|
.m_ctrlport_resp_data (m_ctrlport_resp_data),
|
||||||
.s_ctrlport_req_wr (s_ctrlport_req_wr ),
|
.s_ctrlport_req_wr (1'b0),
|
||||||
.s_ctrlport_req_rd (s_ctrlport_req_rd ),
|
.s_ctrlport_req_rd (1'b0),
|
||||||
.s_ctrlport_req_addr (s_ctrlport_req_addr ),
|
.s_ctrlport_req_addr (20'b0),
|
||||||
.s_ctrlport_req_portid (s_ctrlport_req_portid ),
|
.s_ctrlport_req_portid (10'b0),
|
||||||
.s_ctrlport_req_rem_epid (s_ctrlport_req_rem_epid ),
|
.s_ctrlport_req_rem_epid (16'b0),
|
||||||
.s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
|
.s_ctrlport_req_rem_portid (10'b0),
|
||||||
.s_ctrlport_req_data (s_ctrlport_req_data ),
|
.s_ctrlport_req_data (32'b0),
|
||||||
.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en ),
|
.s_ctrlport_req_byte_en (4'hF),
|
||||||
.s_ctrlport_req_has_time (s_ctrlport_req_has_time ),
|
.s_ctrlport_req_has_time (1'b0),
|
||||||
.s_ctrlport_req_time (s_ctrlport_req_time ),
|
.s_ctrlport_req_time (64'b0),
|
||||||
.s_ctrlport_resp_ack (s_ctrlport_resp_ack ),
|
.s_ctrlport_resp_ack (),
|
||||||
.s_ctrlport_resp_status (s_ctrlport_resp_status ),
|
.s_ctrlport_resp_status (),
|
||||||
.s_ctrlport_resp_data (s_ctrlport_resp_data )
|
.s_ctrlport_resp_data ()
|
||||||
);
|
);
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -216,79 +221,87 @@ module noc_shell_fft #(
|
|||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
genvar i;
|
genvar i;
|
||||||
generate
|
|
||||||
|
|
||||||
for (i = 0; i < NUM_DATA_I; i = i + 1) begin: chdr_to_data
|
assign axis_data_clk = ce_clk;
|
||||||
chdr_to_axis_pyld_ctxt #(
|
assign axis_data_rst = ce_rst;
|
||||||
.CHDR_W (CHDR_W ),
|
|
||||||
.ITEM_W (ITEM_W ),
|
|
||||||
.NIPC (NIPC ),
|
|
||||||
.SYNC_CLKS (SYNC_CLKS ),
|
|
||||||
.CONTEXT_FIFO_SIZE (CTXT_FIFO_SIZE),
|
|
||||||
.PAYLOAD_FIFO_SIZE (PYLD_FIFO_SIZE),
|
|
||||||
.CONTEXT_PREFETCH_EN (1 )
|
|
||||||
) chdr_to_axis_pyld_ctxt_i (
|
|
||||||
.axis_chdr_clk (rfnoc_chdr_clk ),
|
|
||||||
.axis_chdr_rst (rfnoc_chdr_rst ),
|
|
||||||
.axis_data_clk (axis_data_clk ),
|
|
||||||
.axis_data_rst (axis_data_rst ),
|
|
||||||
.s_axis_chdr_tdata (s_rfnoc_chdr_tdata [(i*CHDR_W)+:CHDR_W] ),
|
|
||||||
.s_axis_chdr_tlast (s_rfnoc_chdr_tlast [i] ),
|
|
||||||
.s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid [i] ),
|
|
||||||
.s_axis_chdr_tready (s_rfnoc_chdr_tready [i] ),
|
|
||||||
.m_axis_payload_tdata (m_axis_payload_tdata [(i*ITEM_W*NIPC)+:(ITEM_W*NIPC)]),
|
|
||||||
.m_axis_payload_tkeep (m_axis_payload_tkeep [(i*NIPC)+:NIPC] ),
|
|
||||||
.m_axis_payload_tlast (m_axis_payload_tlast [i] ),
|
|
||||||
.m_axis_payload_tvalid(m_axis_payload_tvalid[i] ),
|
|
||||||
.m_axis_payload_tready(m_axis_payload_tready[i] ),
|
|
||||||
.m_axis_context_tdata (m_axis_context_tdata [(i*CHDR_W)+:(CHDR_W)] ),
|
|
||||||
.m_axis_context_tuser (m_axis_context_tuser [(i*4)+:4] ),
|
|
||||||
.m_axis_context_tlast (m_axis_context_tlast [i] ),
|
|
||||||
.m_axis_context_tvalid(m_axis_context_tvalid[i] ),
|
|
||||||
.m_axis_context_tready(m_axis_context_tready[i] ),
|
|
||||||
.flush_en (data_i_flush_en ),
|
|
||||||
.flush_timeout (data_i_flush_timeout ),
|
|
||||||
.flush_active (data_i_flush_active [i] ),
|
|
||||||
.flush_done (data_i_flush_done [i] )
|
|
||||||
);
|
|
||||||
end
|
|
||||||
|
|
||||||
for (i = 0; i < NUM_DATA_O; i = i + 1) begin: data_to_chdr
|
//---------------------
|
||||||
axis_pyld_ctxt_to_chdr #(
|
// Input Data Paths
|
||||||
.CHDR_W (CHDR_W ),
|
//---------------------
|
||||||
.ITEM_W (ITEM_W ),
|
|
||||||
.NIPC (NIPC ),
|
|
||||||
.SYNC_CLKS (SYNC_CLKS ),
|
|
||||||
.CONTEXT_FIFO_SIZE (CTXT_FIFO_SIZE),
|
|
||||||
.PAYLOAD_FIFO_SIZE (PYLD_FIFO_SIZE),
|
|
||||||
.CONTEXT_PREFETCH_EN (1 ),
|
|
||||||
.MTU (MTU )
|
|
||||||
) axis_pyld_ctxt_to_chdr_i (
|
|
||||||
.axis_chdr_clk (rfnoc_chdr_clk ),
|
|
||||||
.axis_chdr_rst (rfnoc_chdr_rst ),
|
|
||||||
.axis_data_clk (axis_data_clk ),
|
|
||||||
.axis_data_rst (axis_data_rst ),
|
|
||||||
.m_axis_chdr_tdata (m_rfnoc_chdr_tdata [(i*CHDR_W)+:CHDR_W] ),
|
|
||||||
.m_axis_chdr_tlast (m_rfnoc_chdr_tlast [i] ),
|
|
||||||
.m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid [i] ),
|
|
||||||
.m_axis_chdr_tready (m_rfnoc_chdr_tready [i] ),
|
|
||||||
.s_axis_payload_tdata (s_axis_payload_tdata [(i*ITEM_W*NIPC)+:(ITEM_W*NIPC)]),
|
|
||||||
.s_axis_payload_tkeep (s_axis_payload_tkeep [(i*NIPC)+:NIPC] ),
|
|
||||||
.s_axis_payload_tlast (s_axis_payload_tlast [i] ),
|
|
||||||
.s_axis_payload_tvalid(s_axis_payload_tvalid[i] ),
|
|
||||||
.s_axis_payload_tready(s_axis_payload_tready[i] ),
|
|
||||||
.s_axis_context_tdata (s_axis_context_tdata [(i*CHDR_W)+:(CHDR_W)] ),
|
|
||||||
.s_axis_context_tuser (s_axis_context_tuser [(i*4)+:4] ),
|
|
||||||
.s_axis_context_tlast (s_axis_context_tlast [i] ),
|
|
||||||
.s_axis_context_tvalid(s_axis_context_tvalid[i] ),
|
|
||||||
.s_axis_context_tready(s_axis_context_tready[i] ),
|
|
||||||
.framer_errors ( ),
|
|
||||||
.flush_en (data_o_flush_en ),
|
|
||||||
.flush_timeout (data_o_flush_timeout ),
|
|
||||||
.flush_active (data_o_flush_active [i] ),
|
|
||||||
.flush_done (data_o_flush_done [i] )
|
|
||||||
);
|
|
||||||
end
|
|
||||||
endgenerate
|
|
||||||
|
|
||||||
endmodule
|
chdr_to_axis_pyld_ctxt #(
|
||||||
|
.CHDR_W (CHDR_W),
|
||||||
|
.ITEM_W (32),
|
||||||
|
.NIPC (1),
|
||||||
|
.SYNC_CLKS (0),
|
||||||
|
.CONTEXT_FIFO_SIZE ($clog2(2)),
|
||||||
|
.PAYLOAD_FIFO_SIZE ($clog2(32)),
|
||||||
|
.CONTEXT_PREFETCH_EN (1)
|
||||||
|
) chdr_to_axis_pyld_ctxt_in_in_0 (
|
||||||
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
|
.axis_data_clk (axis_data_clk),
|
||||||
|
.axis_data_rst (axis_data_rst),
|
||||||
|
.s_axis_chdr_tdata (s_rfnoc_chdr_tdata[(0)*CHDR_W+:CHDR_W]),
|
||||||
|
.s_axis_chdr_tlast (s_rfnoc_chdr_tlast[0]),
|
||||||
|
.s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[0]),
|
||||||
|
.s_axis_chdr_tready (s_rfnoc_chdr_tready[0]),
|
||||||
|
.m_axis_payload_tdata (m_in_0_payload_tdata),
|
||||||
|
.m_axis_payload_tkeep (m_in_0_payload_tkeep),
|
||||||
|
.m_axis_payload_tlast (m_in_0_payload_tlast),
|
||||||
|
.m_axis_payload_tvalid (m_in_0_payload_tvalid),
|
||||||
|
.m_axis_payload_tready (m_in_0_payload_tready),
|
||||||
|
.m_axis_context_tdata (m_in_0_context_tdata),
|
||||||
|
.m_axis_context_tuser (m_in_0_context_tuser),
|
||||||
|
.m_axis_context_tlast (m_in_0_context_tlast),
|
||||||
|
.m_axis_context_tvalid (m_in_0_context_tvalid),
|
||||||
|
.m_axis_context_tready (m_in_0_context_tready),
|
||||||
|
.flush_en (data_i_flush_en),
|
||||||
|
.flush_timeout (data_i_flush_timeout),
|
||||||
|
.flush_active (data_i_flush_active[0]),
|
||||||
|
.flush_done (data_i_flush_done[0])
|
||||||
|
);
|
||||||
|
|
||||||
|
//---------------------
|
||||||
|
// Output Data Paths
|
||||||
|
//---------------------
|
||||||
|
|
||||||
|
axis_pyld_ctxt_to_chdr #(
|
||||||
|
.CHDR_W (CHDR_W),
|
||||||
|
.ITEM_W (32),
|
||||||
|
.NIPC (1),
|
||||||
|
.SYNC_CLKS (0),
|
||||||
|
.CONTEXT_FIFO_SIZE ($clog2(2)),
|
||||||
|
.PAYLOAD_FIFO_SIZE ($clog2(32)),
|
||||||
|
.MTU (MTU),
|
||||||
|
.CONTEXT_PREFETCH_EN (1)
|
||||||
|
) axis_pyld_ctxt_to_chdr_out_out_0 (
|
||||||
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
|
.axis_data_clk (axis_data_clk),
|
||||||
|
.axis_data_rst (axis_data_rst),
|
||||||
|
.m_axis_chdr_tdata (m_rfnoc_chdr_tdata[(0)*CHDR_W+:CHDR_W]),
|
||||||
|
.m_axis_chdr_tlast (m_rfnoc_chdr_tlast[0]),
|
||||||
|
.m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[0]),
|
||||||
|
.m_axis_chdr_tready (m_rfnoc_chdr_tready[0]),
|
||||||
|
.s_axis_payload_tdata (s_out_0_payload_tdata),
|
||||||
|
.s_axis_payload_tkeep (s_out_0_payload_tkeep),
|
||||||
|
.s_axis_payload_tlast (s_out_0_payload_tlast),
|
||||||
|
.s_axis_payload_tvalid (s_out_0_payload_tvalid),
|
||||||
|
.s_axis_payload_tready (s_out_0_payload_tready),
|
||||||
|
.s_axis_context_tdata (s_out_0_context_tdata),
|
||||||
|
.s_axis_context_tuser (s_out_0_context_tuser),
|
||||||
|
.s_axis_context_tlast (s_out_0_context_tlast),
|
||||||
|
.s_axis_context_tvalid (s_out_0_context_tvalid),
|
||||||
|
.s_axis_context_tready (s_out_0_context_tready),
|
||||||
|
.framer_errors (),
|
||||||
|
.flush_en (data_o_flush_en),
|
||||||
|
.flush_timeout (data_o_flush_timeout),
|
||||||
|
.flush_active (data_o_flush_active[0]),
|
||||||
|
.flush_done (data_o_flush_done[0])
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule // noc_shell_fft
|
||||||
|
|
||||||
|
|
||||||
|
`default_nettype wire
|
||||||
|
|||||||
@@ -76,22 +76,16 @@ module rfnoc_block_fft #(
|
|||||||
localparam ITEM_W = 32;
|
localparam ITEM_W = 32;
|
||||||
localparam NIPC = 1;
|
localparam NIPC = 1;
|
||||||
|
|
||||||
localparam NOC_ID = 32'hFF70_0000;
|
|
||||||
|
|
||||||
`include "../../core/rfnoc_axis_ctrl_utils.vh"
|
`include "../../core/rfnoc_axis_ctrl_utils.vh"
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// Signal Declarations
|
// Signal Declarations
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
wire rfnoc_chdr_rst;
|
|
||||||
|
|
||||||
wire ctrlport_req_wr;
|
wire ctrlport_req_wr;
|
||||||
wire ctrlport_req_rd;
|
wire ctrlport_req_rd;
|
||||||
wire [19:0] ctrlport_req_addr;
|
wire [19:0] ctrlport_req_addr;
|
||||||
wire [31:0] ctrlport_req_data;
|
wire [31:0] ctrlport_req_data;
|
||||||
wire ctrlport_req_has_time;
|
|
||||||
wire [63:0] ctrlport_req_time;
|
|
||||||
wire ctrlport_resp_ack;
|
wire ctrlport_resp_ack;
|
||||||
wire [31:0] ctrlport_resp_data;
|
wire [31:0] ctrlport_resp_data;
|
||||||
|
|
||||||
@@ -119,106 +113,70 @@ module rfnoc_block_fft #(
|
|||||||
|
|
||||||
wire ce_rst;
|
wire ce_rst;
|
||||||
|
|
||||||
// Cross the CHDR reset to the radio_clk domain
|
|
||||||
pulse_synchronizer #(
|
|
||||||
.MODE ("POSEDGE")
|
|
||||||
) ctrl_rst_sync_i (
|
|
||||||
.clk_a (rfnoc_chdr_clk),
|
|
||||||
.rst_a (1'b0),
|
|
||||||
.pulse_a (rfnoc_chdr_rst),
|
|
||||||
.busy_a (),
|
|
||||||
.clk_b (ce_clk),
|
|
||||||
.pulse_b (ce_rst)
|
|
||||||
);
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// NoC Shell
|
// NoC Shell
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
noc_shell_fft #(
|
noc_shell_fft #(
|
||||||
.NOC_ID (NOC_ID ),
|
.THIS_PORTID (THIS_PORTID),
|
||||||
.THIS_PORTID (THIS_PORTID),
|
.CHDR_W (CHDR_W ),
|
||||||
.CHDR_W (CHDR_W ),
|
.MTU (MTU )
|
||||||
.CTRLPORT_SLV_EN(0 ),
|
|
||||||
.CTRLPORT_MST_EN(1 ),
|
|
||||||
.SYNC_CLKS (0 ),
|
|
||||||
.NUM_DATA_I (1 ),
|
|
||||||
.NUM_DATA_O (1 ),
|
|
||||||
.ITEM_W (ITEM_W ),
|
|
||||||
.NIPC (NIPC ),
|
|
||||||
.PYLD_FIFO_SIZE (MTU ),
|
|
||||||
.CTXT_FIFO_SIZE (1 ),
|
|
||||||
.MTU (MTU )
|
|
||||||
) noc_shell_fft_i (
|
) noc_shell_fft_i (
|
||||||
.rfnoc_chdr_clk (rfnoc_chdr_clk ),
|
.rfnoc_chdr_clk (rfnoc_chdr_clk ),
|
||||||
.rfnoc_chdr_rst (rfnoc_chdr_rst ),
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
|
||||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
|
.ce_clk (ce_clk ),
|
||||||
.rfnoc_ctrl_rst ( ),
|
.rfnoc_chdr_rst ( ),
|
||||||
.rfnoc_core_config (rfnoc_core_config ),
|
.rfnoc_ctrl_rst ( ),
|
||||||
.rfnoc_core_status (rfnoc_core_status ),
|
.ce_rst (ce_rst ),
|
||||||
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata ),
|
.rfnoc_core_config (rfnoc_core_config ),
|
||||||
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast ),
|
.rfnoc_core_status (rfnoc_core_status ),
|
||||||
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid ),
|
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata ),
|
||||||
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready ),
|
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast ),
|
||||||
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata ),
|
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid ),
|
||||||
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast ),
|
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready ),
|
||||||
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid ),
|
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata ),
|
||||||
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready ),
|
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast ),
|
||||||
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata ),
|
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid ),
|
||||||
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast ),
|
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready ),
|
||||||
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid ),
|
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata ),
|
||||||
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready ),
|
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast ),
|
||||||
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata ),
|
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid ),
|
||||||
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast ),
|
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready ),
|
||||||
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid ),
|
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata ),
|
||||||
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready ),
|
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast ),
|
||||||
.ctrlport_clk (ce_clk ),
|
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid ),
|
||||||
.ctrlport_rst (ce_rst ),
|
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready ),
|
||||||
.m_ctrlport_req_wr (ctrlport_req_wr ),
|
.ctrlport_clk ( ),
|
||||||
.m_ctrlport_req_rd (ctrlport_req_rd ),
|
.ctrlport_rst ( ),
|
||||||
.m_ctrlport_req_addr (ctrlport_req_addr ),
|
.m_ctrlport_req_wr (ctrlport_req_wr ),
|
||||||
.m_ctrlport_req_data (ctrlport_req_data ),
|
.m_ctrlport_req_rd (ctrlport_req_rd ),
|
||||||
.m_ctrlport_req_byte_en ( ),
|
.m_ctrlport_req_addr (ctrlport_req_addr ),
|
||||||
.m_ctrlport_req_has_time (ctrlport_req_has_time),
|
.m_ctrlport_req_data (ctrlport_req_data ),
|
||||||
.m_ctrlport_req_time (ctrlport_req_time ),
|
.m_ctrlport_resp_ack (ctrlport_resp_ack ),
|
||||||
.m_ctrlport_resp_ack (ctrlport_resp_ack ),
|
.m_ctrlport_resp_data (ctrlport_resp_data ),
|
||||||
.m_ctrlport_resp_status (AXIS_CTRL_STS_OKAY ),
|
.axis_data_clk ( ),
|
||||||
.m_ctrlport_resp_data (ctrlport_resp_data ),
|
.axis_data_rst ( ),
|
||||||
.s_ctrlport_req_wr (1'b0 ),
|
.m_in_0_payload_tdata (axis_to_fft_tdata ),
|
||||||
.s_ctrlport_req_rd (1'b0 ),
|
.m_in_0_payload_tkeep ( ),
|
||||||
.s_ctrlport_req_addr (20'b0 ),
|
.m_in_0_payload_tlast (axis_to_fft_tlast ),
|
||||||
.s_ctrlport_req_portid (10'b0 ),
|
.m_in_0_payload_tvalid (axis_to_fft_tvalid ),
|
||||||
.s_ctrlport_req_rem_epid (16'b0 ),
|
.m_in_0_payload_tready (axis_to_fft_tready ),
|
||||||
.s_ctrlport_req_rem_portid(10'b0 ),
|
.m_in_0_context_tdata (m_axis_context_tdata ),
|
||||||
.s_ctrlport_req_data (32'b0 ),
|
.m_in_0_context_tuser (m_axis_context_tuser ),
|
||||||
.s_ctrlport_req_byte_en (4'b0 ),
|
.m_in_0_context_tlast (m_axis_context_tlast ),
|
||||||
.s_ctrlport_req_has_time (1'b0 ),
|
.m_in_0_context_tvalid (m_axis_context_tvalid),
|
||||||
.s_ctrlport_req_time (64'b0 ),
|
.m_in_0_context_tready (m_axis_context_tready),
|
||||||
.s_ctrlport_resp_ack ( ),
|
.s_out_0_payload_tdata (axis_from_fft_tdata ),
|
||||||
.s_ctrlport_resp_status ( ),
|
.s_out_0_payload_tkeep ({1*NIPC{1'b1}} ),
|
||||||
.s_ctrlport_resp_data ( ),
|
.s_out_0_payload_tlast (axis_from_fft_tlast ),
|
||||||
.axis_data_clk (ce_clk ),
|
.s_out_0_payload_tvalid (axis_from_fft_tvalid ),
|
||||||
.axis_data_rst (ce_rst ),
|
.s_out_0_payload_tready (axis_from_fft_tready ),
|
||||||
.m_axis_payload_tdata (axis_to_fft_tdata ),
|
.s_out_0_context_tdata (s_axis_context_tdata ),
|
||||||
.m_axis_payload_tkeep ( ),
|
.s_out_0_context_tuser (s_axis_context_tuser ),
|
||||||
.m_axis_payload_tlast (axis_to_fft_tlast ),
|
.s_out_0_context_tlast (s_axis_context_tlast ),
|
||||||
.m_axis_payload_tvalid (axis_to_fft_tvalid ),
|
.s_out_0_context_tvalid (s_axis_context_tvalid),
|
||||||
.m_axis_payload_tready (axis_to_fft_tready ),
|
.s_out_0_context_tready (s_axis_context_tready)
|
||||||
.s_axis_payload_tdata (axis_from_fft_tdata ),
|
|
||||||
.s_axis_payload_tkeep ({1*NIPC{1'b1}} ),
|
|
||||||
.s_axis_payload_tlast (axis_from_fft_tlast ),
|
|
||||||
.s_axis_payload_tvalid (axis_from_fft_tvalid ),
|
|
||||||
.s_axis_payload_tready (axis_from_fft_tready ),
|
|
||||||
.m_axis_context_tdata (m_axis_context_tdata ),
|
|
||||||
.m_axis_context_tuser (m_axis_context_tuser ),
|
|
||||||
.m_axis_context_tlast (m_axis_context_tlast ),
|
|
||||||
.m_axis_context_tvalid (m_axis_context_tvalid),
|
|
||||||
.m_axis_context_tready (m_axis_context_tready),
|
|
||||||
.s_axis_context_tdata (s_axis_context_tdata ),
|
|
||||||
.s_axis_context_tuser (s_axis_context_tuser ),
|
|
||||||
.s_axis_context_tlast (s_axis_context_tlast ),
|
|
||||||
.s_axis_context_tvalid (s_axis_context_tvalid),
|
|
||||||
.s_axis_context_tready (s_axis_context_tready)
|
|
||||||
);
|
);
|
||||||
|
|
||||||
// The input packets are the same configuration as the output packets, so
|
// The input packets are the same configuration as the output packets, so
|
||||||
@@ -233,7 +191,6 @@ module rfnoc_block_fft #(
|
|||||||
|
|
||||||
wire [ 8-1:0] set_addr;
|
wire [ 8-1:0] set_addr;
|
||||||
wire [32-1:0] set_data;
|
wire [32-1:0] set_data;
|
||||||
wire set_has_time;
|
|
||||||
wire set_stb;
|
wire set_stb;
|
||||||
wire [ 8-1:0] rb_addr;
|
wire [ 8-1:0] rb_addr;
|
||||||
reg [64-1:0] rb_data;
|
reg [64-1:0] rb_data;
|
||||||
@@ -247,15 +204,15 @@ module rfnoc_block_fft #(
|
|||||||
.s_ctrlport_req_rd (ctrlport_req_rd),
|
.s_ctrlport_req_rd (ctrlport_req_rd),
|
||||||
.s_ctrlport_req_addr (ctrlport_req_addr),
|
.s_ctrlport_req_addr (ctrlport_req_addr),
|
||||||
.s_ctrlport_req_data (ctrlport_req_data),
|
.s_ctrlport_req_data (ctrlport_req_data),
|
||||||
.s_ctrlport_req_has_time (ctrlport_req_has_time),
|
.s_ctrlport_req_has_time (1'b0),
|
||||||
.s_ctrlport_req_time (ctrlport_req_time),
|
.s_ctrlport_req_time (64'b0),
|
||||||
.s_ctrlport_resp_ack (ctrlport_resp_ack),
|
.s_ctrlport_resp_ack (ctrlport_resp_ack),
|
||||||
.s_ctrlport_resp_data (ctrlport_resp_data),
|
.s_ctrlport_resp_data (ctrlport_resp_data),
|
||||||
.set_data (set_data),
|
.set_data (set_data),
|
||||||
.set_addr (set_addr),
|
.set_addr (set_addr),
|
||||||
.set_stb (set_stb),
|
.set_stb (set_stb),
|
||||||
.set_time (),
|
.set_time (),
|
||||||
.set_has_time (set_has_time),
|
.set_has_time (),
|
||||||
.rb_stb (1'b1),
|
.rb_stb (1'b1),
|
||||||
.rb_addr (rb_addr),
|
.rb_addr (rb_addr),
|
||||||
.rb_data (rb_data));
|
.rb_data (rb_data));
|
||||||
|
|||||||
@@ -28,6 +28,7 @@ module rfnoc_block_fft_tb();
|
|||||||
localparam int STALL_PROB = 25; // BFM stall probability
|
localparam int STALL_PROB = 25; // BFM stall probability
|
||||||
|
|
||||||
// Block configuration
|
// Block configuration
|
||||||
|
localparam int NOC_ID = 32'hFF70_0000;
|
||||||
localparam int CHDR_W = 64;
|
localparam int CHDR_W = 64;
|
||||||
localparam int THIS_PORTID = 'h123;
|
localparam int THIS_PORTID = 'h123;
|
||||||
localparam int MTU = 10;
|
localparam int MTU = 10;
|
||||||
@@ -222,7 +223,7 @@ module rfnoc_block_fft_tb();
|
|||||||
//-------------------------------------------------------------------------
|
//-------------------------------------------------------------------------
|
||||||
|
|
||||||
test.start_test("Verify Block Info", 2us);
|
test.start_test("Verify Block Info", 2us);
|
||||||
`ASSERT_ERROR(blk_ctrl.get_noc_id() == DUT.NOC_ID, "Incorrect NOC_ID Value");
|
`ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I Value");
|
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O Value");
|
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
|
`ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
|
||||||
|
|||||||
@@ -1,134 +1,121 @@
|
|||||||
//
|
//
|
||||||
// Copyright 2019 Ettus Research, A National Instruments Company
|
// Copyright 2019 Ettus Research, A National Instruments Brand
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||||
//
|
//
|
||||||
// Module: noc_shell_fir_filter
|
// Module: noc_shell_fir_filter
|
||||||
//
|
//
|
||||||
// Description: A NoC Shell for RFNoC. This should eventually be replaced
|
// Description:
|
||||||
// by an auto-generated NoC Shell.
|
//
|
||||||
|
// This is a tool-generated NoC-shell for the fir_filter block.
|
||||||
|
// See the RFNoC specification for more information about NoC shells.
|
||||||
|
//
|
||||||
|
// Parameters:
|
||||||
|
//
|
||||||
|
// THIS_PORTID : Control crossbar port to which this block is connected
|
||||||
|
// CHDR_W : AXIS-CHDR data bus width
|
||||||
|
// MTU : Maximum transmission unit (i.e., maximum packet size in
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
|
||||||
module noc_shell_fir_filter #(
|
module noc_shell_fir_filter #(
|
||||||
parameter [31:0] NOC_ID = 32 'h0,
|
parameter [9:0] THIS_PORTID = 10'd0,
|
||||||
parameter [ 9:0] THIS_PORTID = 10 'd0,
|
parameter CHDR_W = 64,
|
||||||
parameter CHDR_W = 64,
|
parameter [5:0] MTU = 10,
|
||||||
parameter [ 0:0] CTRLPORT_SLV_EN = 1,
|
parameter NUM_PORTS = 1,
|
||||||
parameter [ 0:0] CTRLPORT_MST_EN = 1,
|
parameter COEFF_WIDTH = 16,
|
||||||
parameter SYNC_CLKS = 0,
|
parameter NUM_COEFFS = 41,
|
||||||
parameter [ 5:0] NUM_DATA_I = 1,
|
parameter COEFFS_VEC = { 16'h7FFF, {640{1'b0}} },
|
||||||
parameter [ 5:0] NUM_DATA_O = 1,
|
parameter RELOADABLE_COEFFS = 1,
|
||||||
parameter ITEM_W = 32,
|
parameter SYMMETRIC_COEFFS = 0,
|
||||||
parameter NIPC = 2,
|
parameter SKIP_ZERO_COEFFS = 0,
|
||||||
parameter PYLD_FIFO_SIZE = 5,
|
parameter USE_EMBEDDED_REGS_COEFFS = 1
|
||||||
parameter CTXT_FIFO_SIZE = 5,
|
|
||||||
parameter MTU = 10
|
|
||||||
) (
|
) (
|
||||||
//---------------------------------------------------------------------------
|
//---------------------
|
||||||
// Framework Interface
|
// Framework Interface
|
||||||
//---------------------------------------------------------------------------
|
//---------------------
|
||||||
|
|
||||||
|
// RFNoC Framework Clocks
|
||||||
|
input wire rfnoc_chdr_clk,
|
||||||
|
input wire rfnoc_ctrl_clk,
|
||||||
|
input wire ce_clk,
|
||||||
|
|
||||||
|
// NoC Shell Generated Resets
|
||||||
|
output wire rfnoc_chdr_rst,
|
||||||
|
output wire rfnoc_ctrl_rst,
|
||||||
|
output wire ce_rst,
|
||||||
|
|
||||||
// RFNoC Framework Clocks and Resets
|
|
||||||
input wire rfnoc_chdr_clk,
|
|
||||||
output wire rfnoc_chdr_rst,
|
|
||||||
input wire rfnoc_ctrl_clk,
|
|
||||||
output wire rfnoc_ctrl_rst,
|
|
||||||
// RFNoC Backend Interface
|
// RFNoC Backend Interface
|
||||||
input wire [ 511:0] rfnoc_core_config,
|
input wire [511:0] rfnoc_core_config,
|
||||||
output wire [ 511:0] rfnoc_core_status,
|
output wire [511:0] rfnoc_core_status,
|
||||||
// CHDR Input Ports (from framework)
|
|
||||||
input wire [(CHDR_W*NUM_DATA_I)-1:0] s_rfnoc_chdr_tdata,
|
|
||||||
input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tlast,
|
|
||||||
input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tvalid,
|
|
||||||
output wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tready,
|
|
||||||
// CHDR Output Ports (to framework)
|
|
||||||
output wire [(CHDR_W*NUM_DATA_O)-1:0] m_rfnoc_chdr_tdata,
|
|
||||||
output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tlast,
|
|
||||||
output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tvalid,
|
|
||||||
input wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tready,
|
|
||||||
// AXIS-Ctrl Input Port (from framework)
|
|
||||||
input wire [ 31:0] s_rfnoc_ctrl_tdata,
|
|
||||||
input wire s_rfnoc_ctrl_tlast,
|
|
||||||
input wire s_rfnoc_ctrl_tvalid,
|
|
||||||
output wire s_rfnoc_ctrl_tready,
|
|
||||||
// AXIS-Ctrl Output Port (to framework)
|
|
||||||
output wire [ 31:0] m_rfnoc_ctrl_tdata,
|
|
||||||
output wire m_rfnoc_ctrl_tlast,
|
|
||||||
output wire m_rfnoc_ctrl_tvalid,
|
|
||||||
input wire m_rfnoc_ctrl_tready,
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
// AXIS-CHDR Input Ports (from framework)
|
||||||
// Client Control Port Interface
|
input wire [(0+NUM_PORTS)*CHDR_W-1:0] s_rfnoc_chdr_tdata,
|
||||||
//---------------------------------------------------------------------------
|
input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tlast,
|
||||||
|
input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tvalid,
|
||||||
|
output wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tready,
|
||||||
|
// AXIS-CHDR Output Ports (to framework)
|
||||||
|
output wire [(0+NUM_PORTS)*CHDR_W-1:0] m_rfnoc_chdr_tdata,
|
||||||
|
output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tlast,
|
||||||
|
output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tvalid,
|
||||||
|
input wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tready,
|
||||||
|
|
||||||
// Clock
|
// AXIS-Ctrl Control Input Port (from framework)
|
||||||
input wire ctrlport_clk,
|
input wire [31:0] s_rfnoc_ctrl_tdata,
|
||||||
input wire ctrlport_rst,
|
input wire s_rfnoc_ctrl_tlast,
|
||||||
// Master
|
input wire s_rfnoc_ctrl_tvalid,
|
||||||
output wire m_ctrlport_req_wr,
|
output wire s_rfnoc_ctrl_tready,
|
||||||
output wire m_ctrlport_req_rd,
|
// AXIS-Ctrl Control Output Port (to framework)
|
||||||
output wire [19:0] m_ctrlport_req_addr,
|
output wire [31:0] m_rfnoc_ctrl_tdata,
|
||||||
output wire [31:0] m_ctrlport_req_data,
|
output wire m_rfnoc_ctrl_tlast,
|
||||||
output wire [ 3:0] m_ctrlport_req_byte_en,
|
output wire m_rfnoc_ctrl_tvalid,
|
||||||
output wire m_ctrlport_req_has_time,
|
input wire m_rfnoc_ctrl_tready,
|
||||||
output wire [63:0] m_ctrlport_req_time,
|
|
||||||
input wire m_ctrlport_resp_ack,
|
|
||||||
input wire [ 1:0] m_ctrlport_resp_status,
|
|
||||||
input wire [31:0] m_ctrlport_resp_data,
|
|
||||||
// Slave
|
|
||||||
input wire s_ctrlport_req_wr,
|
|
||||||
input wire s_ctrlport_req_rd,
|
|
||||||
input wire [19:0] s_ctrlport_req_addr,
|
|
||||||
input wire [ 9:0] s_ctrlport_req_portid,
|
|
||||||
input wire [15:0] s_ctrlport_req_rem_epid,
|
|
||||||
input wire [ 9:0] s_ctrlport_req_rem_portid,
|
|
||||||
input wire [31:0] s_ctrlport_req_data,
|
|
||||||
input wire [ 3:0] s_ctrlport_req_byte_en,
|
|
||||||
input wire s_ctrlport_req_has_time,
|
|
||||||
input wire [63:0] s_ctrlport_req_time,
|
|
||||||
output wire s_ctrlport_resp_ack,
|
|
||||||
output wire [ 1:0] s_ctrlport_resp_status,
|
|
||||||
output wire [31:0] s_ctrlport_resp_data,
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------
|
||||||
// Client Data Interface
|
// Client Interface
|
||||||
//---------------------------------------------------------------------------
|
//---------------------
|
||||||
|
|
||||||
// Clock
|
// CtrlPort Clock and Reset
|
||||||
input wire axis_data_clk,
|
output wire ctrlport_clk,
|
||||||
input wire axis_data_rst,
|
output wire ctrlport_rst,
|
||||||
|
// CtrlPort Master
|
||||||
|
output wire m_ctrlport_req_wr,
|
||||||
|
output wire m_ctrlport_req_rd,
|
||||||
|
output wire [19:0] m_ctrlport_req_addr,
|
||||||
|
output wire [31:0] m_ctrlport_req_data,
|
||||||
|
input wire m_ctrlport_resp_ack,
|
||||||
|
input wire [31:0] m_ctrlport_resp_data,
|
||||||
|
|
||||||
// Output data stream (to user logic)
|
// AXI-Stream Payload Context Clock and Reset
|
||||||
output wire [(NUM_DATA_I*ITEM_W*NIPC)-1:0] m_axis_payload_tdata,
|
output wire axis_data_clk,
|
||||||
output wire [ (NUM_DATA_I*NIPC)-1:0] m_axis_payload_tkeep,
|
output wire axis_data_rst,
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_payload_tlast,
|
// Payload Stream to User Logic: in
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_payload_tvalid,
|
output wire [NUM_PORTS*32*1-1:0] m_in_payload_tdata,
|
||||||
input wire [ NUM_DATA_I-1:0] m_axis_payload_tready,
|
output wire [NUM_PORTS*1-1:0] m_in_payload_tkeep,
|
||||||
|
output wire [NUM_PORTS-1:0] m_in_payload_tlast,
|
||||||
// Input data stream (from user logic)
|
output wire [NUM_PORTS-1:0] m_in_payload_tvalid,
|
||||||
input wire [(NUM_DATA_O*ITEM_W*NIPC)-1:0] s_axis_payload_tdata,
|
input wire [NUM_PORTS-1:0] m_in_payload_tready,
|
||||||
input wire [ (NUM_DATA_O*NIPC)-1:0] s_axis_payload_tkeep,
|
// Context Stream to User Logic: in
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_payload_tlast,
|
output wire [NUM_PORTS*CHDR_W-1:0] m_in_context_tdata,
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_payload_tvalid,
|
output wire [NUM_PORTS*4-1:0] m_in_context_tuser,
|
||||||
output wire [ NUM_DATA_O-1:0] s_axis_payload_tready,
|
output wire [NUM_PORTS-1:0] m_in_context_tlast,
|
||||||
|
output wire [NUM_PORTS-1:0] m_in_context_tvalid,
|
||||||
// Output context stream (to user logic)
|
input wire [NUM_PORTS-1:0] m_in_context_tready,
|
||||||
output wire [(NUM_DATA_I*CHDR_W)-1:0] m_axis_context_tdata,
|
// Payload Stream to User Logic: out
|
||||||
output wire [ (4*NUM_DATA_I)-1:0] m_axis_context_tuser,
|
input wire [NUM_PORTS*32*1-1:0] s_out_payload_tdata,
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_context_tlast,
|
input wire [NUM_PORTS*1-1:0] s_out_payload_tkeep,
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_context_tvalid,
|
input wire [NUM_PORTS-1:0] s_out_payload_tlast,
|
||||||
input wire [ NUM_DATA_I-1:0] m_axis_context_tready,
|
input wire [NUM_PORTS-1:0] s_out_payload_tvalid,
|
||||||
|
output wire [NUM_PORTS-1:0] s_out_payload_tready,
|
||||||
// Input context stream (from user logic)
|
// Context Stream to User Logic: out
|
||||||
input wire [(NUM_DATA_O*CHDR_W)-1:0] s_axis_context_tdata,
|
input wire [NUM_PORTS*CHDR_W-1:0] s_out_context_tdata,
|
||||||
input wire [ (4*NUM_DATA_O)-1:0] s_axis_context_tuser,
|
input wire [NUM_PORTS*4-1:0] s_out_context_tuser,
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_context_tlast,
|
input wire [NUM_PORTS-1:0] s_out_context_tlast,
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_context_tvalid,
|
input wire [NUM_PORTS-1:0] s_out_context_tvalid,
|
||||||
output wire [ NUM_DATA_O-1:0] s_axis_context_tready
|
output wire [NUM_PORTS-1:0] s_out_context_tready
|
||||||
);
|
);
|
||||||
|
|
||||||
localparam CTRL_FIFO_SIZE = 5;
|
|
||||||
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// Backend Interface
|
// Backend Interface
|
||||||
@@ -144,18 +131,18 @@ module noc_shell_fir_filter #(
|
|||||||
wire [63:0] data_o_flush_done;
|
wire [63:0] data_o_flush_done;
|
||||||
|
|
||||||
backend_iface #(
|
backend_iface #(
|
||||||
.NOC_ID (NOC_ID),
|
.NOC_ID (32'hF1120000),
|
||||||
.NUM_DATA_I (NUM_DATA_I),
|
.NUM_DATA_I (0+NUM_PORTS),
|
||||||
.NUM_DATA_O (NUM_DATA_O),
|
.NUM_DATA_O (0+NUM_PORTS),
|
||||||
.CTRL_FIFOSIZE (CTRL_FIFO_SIZE),
|
.CTRL_FIFOSIZE ($clog2(32)),
|
||||||
.MTU (MTU)
|
.MTU (MTU)
|
||||||
) backend_iface_i (
|
) backend_iface_i (
|
||||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
||||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||||
.rfnoc_core_config (rfnoc_core_config),
|
.rfnoc_core_config (rfnoc_core_config),
|
||||||
.rfnoc_core_status (rfnoc_core_status),
|
.rfnoc_core_status (rfnoc_core_status),
|
||||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
|
||||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
|
||||||
.data_i_flush_en (data_i_flush_en),
|
.data_i_flush_en (data_i_flush_en),
|
||||||
.data_i_flush_timeout (data_i_flush_timeout),
|
.data_i_flush_timeout (data_i_flush_timeout),
|
||||||
.data_i_flush_active (data_i_flush_active),
|
.data_i_flush_active (data_i_flush_active),
|
||||||
@@ -166,52 +153,71 @@ module noc_shell_fir_filter #(
|
|||||||
.data_o_flush_done (data_o_flush_done)
|
.data_o_flush_done (data_o_flush_done)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Reset Generation
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
wire ce_rst_pulse;
|
||||||
|
|
||||||
|
pulse_synchronizer #(.MODE ("POSEDGE")) pulse_synchronizer_ce (
|
||||||
|
.clk_a(rfnoc_chdr_clk), .rst_a(1'b0), .pulse_a (rfnoc_chdr_rst), .busy_a (),
|
||||||
|
.clk_b(ce_clk), .pulse_b (ce_rst_pulse)
|
||||||
|
);
|
||||||
|
|
||||||
|
pulse_stretch_min #(.LENGTH(32)) pulse_stretch_min_ce (
|
||||||
|
.clk(ce_clk), .rst(1'b0),
|
||||||
|
.pulse_in(ce_rst_pulse), .pulse_out(ce_rst)
|
||||||
|
);
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// Control Path
|
// Control Path
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
assign ctrlport_clk = ce_clk;
|
||||||
|
assign ctrlport_rst = ce_rst;
|
||||||
|
|
||||||
ctrlport_endpoint #(
|
ctrlport_endpoint #(
|
||||||
.THIS_PORTID (THIS_PORTID ),
|
.THIS_PORTID (THIS_PORTID),
|
||||||
.SYNC_CLKS (0 ),
|
.SYNC_CLKS (0),
|
||||||
.AXIS_CTRL_MST_EN (CTRLPORT_SLV_EN),
|
.AXIS_CTRL_MST_EN (0),
|
||||||
.AXIS_CTRL_SLV_EN (CTRLPORT_MST_EN),
|
.AXIS_CTRL_SLV_EN (1),
|
||||||
.SLAVE_FIFO_SIZE (CTRL_FIFO_SIZE )
|
.SLAVE_FIFO_SIZE ($clog2(32))
|
||||||
) ctrlport_ep_i (
|
) ctrlport_endpoint_i (
|
||||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||||
.ctrlport_clk (ctrlport_clk ),
|
.ctrlport_clk (ctrlport_clk),
|
||||||
.ctrlport_rst (ctrlport_rst ),
|
.ctrlport_rst (ctrlport_rst),
|
||||||
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata ),
|
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
||||||
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast ),
|
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
||||||
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid ),
|
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
||||||
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready ),
|
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
||||||
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata ),
|
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
||||||
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast ),
|
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
||||||
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid ),
|
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
||||||
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready ),
|
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
||||||
.m_ctrlport_req_wr (m_ctrlport_req_wr ),
|
.m_ctrlport_req_wr (m_ctrlport_req_wr),
|
||||||
.m_ctrlport_req_rd (m_ctrlport_req_rd ),
|
.m_ctrlport_req_rd (m_ctrlport_req_rd),
|
||||||
.m_ctrlport_req_addr (m_ctrlport_req_addr ),
|
.m_ctrlport_req_addr (m_ctrlport_req_addr),
|
||||||
.m_ctrlport_req_data (m_ctrlport_req_data ),
|
.m_ctrlport_req_data (m_ctrlport_req_data),
|
||||||
.m_ctrlport_req_byte_en (m_ctrlport_req_byte_en ),
|
.m_ctrlport_req_byte_en (),
|
||||||
.m_ctrlport_req_has_time (m_ctrlport_req_has_time ),
|
.m_ctrlport_req_has_time (),
|
||||||
.m_ctrlport_req_time (m_ctrlport_req_time ),
|
.m_ctrlport_req_time (),
|
||||||
.m_ctrlport_resp_ack (m_ctrlport_resp_ack ),
|
.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
|
||||||
.m_ctrlport_resp_status (m_ctrlport_resp_status ),
|
.m_ctrlport_resp_status (2'b0),
|
||||||
.m_ctrlport_resp_data (m_ctrlport_resp_data ),
|
.m_ctrlport_resp_data (m_ctrlport_resp_data),
|
||||||
.s_ctrlport_req_wr (s_ctrlport_req_wr ),
|
.s_ctrlport_req_wr (1'b0),
|
||||||
.s_ctrlport_req_rd (s_ctrlport_req_rd ),
|
.s_ctrlport_req_rd (1'b0),
|
||||||
.s_ctrlport_req_addr (s_ctrlport_req_addr ),
|
.s_ctrlport_req_addr (20'b0),
|
||||||
.s_ctrlport_req_portid (s_ctrlport_req_portid ),
|
.s_ctrlport_req_portid (10'b0),
|
||||||
.s_ctrlport_req_rem_epid (s_ctrlport_req_rem_epid ),
|
.s_ctrlport_req_rem_epid (16'b0),
|
||||||
.s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
|
.s_ctrlport_req_rem_portid (10'b0),
|
||||||
.s_ctrlport_req_data (s_ctrlport_req_data ),
|
.s_ctrlport_req_data (32'b0),
|
||||||
.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en ),
|
.s_ctrlport_req_byte_en (4'hF),
|
||||||
.s_ctrlport_req_has_time (s_ctrlport_req_has_time ),
|
.s_ctrlport_req_has_time (1'b0),
|
||||||
.s_ctrlport_req_time (s_ctrlport_req_time ),
|
.s_ctrlport_req_time (64'b0),
|
||||||
.s_ctrlport_resp_ack (s_ctrlport_resp_ack ),
|
.s_ctrlport_resp_ack (),
|
||||||
.s_ctrlport_resp_status (s_ctrlport_resp_status ),
|
.s_ctrlport_resp_status (),
|
||||||
.s_ctrlport_resp_data (s_ctrlport_resp_data )
|
.s_ctrlport_resp_data ()
|
||||||
);
|
);
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -219,79 +225,91 @@ module noc_shell_fir_filter #(
|
|||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
genvar i;
|
genvar i;
|
||||||
generate
|
|
||||||
|
|
||||||
for (i = 0; i < NUM_DATA_I; i = i + 1) begin: chdr_to_data
|
assign axis_data_clk = ce_clk;
|
||||||
chdr_to_axis_pyld_ctxt #(
|
assign axis_data_rst = ce_rst;
|
||||||
.CHDR_W (CHDR_W ),
|
|
||||||
.ITEM_W (ITEM_W ),
|
|
||||||
.NIPC (NIPC ),
|
|
||||||
.SYNC_CLKS (SYNC_CLKS ),
|
|
||||||
.CONTEXT_FIFO_SIZE (CTXT_FIFO_SIZE),
|
|
||||||
.PAYLOAD_FIFO_SIZE (PYLD_FIFO_SIZE),
|
|
||||||
.CONTEXT_PREFETCH_EN (1 )
|
|
||||||
) chdr_to_axis_pyld_ctxt_i (
|
|
||||||
.axis_chdr_clk (rfnoc_chdr_clk ),
|
|
||||||
.axis_chdr_rst (rfnoc_chdr_rst ),
|
|
||||||
.axis_data_clk (axis_data_clk ),
|
|
||||||
.axis_data_rst (axis_data_rst ),
|
|
||||||
.s_axis_chdr_tdata (s_rfnoc_chdr_tdata [(i*CHDR_W)+:CHDR_W] ),
|
|
||||||
.s_axis_chdr_tlast (s_rfnoc_chdr_tlast [i] ),
|
|
||||||
.s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid [i] ),
|
|
||||||
.s_axis_chdr_tready (s_rfnoc_chdr_tready [i] ),
|
|
||||||
.m_axis_payload_tdata (m_axis_payload_tdata [(i*ITEM_W*NIPC)+:(ITEM_W*NIPC)]),
|
|
||||||
.m_axis_payload_tkeep (m_axis_payload_tkeep [(i*NIPC)+:NIPC] ),
|
|
||||||
.m_axis_payload_tlast (m_axis_payload_tlast [i] ),
|
|
||||||
.m_axis_payload_tvalid(m_axis_payload_tvalid[i] ),
|
|
||||||
.m_axis_payload_tready(m_axis_payload_tready[i] ),
|
|
||||||
.m_axis_context_tdata (m_axis_context_tdata [(i*CHDR_W)+:(CHDR_W)] ),
|
|
||||||
.m_axis_context_tuser (m_axis_context_tuser [(i*4)+:4] ),
|
|
||||||
.m_axis_context_tlast (m_axis_context_tlast [i] ),
|
|
||||||
.m_axis_context_tvalid(m_axis_context_tvalid[i] ),
|
|
||||||
.m_axis_context_tready(m_axis_context_tready[i] ),
|
|
||||||
.flush_en (data_i_flush_en ),
|
|
||||||
.flush_timeout (data_i_flush_timeout ),
|
|
||||||
.flush_active (data_i_flush_active [i] ),
|
|
||||||
.flush_done (data_i_flush_done [i] )
|
|
||||||
);
|
|
||||||
end
|
|
||||||
|
|
||||||
for (i = 0; i < NUM_DATA_O; i = i + 1) begin: data_to_chdr
|
//---------------------
|
||||||
axis_pyld_ctxt_to_chdr #(
|
// Input Data Paths
|
||||||
.CHDR_W (CHDR_W ),
|
//---------------------
|
||||||
.ITEM_W (ITEM_W ),
|
|
||||||
.NIPC (NIPC ),
|
|
||||||
.SYNC_CLKS (SYNC_CLKS ),
|
|
||||||
.CONTEXT_FIFO_SIZE (CTXT_FIFO_SIZE),
|
|
||||||
.PAYLOAD_FIFO_SIZE (PYLD_FIFO_SIZE),
|
|
||||||
.CONTEXT_PREFETCH_EN (1 ),
|
|
||||||
.MTU (MTU )
|
|
||||||
) axis_pyld_ctxt_to_chdr_i (
|
|
||||||
.axis_chdr_clk (rfnoc_chdr_clk ),
|
|
||||||
.axis_chdr_rst (rfnoc_chdr_rst ),
|
|
||||||
.axis_data_clk (axis_data_clk ),
|
|
||||||
.axis_data_rst (axis_data_rst ),
|
|
||||||
.m_axis_chdr_tdata (m_rfnoc_chdr_tdata [(i*CHDR_W)+:CHDR_W] ),
|
|
||||||
.m_axis_chdr_tlast (m_rfnoc_chdr_tlast [i] ),
|
|
||||||
.m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid [i] ),
|
|
||||||
.m_axis_chdr_tready (m_rfnoc_chdr_tready [i] ),
|
|
||||||
.s_axis_payload_tdata (s_axis_payload_tdata [(i*ITEM_W*NIPC)+:(ITEM_W*NIPC)]),
|
|
||||||
.s_axis_payload_tkeep (s_axis_payload_tkeep [(i*NIPC)+:NIPC] ),
|
|
||||||
.s_axis_payload_tlast (s_axis_payload_tlast [i] ),
|
|
||||||
.s_axis_payload_tvalid(s_axis_payload_tvalid[i] ),
|
|
||||||
.s_axis_payload_tready(s_axis_payload_tready[i] ),
|
|
||||||
.s_axis_context_tdata (s_axis_context_tdata [(i*CHDR_W)+:(CHDR_W)] ),
|
|
||||||
.s_axis_context_tuser (s_axis_context_tuser [(i*4)+:4] ),
|
|
||||||
.s_axis_context_tlast (s_axis_context_tlast [i] ),
|
|
||||||
.s_axis_context_tvalid(s_axis_context_tvalid[i] ),
|
|
||||||
.s_axis_context_tready(s_axis_context_tready[i] ),
|
|
||||||
.framer_errors ( ),
|
|
||||||
.flush_en (data_o_flush_en ),
|
|
||||||
.flush_timeout (data_o_flush_timeout ),
|
|
||||||
.flush_active (data_o_flush_active [i] ),
|
|
||||||
.flush_done (data_o_flush_done [i] )
|
|
||||||
);
|
|
||||||
end
|
|
||||||
endgenerate
|
|
||||||
|
|
||||||
endmodule
|
for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_input_in
|
||||||
|
chdr_to_axis_pyld_ctxt #(
|
||||||
|
.CHDR_W (CHDR_W),
|
||||||
|
.ITEM_W (32),
|
||||||
|
.NIPC (1),
|
||||||
|
.SYNC_CLKS (0),
|
||||||
|
.CONTEXT_FIFO_SIZE ($clog2(2)),
|
||||||
|
.PAYLOAD_FIFO_SIZE ($clog2(32)),
|
||||||
|
.CONTEXT_PREFETCH_EN (1)
|
||||||
|
) chdr_to_axis_pyld_ctxt_in_in (
|
||||||
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
|
.axis_data_clk (axis_data_clk),
|
||||||
|
.axis_data_rst (axis_data_rst),
|
||||||
|
.s_axis_chdr_tdata (s_rfnoc_chdr_tdata[((0+i)*CHDR_W)+:CHDR_W]),
|
||||||
|
.s_axis_chdr_tlast (s_rfnoc_chdr_tlast[0+i]),
|
||||||
|
.s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[0+i]),
|
||||||
|
.s_axis_chdr_tready (s_rfnoc_chdr_tready[0+i]),
|
||||||
|
.m_axis_payload_tdata (m_in_payload_tdata[(32*1)*i+:(32*1)]),
|
||||||
|
.m_axis_payload_tkeep (m_in_payload_tkeep[1*i+:1]),
|
||||||
|
.m_axis_payload_tlast (m_in_payload_tlast[i]),
|
||||||
|
.m_axis_payload_tvalid (m_in_payload_tvalid[i]),
|
||||||
|
.m_axis_payload_tready (m_in_payload_tready[i]),
|
||||||
|
.m_axis_context_tdata (m_in_context_tdata[CHDR_W*i+:CHDR_W]),
|
||||||
|
.m_axis_context_tuser (m_in_context_tuser[4*i+:4]),
|
||||||
|
.m_axis_context_tlast (m_in_context_tlast[i]),
|
||||||
|
.m_axis_context_tvalid (m_in_context_tvalid[i]),
|
||||||
|
.m_axis_context_tready (m_in_context_tready[i]),
|
||||||
|
.flush_en (data_i_flush_en),
|
||||||
|
.flush_timeout (data_i_flush_timeout),
|
||||||
|
.flush_active (data_i_flush_active[0+i]),
|
||||||
|
.flush_done (data_i_flush_done[0+i])
|
||||||
|
);
|
||||||
|
end
|
||||||
|
|
||||||
|
//---------------------
|
||||||
|
// Output Data Paths
|
||||||
|
//---------------------
|
||||||
|
|
||||||
|
for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_output_out
|
||||||
|
axis_pyld_ctxt_to_chdr #(
|
||||||
|
.CHDR_W (CHDR_W),
|
||||||
|
.ITEM_W (32),
|
||||||
|
.NIPC (1),
|
||||||
|
.SYNC_CLKS (0),
|
||||||
|
.CONTEXT_FIFO_SIZE ($clog2(2)),
|
||||||
|
.PAYLOAD_FIFO_SIZE ($clog2(32)),
|
||||||
|
.MTU (MTU),
|
||||||
|
.CONTEXT_PREFETCH_EN (1)
|
||||||
|
) axis_pyld_ctxt_to_chdr_out_out (
|
||||||
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
|
.axis_data_clk (axis_data_clk),
|
||||||
|
.axis_data_rst (axis_data_rst),
|
||||||
|
.m_axis_chdr_tdata (m_rfnoc_chdr_tdata[(0+i)*CHDR_W+:CHDR_W]),
|
||||||
|
.m_axis_chdr_tlast (m_rfnoc_chdr_tlast[0+i]),
|
||||||
|
.m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[0+i]),
|
||||||
|
.m_axis_chdr_tready (m_rfnoc_chdr_tready[0+i]),
|
||||||
|
.s_axis_payload_tdata (s_out_payload_tdata[(32*1)*i+:(32*1)]),
|
||||||
|
.s_axis_payload_tkeep (s_out_payload_tkeep[1*i+:1]),
|
||||||
|
.s_axis_payload_tlast (s_out_payload_tlast[i]),
|
||||||
|
.s_axis_payload_tvalid (s_out_payload_tvalid[i]),
|
||||||
|
.s_axis_payload_tready (s_out_payload_tready[i]),
|
||||||
|
.s_axis_context_tdata (s_out_context_tdata[CHDR_W*i+:CHDR_W]),
|
||||||
|
.s_axis_context_tuser (s_out_context_tuser[4*i+:4]),
|
||||||
|
.s_axis_context_tlast (s_out_context_tlast[i]),
|
||||||
|
.s_axis_context_tvalid (s_out_context_tvalid[i]),
|
||||||
|
.s_axis_context_tready (s_out_context_tready[i]),
|
||||||
|
.framer_errors (),
|
||||||
|
.flush_en (data_o_flush_en),
|
||||||
|
.flush_timeout (data_o_flush_timeout),
|
||||||
|
.flush_active (data_o_flush_active[0+i]),
|
||||||
|
.flush_done (data_o_flush_done[0+i])
|
||||||
|
);
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule // noc_shell_fir_filter
|
||||||
|
|
||||||
|
|
||||||
|
`default_nettype wire
|
||||||
|
|||||||
@@ -127,7 +127,6 @@ module rfnoc_block_fir_filter #(
|
|||||||
wire [19:0] ctrlport_reg_req_addr;
|
wire [19:0] ctrlport_reg_req_addr;
|
||||||
wire [31:0] ctrlport_reg_req_data;
|
wire [31:0] ctrlport_reg_req_data;
|
||||||
wire ctrlport_reg_resp_ack;
|
wire ctrlport_reg_resp_ack;
|
||||||
wire [ 1:0] ctrlport_reg_resp_status;
|
|
||||||
wire [31:0] ctrlport_reg_resp_data;
|
wire [31:0] ctrlport_reg_resp_data;
|
||||||
|
|
||||||
wire [(NUM_PORTS*ITEM_W*NIPC)-1:0] axis_to_fir_tdata;
|
wire [(NUM_PORTS*ITEM_W*NIPC)-1:0] axis_to_fir_tdata;
|
||||||
@@ -152,104 +151,68 @@ module rfnoc_block_fir_filter #(
|
|||||||
wire [ NUM_PORTS-1:0] s_axis_context_tvalid;
|
wire [ NUM_PORTS-1:0] s_axis_context_tvalid;
|
||||||
wire [ NUM_PORTS-1:0] s_axis_context_tready;
|
wire [ NUM_PORTS-1:0] s_axis_context_tready;
|
||||||
|
|
||||||
wire rfnoc_chdr_rst;
|
|
||||||
wire ce_rst;
|
wire ce_rst;
|
||||||
|
|
||||||
localparam NOC_ID = 32'hF112_0000;
|
|
||||||
|
|
||||||
|
|
||||||
// Cross the CHDR reset to the ddc_clk domain
|
|
||||||
synchronizer ce_rst_sync_i (
|
|
||||||
.clk (ce_clk),
|
|
||||||
.rst (1'b0),
|
|
||||||
.in (rfnoc_chdr_rst),
|
|
||||||
.out (ce_rst)
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
noc_shell_fir_filter #(
|
noc_shell_fir_filter #(
|
||||||
.NOC_ID (NOC_ID),
|
.THIS_PORTID (THIS_PORTID),
|
||||||
.THIS_PORTID (THIS_PORTID),
|
.CHDR_W (CHDR_W),
|
||||||
.CHDR_W (CHDR_W),
|
.NUM_PORTS (NUM_PORTS),
|
||||||
.CTRLPORT_SLV_EN (0),
|
.MTU (MTU)
|
||||||
.CTRLPORT_MST_EN (1),
|
|
||||||
.NUM_DATA_I (NUM_PORTS),
|
|
||||||
.NUM_DATA_O (NUM_PORTS),
|
|
||||||
.ITEM_W (ITEM_W),
|
|
||||||
.NIPC (NIPC),
|
|
||||||
.PYLD_FIFO_SIZE (5),
|
|
||||||
.CTXT_FIFO_SIZE (5),
|
|
||||||
.MTU (MTU)
|
|
||||||
) noc_shell_fir_filter_i (
|
) noc_shell_fir_filter_i (
|
||||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
.ce_clk (ce_clk),
|
||||||
.rfnoc_ctrl_rst (),
|
.rfnoc_chdr_rst (),
|
||||||
.rfnoc_core_config (rfnoc_core_config),
|
.rfnoc_ctrl_rst (),
|
||||||
.rfnoc_core_status (rfnoc_core_status),
|
.ce_rst (ce_rst),
|
||||||
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
|
.rfnoc_core_config (rfnoc_core_config),
|
||||||
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
|
.rfnoc_core_status (rfnoc_core_status),
|
||||||
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
|
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
|
||||||
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
|
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
|
||||||
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
|
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
|
||||||
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
|
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
|
||||||
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
|
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
|
||||||
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
|
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
|
||||||
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
|
||||||
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
|
||||||
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
||||||
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
||||||
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
||||||
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
||||||
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
||||||
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
||||||
.ctrlport_clk (ce_clk),
|
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
||||||
.ctrlport_rst (ce_rst),
|
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
||||||
.m_ctrlport_req_wr (ctrlport_reg_req_wr),
|
.ctrlport_clk (),
|
||||||
.m_ctrlport_req_rd (ctrlport_reg_req_rd),
|
.ctrlport_rst (),
|
||||||
.m_ctrlport_req_addr (ctrlport_reg_req_addr),
|
.m_ctrlport_req_wr (ctrlport_reg_req_wr),
|
||||||
.m_ctrlport_req_data (ctrlport_reg_req_data),
|
.m_ctrlport_req_rd (ctrlport_reg_req_rd),
|
||||||
.m_ctrlport_req_byte_en (),
|
.m_ctrlport_req_addr (ctrlport_reg_req_addr),
|
||||||
.m_ctrlport_req_has_time (),
|
.m_ctrlport_req_data (ctrlport_reg_req_data),
|
||||||
.m_ctrlport_req_time (),
|
.m_ctrlport_resp_ack (ctrlport_reg_resp_ack),
|
||||||
.m_ctrlport_resp_ack (ctrlport_reg_resp_ack),
|
.m_ctrlport_resp_data (ctrlport_reg_resp_data),
|
||||||
.m_ctrlport_resp_status (ctrlport_reg_resp_status),
|
.axis_data_clk (),
|
||||||
.m_ctrlport_resp_data (ctrlport_reg_resp_data),
|
.axis_data_rst (),
|
||||||
.s_ctrlport_req_wr (1'b0),
|
.m_in_payload_tdata (axis_to_fir_tdata),
|
||||||
.s_ctrlport_req_rd (1'b0),
|
.m_in_payload_tkeep (),
|
||||||
.s_ctrlport_req_addr (20'b0),
|
.m_in_payload_tlast (axis_to_fir_tlast),
|
||||||
.s_ctrlport_req_portid (10'b0),
|
.m_in_payload_tvalid (axis_to_fir_tvalid),
|
||||||
.s_ctrlport_req_rem_epid (16'b0),
|
.m_in_payload_tready (axis_to_fir_tready),
|
||||||
.s_ctrlport_req_rem_portid (10'b0),
|
.m_in_context_tdata (m_axis_context_tdata),
|
||||||
.s_ctrlport_req_data (32'b0),
|
.m_in_context_tuser (m_axis_context_tuser),
|
||||||
.s_ctrlport_req_byte_en (4'hF),
|
.m_in_context_tlast (m_axis_context_tlast),
|
||||||
.s_ctrlport_req_has_time (1'b0),
|
.m_in_context_tvalid (m_axis_context_tvalid),
|
||||||
.s_ctrlport_req_time (64'b0),
|
.m_in_context_tready (m_axis_context_tready),
|
||||||
.s_ctrlport_resp_ack (),
|
.s_out_payload_tdata (axis_from_fir_tdata),
|
||||||
.s_ctrlport_resp_status (),
|
.s_out_payload_tkeep ({NUM_PORTS*NIPC{1'b1}}),
|
||||||
.s_ctrlport_resp_data (),
|
.s_out_payload_tlast (axis_from_fir_tlast),
|
||||||
.axis_data_clk (ce_clk),
|
.s_out_payload_tvalid (axis_from_fir_tvalid),
|
||||||
.axis_data_rst (ce_rst),
|
.s_out_payload_tready (axis_from_fir_tready),
|
||||||
.m_axis_payload_tdata (axis_to_fir_tdata),
|
.s_out_context_tdata (s_axis_context_tdata),
|
||||||
.m_axis_payload_tkeep (),
|
.s_out_context_tuser (s_axis_context_tuser),
|
||||||
.m_axis_payload_tlast (axis_to_fir_tlast),
|
.s_out_context_tlast (s_axis_context_tlast),
|
||||||
.m_axis_payload_tvalid (axis_to_fir_tvalid),
|
.s_out_context_tvalid (s_axis_context_tvalid),
|
||||||
.m_axis_payload_tready (axis_to_fir_tready),
|
.s_out_context_tready (s_axis_context_tready)
|
||||||
.s_axis_payload_tdata (axis_from_fir_tdata),
|
|
||||||
.s_axis_payload_tkeep ({NUM_PORTS*NIPC{1'b1}}),
|
|
||||||
.s_axis_payload_tlast (axis_from_fir_tlast),
|
|
||||||
.s_axis_payload_tvalid (axis_from_fir_tvalid),
|
|
||||||
.s_axis_payload_tready (axis_from_fir_tready),
|
|
||||||
.m_axis_context_tdata (m_axis_context_tdata),
|
|
||||||
.m_axis_context_tuser (m_axis_context_tuser),
|
|
||||||
.m_axis_context_tlast (m_axis_context_tlast),
|
|
||||||
.m_axis_context_tvalid (m_axis_context_tvalid),
|
|
||||||
.m_axis_context_tready (m_axis_context_tready),
|
|
||||||
.s_axis_context_tdata (s_axis_context_tdata),
|
|
||||||
.s_axis_context_tuser (s_axis_context_tuser),
|
|
||||||
.s_axis_context_tlast (s_axis_context_tlast),
|
|
||||||
.s_axis_context_tvalid (s_axis_context_tvalid),
|
|
||||||
.s_axis_context_tready (s_axis_context_tready)
|
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
@@ -290,7 +253,7 @@ module rfnoc_block_fir_filter #(
|
|||||||
.s_ctrlport_req_has_time (1'b0),
|
.s_ctrlport_req_has_time (1'b0),
|
||||||
.s_ctrlport_req_time (64'b0),
|
.s_ctrlport_req_time (64'b0),
|
||||||
.s_ctrlport_resp_ack (ctrlport_reg_resp_ack),
|
.s_ctrlport_resp_ack (ctrlport_reg_resp_ack),
|
||||||
.s_ctrlport_resp_status (ctrlport_reg_resp_status),
|
.s_ctrlport_resp_status (),
|
||||||
.s_ctrlport_resp_data (ctrlport_reg_resp_data),
|
.s_ctrlport_resp_data (ctrlport_reg_resp_data),
|
||||||
.m_ctrlport_req_wr (m_ctrlport_req_wr),
|
.m_ctrlport_req_wr (m_ctrlport_req_wr),
|
||||||
.m_ctrlport_req_rd (m_ctrlport_req_rd),
|
.m_ctrlport_req_rd (m_ctrlport_req_rd),
|
||||||
|
|||||||
@@ -27,6 +27,8 @@ module rfnoc_block_fir_filter_tb #(
|
|||||||
// Local Parameters
|
// Local Parameters
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
localparam int NOC_ID = 32'hF112_0000;
|
||||||
|
|
||||||
// Simulation parameters
|
// Simulation parameters
|
||||||
localparam real CHDR_CLK_PER = 6.0; // 166 MHz
|
localparam real CHDR_CLK_PER = 6.0; // 166 MHz
|
||||||
localparam real CE_CLK_PER = 5.0; // 200 MHz
|
localparam real CE_CLK_PER = 5.0; // 200 MHz
|
||||||
@@ -218,7 +220,7 @@ module rfnoc_block_fir_filter_tb #(
|
|||||||
//-------------------------------------------------------------------------
|
//-------------------------------------------------------------------------
|
||||||
|
|
||||||
test.start_test("Verify Block Info", 2us);
|
test.start_test("Verify Block Info", 2us);
|
||||||
`ASSERT_ERROR(blk_ctrl.get_noc_id() == rfnoc_block_fir_filter_i.NOC_ID, "Incorrect NOC_ID Value");
|
`ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I Value");
|
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O Value");
|
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
|
`ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
|
||||||
|
|||||||
@@ -8,5 +8,6 @@
|
|||||||
# RFNoC Utility Sources
|
# RFNoC Utility Sources
|
||||||
##################################################
|
##################################################
|
||||||
RFNOC_OOT_SRCS += $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_null_src_sink/, \
|
RFNOC_OOT_SRCS += $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/rfnoc_block_null_src_sink/, \
|
||||||
|
noc_shell_null_src_sink.v \
|
||||||
rfnoc_block_null_src_sink.v \
|
rfnoc_block_null_src_sink.v \
|
||||||
))
|
))
|
||||||
|
|||||||
@@ -0,0 +1,377 @@
|
|||||||
|
//
|
||||||
|
// Copyright 2019 Ettus Research, A National Instruments Brand
|
||||||
|
//
|
||||||
|
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||||
|
//
|
||||||
|
// Module: noc_shell_null_src_sink
|
||||||
|
//
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// This is a tool-generated NoC-shell for the null_src_sink block.
|
||||||
|
// See the RFNoC specification for more information about NoC shells.
|
||||||
|
//
|
||||||
|
// Parameters:
|
||||||
|
//
|
||||||
|
// THIS_PORTID : Control crossbar port to which this block is connected
|
||||||
|
// CHDR_W : AXIS-CHDR data bus width
|
||||||
|
// MTU : Maximum transmission unit (i.e., maximum packet size in
|
||||||
|
//
|
||||||
|
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
|
||||||
|
module noc_shell_null_src_sink #(
|
||||||
|
parameter [9:0] THIS_PORTID = 10'd0,
|
||||||
|
parameter CHDR_W = 64,
|
||||||
|
parameter [5:0] MTU = 10
|
||||||
|
) (
|
||||||
|
//---------------------
|
||||||
|
// Framework Interface
|
||||||
|
//---------------------
|
||||||
|
|
||||||
|
// RFNoC Framework Clocks
|
||||||
|
input wire rfnoc_chdr_clk,
|
||||||
|
input wire rfnoc_ctrl_clk,
|
||||||
|
|
||||||
|
// NoC Shell Generated Resets
|
||||||
|
output wire rfnoc_chdr_rst,
|
||||||
|
output wire rfnoc_ctrl_rst,
|
||||||
|
|
||||||
|
// RFNoC Backend Interface
|
||||||
|
input wire [511:0] rfnoc_core_config,
|
||||||
|
output wire [511:0] rfnoc_core_status,
|
||||||
|
|
||||||
|
// AXIS-CHDR Input Ports (from framework)
|
||||||
|
input wire [(2)*CHDR_W-1:0] s_rfnoc_chdr_tdata,
|
||||||
|
input wire [(2)-1:0] s_rfnoc_chdr_tlast,
|
||||||
|
input wire [(2)-1:0] s_rfnoc_chdr_tvalid,
|
||||||
|
output wire [(2)-1:0] s_rfnoc_chdr_tready,
|
||||||
|
// AXIS-CHDR Output Ports (to framework)
|
||||||
|
output wire [(2)*CHDR_W-1:0] m_rfnoc_chdr_tdata,
|
||||||
|
output wire [(2)-1:0] m_rfnoc_chdr_tlast,
|
||||||
|
output wire [(2)-1:0] m_rfnoc_chdr_tvalid,
|
||||||
|
input wire [(2)-1:0] m_rfnoc_chdr_tready,
|
||||||
|
|
||||||
|
// AXIS-Ctrl Control Input Port (from framework)
|
||||||
|
input wire [31:0] s_rfnoc_ctrl_tdata,
|
||||||
|
input wire s_rfnoc_ctrl_tlast,
|
||||||
|
input wire s_rfnoc_ctrl_tvalid,
|
||||||
|
output wire s_rfnoc_ctrl_tready,
|
||||||
|
// AXIS-Ctrl Control Output Port (to framework)
|
||||||
|
output wire [31:0] m_rfnoc_ctrl_tdata,
|
||||||
|
output wire m_rfnoc_ctrl_tlast,
|
||||||
|
output wire m_rfnoc_ctrl_tvalid,
|
||||||
|
input wire m_rfnoc_ctrl_tready,
|
||||||
|
|
||||||
|
//---------------------
|
||||||
|
// Client Interface
|
||||||
|
//---------------------
|
||||||
|
|
||||||
|
// CtrlPort Clock and Reset
|
||||||
|
output wire ctrlport_clk,
|
||||||
|
output wire ctrlport_rst,
|
||||||
|
// CtrlPort Master
|
||||||
|
output wire m_ctrlport_req_wr,
|
||||||
|
output wire m_ctrlport_req_rd,
|
||||||
|
output wire [19:0] m_ctrlport_req_addr,
|
||||||
|
output wire [31:0] m_ctrlport_req_data,
|
||||||
|
input wire m_ctrlport_resp_ack,
|
||||||
|
input wire [31:0] m_ctrlport_resp_data,
|
||||||
|
|
||||||
|
// AXI-Stream Payload Context Clock and Reset
|
||||||
|
output wire axis_data_clk,
|
||||||
|
output wire axis_data_rst,
|
||||||
|
// Payload Stream to User Logic: sink
|
||||||
|
output wire [32*2-1:0] m_sink_payload_tdata,
|
||||||
|
output wire [2-1:0] m_sink_payload_tkeep,
|
||||||
|
output wire m_sink_payload_tlast,
|
||||||
|
output wire m_sink_payload_tvalid,
|
||||||
|
input wire m_sink_payload_tready,
|
||||||
|
// Context Stream to User Logic: sink
|
||||||
|
output wire [CHDR_W-1:0] m_sink_context_tdata,
|
||||||
|
output wire [3:0] m_sink_context_tuser,
|
||||||
|
output wire m_sink_context_tlast,
|
||||||
|
output wire m_sink_context_tvalid,
|
||||||
|
input wire m_sink_context_tready,
|
||||||
|
// Payload Stream to User Logic: loop
|
||||||
|
output wire [32*2-1:0] m_loop_payload_tdata,
|
||||||
|
output wire [2-1:0] m_loop_payload_tkeep,
|
||||||
|
output wire m_loop_payload_tlast,
|
||||||
|
output wire m_loop_payload_tvalid,
|
||||||
|
input wire m_loop_payload_tready,
|
||||||
|
// Context Stream to User Logic: loop
|
||||||
|
output wire [CHDR_W-1:0] m_loop_context_tdata,
|
||||||
|
output wire [3:0] m_loop_context_tuser,
|
||||||
|
output wire m_loop_context_tlast,
|
||||||
|
output wire m_loop_context_tvalid,
|
||||||
|
input wire m_loop_context_tready,
|
||||||
|
// Payload Stream from User Logic: source
|
||||||
|
input wire [32*2-1:0] s_source_payload_tdata,
|
||||||
|
input wire [1:0] s_source_payload_tkeep,
|
||||||
|
input wire s_source_payload_tlast,
|
||||||
|
input wire s_source_payload_tvalid,
|
||||||
|
output wire s_source_payload_tready,
|
||||||
|
// Context Stream from User Logic: source
|
||||||
|
input wire [CHDR_W-1:0] s_source_context_tdata,
|
||||||
|
input wire [3:0] s_source_context_tuser,
|
||||||
|
input wire s_source_context_tlast,
|
||||||
|
input wire s_source_context_tvalid,
|
||||||
|
output wire s_source_context_tready,
|
||||||
|
// Payload Stream from User Logic: loop
|
||||||
|
input wire [32*2-1:0] s_loop_payload_tdata,
|
||||||
|
input wire [1:0] s_loop_payload_tkeep,
|
||||||
|
input wire s_loop_payload_tlast,
|
||||||
|
input wire s_loop_payload_tvalid,
|
||||||
|
output wire s_loop_payload_tready,
|
||||||
|
// Context Stream from User Logic: loop
|
||||||
|
input wire [CHDR_W-1:0] s_loop_context_tdata,
|
||||||
|
input wire [3:0] s_loop_context_tuser,
|
||||||
|
input wire s_loop_context_tlast,
|
||||||
|
input wire s_loop_context_tvalid,
|
||||||
|
output wire s_loop_context_tready
|
||||||
|
);
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Backend Interface
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
wire data_i_flush_en;
|
||||||
|
wire [31:0] data_i_flush_timeout;
|
||||||
|
wire [63:0] data_i_flush_active;
|
||||||
|
wire [63:0] data_i_flush_done;
|
||||||
|
wire data_o_flush_en;
|
||||||
|
wire [31:0] data_o_flush_timeout;
|
||||||
|
wire [63:0] data_o_flush_active;
|
||||||
|
wire [63:0] data_o_flush_done;
|
||||||
|
|
||||||
|
backend_iface #(
|
||||||
|
.NOC_ID (32'h00000001),
|
||||||
|
.NUM_DATA_I (2),
|
||||||
|
.NUM_DATA_O (2),
|
||||||
|
.CTRL_FIFOSIZE ($clog2(32)),
|
||||||
|
.MTU (MTU)
|
||||||
|
) backend_iface_i (
|
||||||
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
||||||
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||||
|
.rfnoc_core_config (rfnoc_core_config),
|
||||||
|
.rfnoc_core_status (rfnoc_core_status),
|
||||||
|
.data_i_flush_en (data_i_flush_en),
|
||||||
|
.data_i_flush_timeout (data_i_flush_timeout),
|
||||||
|
.data_i_flush_active (data_i_flush_active),
|
||||||
|
.data_i_flush_done (data_i_flush_done),
|
||||||
|
.data_o_flush_en (data_o_flush_en),
|
||||||
|
.data_o_flush_timeout (data_o_flush_timeout),
|
||||||
|
.data_o_flush_active (data_o_flush_active),
|
||||||
|
.data_o_flush_done (data_o_flush_done)
|
||||||
|
);
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Control Path
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
assign ctrlport_clk = rfnoc_chdr_clk;
|
||||||
|
assign ctrlport_rst = rfnoc_chdr_rst;
|
||||||
|
|
||||||
|
ctrlport_endpoint #(
|
||||||
|
.THIS_PORTID (THIS_PORTID),
|
||||||
|
.SYNC_CLKS (0),
|
||||||
|
.AXIS_CTRL_MST_EN (0),
|
||||||
|
.AXIS_CTRL_SLV_EN (1),
|
||||||
|
.SLAVE_FIFO_SIZE ($clog2(32))
|
||||||
|
) ctrlport_endpoint_i (
|
||||||
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||||
|
.ctrlport_clk (ctrlport_clk),
|
||||||
|
.ctrlport_rst (ctrlport_rst),
|
||||||
|
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
||||||
|
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
||||||
|
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
||||||
|
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
||||||
|
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
||||||
|
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
||||||
|
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
||||||
|
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
||||||
|
.m_ctrlport_req_wr (m_ctrlport_req_wr),
|
||||||
|
.m_ctrlport_req_rd (m_ctrlport_req_rd),
|
||||||
|
.m_ctrlport_req_addr (m_ctrlport_req_addr),
|
||||||
|
.m_ctrlport_req_data (m_ctrlport_req_data),
|
||||||
|
.m_ctrlport_req_byte_en (),
|
||||||
|
.m_ctrlport_req_has_time (),
|
||||||
|
.m_ctrlport_req_time (),
|
||||||
|
.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
|
||||||
|
.m_ctrlport_resp_status (2'b0),
|
||||||
|
.m_ctrlport_resp_data (m_ctrlport_resp_data),
|
||||||
|
.s_ctrlport_req_wr (1'b0),
|
||||||
|
.s_ctrlport_req_rd (1'b0),
|
||||||
|
.s_ctrlport_req_addr (20'b0),
|
||||||
|
.s_ctrlport_req_portid (10'b0),
|
||||||
|
.s_ctrlport_req_rem_epid (16'b0),
|
||||||
|
.s_ctrlport_req_rem_portid (10'b0),
|
||||||
|
.s_ctrlport_req_data (32'b0),
|
||||||
|
.s_ctrlport_req_byte_en (4'hF),
|
||||||
|
.s_ctrlport_req_has_time (1'b0),
|
||||||
|
.s_ctrlport_req_time (64'b0),
|
||||||
|
.s_ctrlport_resp_ack (),
|
||||||
|
.s_ctrlport_resp_status (),
|
||||||
|
.s_ctrlport_resp_data ()
|
||||||
|
);
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Data Path
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
genvar i;
|
||||||
|
|
||||||
|
assign axis_data_clk = rfnoc_chdr_clk;
|
||||||
|
assign axis_data_rst = rfnoc_chdr_rst;
|
||||||
|
|
||||||
|
//---------------------
|
||||||
|
// Input Data Paths
|
||||||
|
//---------------------
|
||||||
|
|
||||||
|
chdr_to_axis_pyld_ctxt #(
|
||||||
|
.CHDR_W (CHDR_W),
|
||||||
|
.ITEM_W (32),
|
||||||
|
.NIPC (2),
|
||||||
|
.SYNC_CLKS (1),
|
||||||
|
.CONTEXT_FIFO_SIZE ($clog2(2)),
|
||||||
|
.PAYLOAD_FIFO_SIZE ($clog2(2)),
|
||||||
|
.CONTEXT_PREFETCH_EN (1)
|
||||||
|
) chdr_to_axis_pyld_ctxt_in_sink (
|
||||||
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
|
.axis_data_clk (axis_data_clk),
|
||||||
|
.axis_data_rst (axis_data_rst),
|
||||||
|
.s_axis_chdr_tdata (s_rfnoc_chdr_tdata[(0)*CHDR_W+:CHDR_W]),
|
||||||
|
.s_axis_chdr_tlast (s_rfnoc_chdr_tlast[0]),
|
||||||
|
.s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[0]),
|
||||||
|
.s_axis_chdr_tready (s_rfnoc_chdr_tready[0]),
|
||||||
|
.m_axis_payload_tdata (m_sink_payload_tdata),
|
||||||
|
.m_axis_payload_tkeep (m_sink_payload_tkeep),
|
||||||
|
.m_axis_payload_tlast (m_sink_payload_tlast),
|
||||||
|
.m_axis_payload_tvalid (m_sink_payload_tvalid),
|
||||||
|
.m_axis_payload_tready (m_sink_payload_tready),
|
||||||
|
.m_axis_context_tdata (m_sink_context_tdata),
|
||||||
|
.m_axis_context_tuser (m_sink_context_tuser),
|
||||||
|
.m_axis_context_tlast (m_sink_context_tlast),
|
||||||
|
.m_axis_context_tvalid (m_sink_context_tvalid),
|
||||||
|
.m_axis_context_tready (m_sink_context_tready),
|
||||||
|
.flush_en (data_i_flush_en),
|
||||||
|
.flush_timeout (data_i_flush_timeout),
|
||||||
|
.flush_active (data_i_flush_active[0]),
|
||||||
|
.flush_done (data_i_flush_done[0])
|
||||||
|
);
|
||||||
|
|
||||||
|
chdr_to_axis_pyld_ctxt #(
|
||||||
|
.CHDR_W (CHDR_W),
|
||||||
|
.ITEM_W (32),
|
||||||
|
.NIPC (2),
|
||||||
|
.SYNC_CLKS (1),
|
||||||
|
.CONTEXT_FIFO_SIZE ($clog2(2)),
|
||||||
|
.PAYLOAD_FIFO_SIZE ($clog2(2)),
|
||||||
|
.CONTEXT_PREFETCH_EN (1)
|
||||||
|
) chdr_to_axis_pyld_ctxt_in_loop (
|
||||||
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
|
.axis_data_clk (axis_data_clk),
|
||||||
|
.axis_data_rst (axis_data_rst),
|
||||||
|
.s_axis_chdr_tdata (s_rfnoc_chdr_tdata[(1)*CHDR_W+:CHDR_W]),
|
||||||
|
.s_axis_chdr_tlast (s_rfnoc_chdr_tlast[1]),
|
||||||
|
.s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[1]),
|
||||||
|
.s_axis_chdr_tready (s_rfnoc_chdr_tready[1]),
|
||||||
|
.m_axis_payload_tdata (m_loop_payload_tdata),
|
||||||
|
.m_axis_payload_tkeep (m_loop_payload_tkeep),
|
||||||
|
.m_axis_payload_tlast (m_loop_payload_tlast),
|
||||||
|
.m_axis_payload_tvalid (m_loop_payload_tvalid),
|
||||||
|
.m_axis_payload_tready (m_loop_payload_tready),
|
||||||
|
.m_axis_context_tdata (m_loop_context_tdata),
|
||||||
|
.m_axis_context_tuser (m_loop_context_tuser),
|
||||||
|
.m_axis_context_tlast (m_loop_context_tlast),
|
||||||
|
.m_axis_context_tvalid (m_loop_context_tvalid),
|
||||||
|
.m_axis_context_tready (m_loop_context_tready),
|
||||||
|
.flush_en (data_i_flush_en),
|
||||||
|
.flush_timeout (data_i_flush_timeout),
|
||||||
|
.flush_active (data_i_flush_active[1]),
|
||||||
|
.flush_done (data_i_flush_done[1])
|
||||||
|
);
|
||||||
|
|
||||||
|
//---------------------
|
||||||
|
// Output Data Paths
|
||||||
|
//---------------------
|
||||||
|
|
||||||
|
axis_pyld_ctxt_to_chdr #(
|
||||||
|
.CHDR_W (CHDR_W),
|
||||||
|
.ITEM_W (32),
|
||||||
|
.NIPC (2),
|
||||||
|
.SYNC_CLKS (1),
|
||||||
|
.CONTEXT_FIFO_SIZE ($clog2(2)),
|
||||||
|
.PAYLOAD_FIFO_SIZE ($clog2(2)),
|
||||||
|
.MTU (MTU),
|
||||||
|
.CONTEXT_PREFETCH_EN (1)
|
||||||
|
) axis_pyld_ctxt_to_chdr_out_source (
|
||||||
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
|
.axis_data_clk (axis_data_clk),
|
||||||
|
.axis_data_rst (axis_data_rst),
|
||||||
|
.m_axis_chdr_tdata (m_rfnoc_chdr_tdata[(0)*CHDR_W+:CHDR_W]),
|
||||||
|
.m_axis_chdr_tlast (m_rfnoc_chdr_tlast[0]),
|
||||||
|
.m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[0]),
|
||||||
|
.m_axis_chdr_tready (m_rfnoc_chdr_tready[0]),
|
||||||
|
.s_axis_payload_tdata (s_source_payload_tdata),
|
||||||
|
.s_axis_payload_tkeep (s_source_payload_tkeep),
|
||||||
|
.s_axis_payload_tlast (s_source_payload_tlast),
|
||||||
|
.s_axis_payload_tvalid (s_source_payload_tvalid),
|
||||||
|
.s_axis_payload_tready (s_source_payload_tready),
|
||||||
|
.s_axis_context_tdata (s_source_context_tdata),
|
||||||
|
.s_axis_context_tuser (s_source_context_tuser),
|
||||||
|
.s_axis_context_tlast (s_source_context_tlast),
|
||||||
|
.s_axis_context_tvalid (s_source_context_tvalid),
|
||||||
|
.s_axis_context_tready (s_source_context_tready),
|
||||||
|
.framer_errors (),
|
||||||
|
.flush_en (data_o_flush_en),
|
||||||
|
.flush_timeout (data_o_flush_timeout),
|
||||||
|
.flush_active (data_o_flush_active[0]),
|
||||||
|
.flush_done (data_o_flush_done[0])
|
||||||
|
);
|
||||||
|
|
||||||
|
axis_pyld_ctxt_to_chdr #(
|
||||||
|
.CHDR_W (CHDR_W),
|
||||||
|
.ITEM_W (32),
|
||||||
|
.NIPC (2),
|
||||||
|
.SYNC_CLKS (1),
|
||||||
|
.CONTEXT_FIFO_SIZE ($clog2(2)),
|
||||||
|
.PAYLOAD_FIFO_SIZE ($clog2(2)),
|
||||||
|
.MTU (MTU),
|
||||||
|
.CONTEXT_PREFETCH_EN (1)
|
||||||
|
) axis_pyld_ctxt_to_chdr_out_loop (
|
||||||
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
|
.axis_data_clk (axis_data_clk),
|
||||||
|
.axis_data_rst (axis_data_rst),
|
||||||
|
.m_axis_chdr_tdata (m_rfnoc_chdr_tdata[(1)*CHDR_W+:CHDR_W]),
|
||||||
|
.m_axis_chdr_tlast (m_rfnoc_chdr_tlast[1]),
|
||||||
|
.m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[1]),
|
||||||
|
.m_axis_chdr_tready (m_rfnoc_chdr_tready[1]),
|
||||||
|
.s_axis_payload_tdata (s_loop_payload_tdata),
|
||||||
|
.s_axis_payload_tkeep (s_loop_payload_tkeep),
|
||||||
|
.s_axis_payload_tlast (s_loop_payload_tlast),
|
||||||
|
.s_axis_payload_tvalid (s_loop_payload_tvalid),
|
||||||
|
.s_axis_payload_tready (s_loop_payload_tready),
|
||||||
|
.s_axis_context_tdata (s_loop_context_tdata),
|
||||||
|
.s_axis_context_tuser (s_loop_context_tuser),
|
||||||
|
.s_axis_context_tlast (s_loop_context_tlast),
|
||||||
|
.s_axis_context_tvalid (s_loop_context_tvalid),
|
||||||
|
.s_axis_context_tready (s_loop_context_tready),
|
||||||
|
.framer_errors (),
|
||||||
|
.flush_en (data_o_flush_en),
|
||||||
|
.flush_timeout (data_o_flush_timeout),
|
||||||
|
.flush_active (data_o_flush_active[1]),
|
||||||
|
.flush_done (data_o_flush_done[1])
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule // noc_shell_null_src_sink
|
||||||
|
|
||||||
|
|
||||||
|
`default_nettype wire
|
||||||
@@ -64,7 +64,6 @@ module rfnoc_block_null_src_sink #(
|
|||||||
localparam [19:0] REG_LOOP_PKT_CNT_HI = 20'h3C;
|
localparam [19:0] REG_LOOP_PKT_CNT_HI = 20'h3C;
|
||||||
|
|
||||||
wire rfnoc_chdr_rst;
|
wire rfnoc_chdr_rst;
|
||||||
wire rfnoc_ctrl_rst;
|
|
||||||
|
|
||||||
wire ctrlport_req_wr;
|
wire ctrlport_req_wr;
|
||||||
wire ctrlport_req_rd;
|
wire ctrlport_req_rd;
|
||||||
@@ -73,99 +72,97 @@ module rfnoc_block_null_src_sink #(
|
|||||||
reg ctrlport_resp_ack;
|
reg ctrlport_resp_ack;
|
||||||
reg [31:0] ctrlport_resp_data;
|
reg [31:0] ctrlport_resp_data;
|
||||||
|
|
||||||
wire [(32*NIPC)-1:0] src_pyld_tdata , snk_pyld_tdata , loop_pyld_tdata ;
|
wire [(32*NIPC)-1:0] src_pyld_tdata , loop_pyld_tdata ;
|
||||||
wire [NIPC-1:0] src_pyld_tkeep , snk_pyld_tkeep , loop_pyld_tkeep ;
|
wire [NIPC-1:0] src_pyld_tkeep , loop_pyld_tkeep ;
|
||||||
wire src_pyld_tlast , snk_pyld_tlast , loop_pyld_tlast ;
|
wire src_pyld_tlast , snk_pyld_tlast , loop_pyld_tlast ;
|
||||||
wire src_pyld_tvalid, snk_pyld_tvalid, loop_pyld_tvalid;
|
wire src_pyld_tvalid, snk_pyld_tvalid, loop_pyld_tvalid;
|
||||||
wire src_pyld_tready, snk_pyld_tready, loop_pyld_tready;
|
wire src_pyld_tready, snk_pyld_tready, loop_pyld_tready;
|
||||||
|
|
||||||
wire [CHDR_W-1:0] src_ctxt_tdata , snk_ctxt_tdata , loop_ctxt_tdata ;
|
wire [CHDR_W-1:0] src_ctxt_tdata , loop_ctxt_tdata ;
|
||||||
wire [3:0] src_ctxt_tuser , snk_ctxt_tuser , loop_ctxt_tuser ;
|
wire [3:0] src_ctxt_tuser , loop_ctxt_tuser ;
|
||||||
wire src_ctxt_tlast , snk_ctxt_tlast , loop_ctxt_tlast ;
|
wire src_ctxt_tlast , loop_ctxt_tlast ;
|
||||||
wire src_ctxt_tvalid, snk_ctxt_tvalid, loop_ctxt_tvalid;
|
wire src_ctxt_tvalid, loop_ctxt_tvalid;
|
||||||
wire src_ctxt_tready, snk_ctxt_tready, loop_ctxt_tready;
|
wire src_ctxt_tready, snk_ctxt_tready, loop_ctxt_tready;
|
||||||
|
|
||||||
// NoC Shell
|
// NoC Shell
|
||||||
// ---------------------------
|
// ---------------------------
|
||||||
noc_shell_generic_ctrlport_pyld_chdr #(
|
noc_shell_null_src_sink #(
|
||||||
.NOC_ID (32'h0000_0001),
|
.THIS_PORTID (THIS_PORTID),
|
||||||
.THIS_PORTID (THIS_PORTID),
|
.CHDR_W (CHDR_W),
|
||||||
.CHDR_W (CHDR_W),
|
.MTU (MTU)
|
||||||
.CTRL_FIFOSIZE (5),
|
) noc_shell_null_src_sink_i (
|
||||||
.CTRLPORT_SLV_EN (0),
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||||
.NUM_DATA_I (2),
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
.NUM_DATA_O (2),
|
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
||||||
.ITEM_W (32),
|
.rfnoc_ctrl_rst (),
|
||||||
.NIPC (NIPC),
|
.rfnoc_core_config (rfnoc_core_config),
|
||||||
.MTU (MTU),
|
.rfnoc_core_status (rfnoc_core_status),
|
||||||
.CTXT_FIFOSIZE (1),
|
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
|
||||||
.PYLD_FIFOSIZE (1)
|
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
|
||||||
) noc_shell_i (
|
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
|
||||||
.rfnoc_chdr_clk (rfnoc_chdr_clk ),
|
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
|
||||||
.rfnoc_chdr_rst (rfnoc_chdr_rst ),
|
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
|
||||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
|
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
|
||||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
|
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
|
||||||
.rfnoc_core_config (rfnoc_core_config ),
|
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
|
||||||
.rfnoc_core_status (rfnoc_core_status ),
|
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
||||||
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata ),
|
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
||||||
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast ),
|
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
||||||
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid ),
|
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
||||||
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready ),
|
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
||||||
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata ),
|
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
||||||
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast ),
|
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
||||||
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid ),
|
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
||||||
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready ),
|
.ctrlport_clk (),
|
||||||
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata ),
|
.ctrlport_rst (),
|
||||||
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast ),
|
.m_ctrlport_req_wr (ctrlport_req_wr),
|
||||||
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid ),
|
.m_ctrlport_req_rd (ctrlport_req_rd),
|
||||||
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready ),
|
.m_ctrlport_req_addr (ctrlport_req_addr),
|
||||||
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata ),
|
.m_ctrlport_req_data (ctrlport_req_data),
|
||||||
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast ),
|
.m_ctrlport_resp_ack (ctrlport_resp_ack),
|
||||||
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid ),
|
.m_ctrlport_resp_data (ctrlport_resp_data),
|
||||||
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready ),
|
.axis_data_clk (),
|
||||||
.m_ctrlport_req_wr (ctrlport_req_wr ),
|
.axis_data_rst (),
|
||||||
.m_ctrlport_req_rd (ctrlport_req_rd ),
|
.m_sink_payload_tdata (), // Sink data is dropped and not used
|
||||||
.m_ctrlport_req_addr (ctrlport_req_addr ),
|
.m_sink_payload_tkeep (),
|
||||||
.m_ctrlport_req_data (ctrlport_req_data ),
|
.m_sink_payload_tlast (snk_pyld_tlast),
|
||||||
.m_ctrlport_req_byte_en ( ),
|
.m_sink_payload_tvalid (snk_pyld_tvalid),
|
||||||
.m_ctrlport_req_has_time ( ),
|
.m_sink_payload_tready (snk_pyld_tready),
|
||||||
.m_ctrlport_req_time ( ),
|
.m_sink_context_tdata (), // Sink context is dropped and not used
|
||||||
.m_ctrlport_resp_ack (ctrlport_resp_ack ),
|
.m_sink_context_tuser (),
|
||||||
.m_ctrlport_resp_status (2'd0 ),
|
.m_sink_context_tlast (),
|
||||||
.m_ctrlport_resp_data (ctrlport_resp_data ),
|
.m_sink_context_tvalid (),
|
||||||
.s_ctrlport_req_wr ('h0 ),
|
.m_sink_context_tready (snk_ctxt_tready),
|
||||||
.s_ctrlport_req_rd ('h0 ),
|
.m_loop_payload_tdata (loop_pyld_tdata),
|
||||||
.s_ctrlport_req_addr ('h0 ),
|
.m_loop_payload_tkeep (loop_pyld_tkeep),
|
||||||
.s_ctrlport_req_portid ('h0 ),
|
.m_loop_payload_tlast (loop_pyld_tlast),
|
||||||
.s_ctrlport_req_rem_epid ('h0 ),
|
.m_loop_payload_tvalid (loop_pyld_tvalid),
|
||||||
.s_ctrlport_req_rem_portid('h0 ),
|
.m_loop_payload_tready (loop_pyld_tready),
|
||||||
.s_ctrlport_req_data ('h0 ),
|
.m_loop_context_tdata (loop_ctxt_tdata),
|
||||||
.s_ctrlport_req_byte_en ('h0 ),
|
.m_loop_context_tuser (loop_ctxt_tuser),
|
||||||
.s_ctrlport_req_has_time ('h0 ),
|
.m_loop_context_tlast (loop_ctxt_tlast),
|
||||||
.s_ctrlport_req_time ('h0 ),
|
.m_loop_context_tvalid (loop_ctxt_tvalid),
|
||||||
.s_ctrlport_resp_ack ( ),
|
.m_loop_context_tready (loop_ctxt_tready),
|
||||||
.s_ctrlport_resp_status ( ),
|
.s_source_payload_tdata (src_pyld_tdata),
|
||||||
.s_ctrlport_resp_data ( ),
|
.s_source_payload_tkeep (src_pyld_tkeep),
|
||||||
.m_axis_payload_tdata ({loop_pyld_tdata , snk_pyld_tdata }),
|
.s_source_payload_tlast (src_pyld_tlast),
|
||||||
.m_axis_payload_tkeep ({loop_pyld_tkeep , snk_pyld_tkeep }),
|
.s_source_payload_tvalid (src_pyld_tvalid),
|
||||||
.m_axis_payload_tlast ({loop_pyld_tlast , snk_pyld_tlast }),
|
.s_source_payload_tready (src_pyld_tready),
|
||||||
.m_axis_payload_tvalid ({loop_pyld_tvalid, snk_pyld_tvalid}),
|
.s_source_context_tdata (src_ctxt_tdata),
|
||||||
.m_axis_payload_tready ({loop_pyld_tready, snk_pyld_tready}),
|
.s_source_context_tuser (src_ctxt_tuser),
|
||||||
.m_axis_context_tdata ({loop_ctxt_tdata , snk_ctxt_tdata }),
|
.s_source_context_tlast (src_ctxt_tlast),
|
||||||
.m_axis_context_tuser ({loop_ctxt_tuser , snk_ctxt_tuser }),
|
.s_source_context_tvalid (src_ctxt_tvalid),
|
||||||
.m_axis_context_tlast ({loop_ctxt_tlast , snk_ctxt_tlast }),
|
.s_source_context_tready (src_ctxt_tready),
|
||||||
.m_axis_context_tvalid ({loop_ctxt_tvalid, snk_ctxt_tvalid}),
|
.s_loop_payload_tdata (loop_pyld_tdata),
|
||||||
.m_axis_context_tready ({loop_ctxt_tready, snk_ctxt_tready}),
|
.s_loop_payload_tkeep (loop_pyld_tkeep),
|
||||||
.s_axis_payload_tdata ({loop_pyld_tdata , src_pyld_tdata }),
|
.s_loop_payload_tlast (loop_pyld_tlast),
|
||||||
.s_axis_payload_tkeep ({loop_pyld_tkeep , src_pyld_tkeep }),
|
.s_loop_payload_tvalid (loop_pyld_tvalid),
|
||||||
.s_axis_payload_tlast ({loop_pyld_tlast , src_pyld_tlast }),
|
.s_loop_payload_tready (loop_pyld_tready),
|
||||||
.s_axis_payload_tvalid ({loop_pyld_tvalid, src_pyld_tvalid}),
|
.s_loop_context_tdata (loop_ctxt_tdata),
|
||||||
.s_axis_payload_tready ({loop_pyld_tready, src_pyld_tready}),
|
.s_loop_context_tuser (loop_ctxt_tuser),
|
||||||
.s_axis_context_tdata ({loop_ctxt_tdata , src_ctxt_tdata }),
|
.s_loop_context_tlast (loop_ctxt_tlast),
|
||||||
.s_axis_context_tuser ({loop_ctxt_tuser , src_ctxt_tuser }),
|
.s_loop_context_tvalid (loop_ctxt_tvalid),
|
||||||
.s_axis_context_tlast ({loop_ctxt_tlast , src_ctxt_tlast }),
|
.s_loop_context_tready (loop_ctxt_tready)
|
||||||
.s_axis_context_tvalid ({loop_ctxt_tvalid, src_ctxt_tvalid}),
|
|
||||||
.s_axis_context_tready ({loop_ctxt_tready, src_ctxt_tready})
|
|
||||||
);
|
);
|
||||||
|
|
||||||
// Packet Counters
|
// Packet Counters
|
||||||
|
|||||||
@@ -20,6 +20,7 @@ module rfnoc_block_null_src_sink_tb;
|
|||||||
import PkgRfnocItemUtils::*;
|
import PkgRfnocItemUtils::*;
|
||||||
|
|
||||||
// Parameters
|
// Parameters
|
||||||
|
localparam NOC_ID = 32'h0000_0001;
|
||||||
localparam [9:0] THIS_PORTID = 10'h17;
|
localparam [9:0] THIS_PORTID = 10'h17;
|
||||||
localparam [15:0] THIS_EPID = 16'hDEAD;
|
localparam [15:0] THIS_EPID = 16'hDEAD;
|
||||||
localparam int CHDR_W = 64;
|
localparam int CHDR_W = 64;
|
||||||
@@ -87,7 +88,7 @@ module rfnoc_block_null_src_sink_tb;
|
|||||||
// Shared Variables
|
// Shared Variables
|
||||||
// ----------------------------------------
|
// ----------------------------------------
|
||||||
timeout_t timeout;
|
timeout_t timeout;
|
||||||
ctrl_word_t rvalue = 0;
|
ctrl_word_t rvalue;
|
||||||
|
|
||||||
// Initialize
|
// Initialize
|
||||||
// ----------------------------------------
|
// ----------------------------------------
|
||||||
@@ -118,7 +119,7 @@ module rfnoc_block_null_src_sink_tb;
|
|||||||
begin
|
begin
|
||||||
test.start_timeout(timeout, 1us, "Waiting for block info response");
|
test.start_timeout(timeout, 1us, "Waiting for block info response");
|
||||||
// Get static block info and validate it
|
// Get static block info and validate it
|
||||||
`ASSERT_ERROR(blk_ctrl.get_noc_id() == 1, "Incorrect noc_id Value");
|
`ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect noc_id Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == 2, "Incorrect num_data_i Value");
|
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == 2, "Incorrect num_data_i Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == 2, "Incorrect num_data_o Value");
|
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == 2, "Incorrect num_data_o Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_ctrl_fifosize() == 5, "Incorrect ctrl_fifosize Value");
|
`ASSERT_ERROR(blk_ctrl.get_ctrl_fifosize() == 5, "Incorrect ctrl_fifosize Value");
|
||||||
|
|||||||
@@ -1,131 +1,131 @@
|
|||||||
//
|
//
|
||||||
// Copyright 2019 Ettus Research, A National Instruments Company
|
// Copyright 2019 Ettus Research, A National Instruments Brand
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||||
//
|
//
|
||||||
// Module: noc_shell_radio
|
// Module: noc_shell_radio
|
||||||
//
|
//
|
||||||
// Description: A NoC Shell for RFNoC. This should eventually be replaced
|
// Description:
|
||||||
// by an auto-generated NoC Shell.
|
//
|
||||||
|
// This is a tool-generated NoC-shell for the radio block.
|
||||||
|
// See the RFNoC specification for more information about NoC shells.
|
||||||
|
//
|
||||||
|
// Parameters:
|
||||||
|
//
|
||||||
|
// THIS_PORTID : Control crossbar port to which this block is connected
|
||||||
|
// CHDR_W : AXIS-CHDR data bus width
|
||||||
|
// MTU : Maximum transmission unit (i.e., maximum packet size in
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
|
||||||
module noc_shell_radio #(
|
module noc_shell_radio #(
|
||||||
parameter [31:0] NOC_ID = 32'h0,
|
parameter [9:0] THIS_PORTID = 10'd0,
|
||||||
parameter [ 9:0] THIS_PORTID = 10'd0,
|
parameter CHDR_W = 64,
|
||||||
parameter CHDR_W = 64,
|
parameter [5:0] MTU = 10,
|
||||||
parameter [ 0:0] CTRLPORT_SLV_EN = 1,
|
parameter NUM_PORTS = 2,
|
||||||
parameter [ 0:0] CTRLPORT_MST_EN = 1,
|
parameter NIPC = 1,
|
||||||
parameter [ 5:0] CTRL_FIFO_SIZE = 9,
|
parameter ITEM_W = 32
|
||||||
parameter [ 5:0] NUM_DATA_I = 1,
|
) (
|
||||||
parameter [ 5:0] NUM_DATA_O = 1,
|
//---------------------
|
||||||
parameter ITEM_W = 32,
|
|
||||||
parameter NIPC = 2,
|
|
||||||
parameter PYLD_FIFO_SIZE = 10,
|
|
||||||
parameter MTU = 10
|
|
||||||
)(
|
|
||||||
//---------------------------------------------------------------------------
|
|
||||||
// Framework Interface
|
// Framework Interface
|
||||||
//---------------------------------------------------------------------------
|
//---------------------
|
||||||
|
|
||||||
|
// RFNoC Framework Clocks
|
||||||
|
input wire rfnoc_chdr_clk,
|
||||||
|
input wire rfnoc_ctrl_clk,
|
||||||
|
input wire radio_clk,
|
||||||
|
|
||||||
|
// NoC Shell Generated Resets
|
||||||
|
output wire rfnoc_chdr_rst,
|
||||||
|
output wire rfnoc_ctrl_rst,
|
||||||
|
output wire radio_rst,
|
||||||
|
|
||||||
// RFNoC Framework Clocks and Resets
|
|
||||||
input wire rfnoc_chdr_clk,
|
|
||||||
output wire rfnoc_chdr_rst,
|
|
||||||
input wire rfnoc_ctrl_clk,
|
|
||||||
output wire rfnoc_ctrl_rst,
|
|
||||||
// RFNoC Backend Interface
|
// RFNoC Backend Interface
|
||||||
input wire [ 511:0] rfnoc_core_config,
|
input wire [511:0] rfnoc_core_config,
|
||||||
output wire [ 511:0] rfnoc_core_status,
|
output wire [511:0] rfnoc_core_status,
|
||||||
// CHDR Input Ports (from framework)
|
|
||||||
input wire [(CHDR_W*NUM_DATA_I)-1:0] s_rfnoc_chdr_tdata,
|
|
||||||
input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tlast,
|
|
||||||
input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tvalid,
|
|
||||||
output wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tready,
|
|
||||||
// CHDR Output Ports (to framework)
|
|
||||||
output wire [(CHDR_W*NUM_DATA_O)-1:0] m_rfnoc_chdr_tdata,
|
|
||||||
output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tlast,
|
|
||||||
output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tvalid,
|
|
||||||
input wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tready,
|
|
||||||
// AXIS-Ctrl Input Port (from framework)
|
|
||||||
input wire [ 31:0] s_rfnoc_ctrl_tdata,
|
|
||||||
input wire s_rfnoc_ctrl_tlast,
|
|
||||||
input wire s_rfnoc_ctrl_tvalid,
|
|
||||||
output wire s_rfnoc_ctrl_tready,
|
|
||||||
// AXIS-Ctrl Output Port (to framework)
|
|
||||||
output wire [ 31:0] m_rfnoc_ctrl_tdata,
|
|
||||||
output wire m_rfnoc_ctrl_tlast,
|
|
||||||
output wire m_rfnoc_ctrl_tvalid,
|
|
||||||
input wire m_rfnoc_ctrl_tready,
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
// AXIS-CHDR Input Ports (from framework)
|
||||||
// Client Control Port Interface
|
input wire [(0+NUM_PORTS)*CHDR_W-1:0] s_rfnoc_chdr_tdata,
|
||||||
//---------------------------------------------------------------------------
|
input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tlast,
|
||||||
|
input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tvalid,
|
||||||
|
output wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tready,
|
||||||
|
// AXIS-CHDR Output Ports (to framework)
|
||||||
|
output wire [(0+NUM_PORTS)*CHDR_W-1:0] m_rfnoc_chdr_tdata,
|
||||||
|
output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tlast,
|
||||||
|
output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tvalid,
|
||||||
|
input wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tready,
|
||||||
|
|
||||||
// Clock
|
// AXIS-Ctrl Control Input Port (from framework)
|
||||||
input wire ctrlport_clk,
|
input wire [31:0] s_rfnoc_ctrl_tdata,
|
||||||
input wire ctrlport_rst,
|
input wire s_rfnoc_ctrl_tlast,
|
||||||
// Master
|
input wire s_rfnoc_ctrl_tvalid,
|
||||||
output wire m_ctrlport_req_wr,
|
output wire s_rfnoc_ctrl_tready,
|
||||||
output wire m_ctrlport_req_rd,
|
// AXIS-Ctrl Control Output Port (to framework)
|
||||||
output wire [19:0] m_ctrlport_req_addr,
|
output wire [31:0] m_rfnoc_ctrl_tdata,
|
||||||
output wire [31:0] m_ctrlport_req_data,
|
output wire m_rfnoc_ctrl_tlast,
|
||||||
output wire [ 3:0] m_ctrlport_req_byte_en,
|
output wire m_rfnoc_ctrl_tvalid,
|
||||||
output wire m_ctrlport_req_has_time,
|
input wire m_rfnoc_ctrl_tready,
|
||||||
output wire [63:0] m_ctrlport_req_time,
|
|
||||||
input wire m_ctrlport_resp_ack,
|
|
||||||
input wire [ 1:0] m_ctrlport_resp_status,
|
|
||||||
input wire [31:0] m_ctrlport_resp_data,
|
|
||||||
// Slave
|
|
||||||
input wire s_ctrlport_req_wr,
|
|
||||||
input wire s_ctrlport_req_rd,
|
|
||||||
input wire [19:0] s_ctrlport_req_addr,
|
|
||||||
input wire [ 9:0] s_ctrlport_req_portid,
|
|
||||||
input wire [15:0] s_ctrlport_req_rem_epid,
|
|
||||||
input wire [ 9:0] s_ctrlport_req_rem_portid,
|
|
||||||
input wire [31:0] s_ctrlport_req_data,
|
|
||||||
input wire [ 3:0] s_ctrlport_req_byte_en,
|
|
||||||
input wire s_ctrlport_req_has_time,
|
|
||||||
input wire [63:0] s_ctrlport_req_time,
|
|
||||||
output wire s_ctrlport_resp_ack,
|
|
||||||
output wire [ 1:0] s_ctrlport_resp_status,
|
|
||||||
output wire [31:0] s_ctrlport_resp_data,
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------
|
||||||
// Client Data Interface
|
// Client Interface
|
||||||
//---------------------------------------------------------------------------
|
//---------------------
|
||||||
|
|
||||||
// Clock
|
// CtrlPort Clock and Reset
|
||||||
input wire axis_data_clk,
|
output wire ctrlport_clk,
|
||||||
input wire axis_data_rst,
|
output wire ctrlport_rst,
|
||||||
|
// CtrlPort Master
|
||||||
|
output wire m_ctrlport_req_wr,
|
||||||
|
output wire m_ctrlport_req_rd,
|
||||||
|
output wire [19:0] m_ctrlport_req_addr,
|
||||||
|
output wire [31:0] m_ctrlport_req_data,
|
||||||
|
output wire [3:0] m_ctrlport_req_byte_en,
|
||||||
|
output wire m_ctrlport_req_has_time,
|
||||||
|
output wire [63:0] m_ctrlport_req_time,
|
||||||
|
input wire m_ctrlport_resp_ack,
|
||||||
|
input wire [1:0] m_ctrlport_resp_status,
|
||||||
|
input wire [31:0] m_ctrlport_resp_data,
|
||||||
|
// CtrlPort Slave
|
||||||
|
input wire s_ctrlport_req_wr,
|
||||||
|
input wire s_ctrlport_req_rd,
|
||||||
|
input wire [19:0] s_ctrlport_req_addr,
|
||||||
|
input wire [9:0] s_ctrlport_req_portid,
|
||||||
|
input wire [15:0] s_ctrlport_req_rem_epid,
|
||||||
|
input wire [9:0] s_ctrlport_req_rem_portid,
|
||||||
|
input wire [31:0] s_ctrlport_req_data,
|
||||||
|
input wire [3:0] s_ctrlport_req_byte_en,
|
||||||
|
input wire s_ctrlport_req_has_time,
|
||||||
|
input wire [63:0] s_ctrlport_req_time,
|
||||||
|
output wire s_ctrlport_resp_ack,
|
||||||
|
output wire [1:0] s_ctrlport_resp_status,
|
||||||
|
output wire [31:0] s_ctrlport_resp_data,
|
||||||
|
|
||||||
// Output data stream (to user logic)
|
// AXI-Stream Data Clock and Reset
|
||||||
output wire [(NUM_DATA_I*ITEM_W*NIPC)-1:0] m_axis_tdata,
|
output wire axis_data_clk,
|
||||||
output wire [ (NUM_DATA_I*NIPC)-1:0] m_axis_tkeep,
|
output wire axis_data_rst,
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_tlast,
|
// Data Stream to User Logic: in
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_tvalid,
|
output wire [NUM_PORTS*ITEM_W*NIPC-1:0] m_in_axis_tdata,
|
||||||
input wire [ NUM_DATA_I-1:0] m_axis_tready,
|
output wire [NUM_PORTS*NIPC-1:0] m_in_axis_tkeep,
|
||||||
// Sideband information
|
output wire [NUM_PORTS-1:0] m_in_axis_tlast,
|
||||||
output wire [ (NUM_DATA_I*64)-1:0] m_axis_ttimestamp,
|
output wire [NUM_PORTS-1:0] m_in_axis_tvalid,
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_thas_time,
|
input wire [NUM_PORTS-1:0] m_in_axis_tready,
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_teov,
|
output wire [NUM_PORTS*64-1:0] m_in_axis_ttimestamp,
|
||||||
output wire [ NUM_DATA_I-1:0] m_axis_teob,
|
output wire [NUM_PORTS-1:0] m_in_axis_thas_time,
|
||||||
|
output wire [NUM_PORTS*16-1:0] m_in_axis_tlength,
|
||||||
// Input data stream (from user logic)
|
output wire [NUM_PORTS-1:0] m_in_axis_teov,
|
||||||
input wire [(NUM_DATA_O*ITEM_W*NIPC)-1:0] s_axis_tdata,
|
output wire [NUM_PORTS-1:0] m_in_axis_teob,
|
||||||
input wire [ (NUM_DATA_O*NIPC)-1:0] s_axis_tkeep,
|
// Data Stream to User Logic: out
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_tlast,
|
input wire [NUM_PORTS*ITEM_W*NIPC-1:0] s_out_axis_tdata,
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_tvalid,
|
input wire [NUM_PORTS*NIPC-1:0] s_out_axis_tkeep,
|
||||||
output wire [ NUM_DATA_O-1:0] s_axis_tready,
|
input wire [NUM_PORTS-1:0] s_out_axis_tlast,
|
||||||
// Sideband info (sampled on the first cycle of the packet)
|
input wire [NUM_PORTS-1:0] s_out_axis_tvalid,
|
||||||
input wire [ (NUM_DATA_O*64)-1:0] s_axis_ttimestamp,
|
output wire [NUM_PORTS-1:0] s_out_axis_tready,
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_thas_time,
|
input wire [NUM_PORTS*64-1:0] s_out_axis_ttimestamp,
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_teov,
|
input wire [NUM_PORTS-1:0] s_out_axis_thas_time,
|
||||||
input wire [ NUM_DATA_O-1:0] s_axis_teob
|
input wire [NUM_PORTS-1:0] s_out_axis_teov,
|
||||||
|
input wire [NUM_PORTS-1:0] s_out_axis_teob
|
||||||
);
|
);
|
||||||
|
|
||||||
localparam SNK_INFO_FIFO_SIZE = 4;
|
|
||||||
localparam SNK_PYLD_FIFO_SIZE = PYLD_FIFO_SIZE;
|
|
||||||
localparam SRC_INFO_FIFO_SIZE = 4;
|
|
||||||
localparam SRC_PYLD_FIFO_SIZE = MTU;
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// Backend Interface
|
// Backend Interface
|
||||||
@@ -141,18 +141,18 @@ module noc_shell_radio #(
|
|||||||
wire [63:0] data_o_flush_done;
|
wire [63:0] data_o_flush_done;
|
||||||
|
|
||||||
backend_iface #(
|
backend_iface #(
|
||||||
.NOC_ID (NOC_ID),
|
.NOC_ID (32'h12AD1000),
|
||||||
.NUM_DATA_I (NUM_DATA_I),
|
.NUM_DATA_I (0+NUM_PORTS),
|
||||||
.NUM_DATA_O (NUM_DATA_O),
|
.NUM_DATA_O (0+NUM_PORTS),
|
||||||
.CTRL_FIFOSIZE (CTRL_FIFO_SIZE),
|
.CTRL_FIFOSIZE ($clog2(512)),
|
||||||
.MTU (MTU)
|
.MTU (MTU)
|
||||||
) backend_iface_i (
|
) backend_iface_i (
|
||||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
||||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||||
.rfnoc_core_config (rfnoc_core_config),
|
.rfnoc_core_config (rfnoc_core_config),
|
||||||
.rfnoc_core_status (rfnoc_core_status),
|
.rfnoc_core_status (rfnoc_core_status),
|
||||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
|
||||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
|
||||||
.data_i_flush_en (data_i_flush_en),
|
.data_i_flush_en (data_i_flush_en),
|
||||||
.data_i_flush_timeout (data_i_flush_timeout),
|
.data_i_flush_timeout (data_i_flush_timeout),
|
||||||
.data_i_flush_active (data_i_flush_active),
|
.data_i_flush_active (data_i_flush_active),
|
||||||
@@ -163,52 +163,71 @@ module noc_shell_radio #(
|
|||||||
.data_o_flush_done (data_o_flush_done)
|
.data_o_flush_done (data_o_flush_done)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Reset Generation
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
wire radio_rst_pulse;
|
||||||
|
|
||||||
|
pulse_synchronizer #(.MODE ("POSEDGE")) pulse_synchronizer_radio (
|
||||||
|
.clk_a(rfnoc_chdr_clk), .rst_a(1'b0), .pulse_a (rfnoc_chdr_rst), .busy_a (),
|
||||||
|
.clk_b(radio_clk), .pulse_b (radio_rst_pulse)
|
||||||
|
);
|
||||||
|
|
||||||
|
pulse_stretch_min #(.LENGTH(32)) pulse_stretch_min_radio (
|
||||||
|
.clk(radio_clk), .rst(1'b0),
|
||||||
|
.pulse_in(radio_rst_pulse), .pulse_out(radio_rst)
|
||||||
|
);
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
// Control Path
|
// Control Path
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
assign ctrlport_clk = radio_clk;
|
||||||
|
assign ctrlport_rst = radio_rst;
|
||||||
|
|
||||||
ctrlport_endpoint #(
|
ctrlport_endpoint #(
|
||||||
.THIS_PORTID (THIS_PORTID ),
|
.THIS_PORTID (THIS_PORTID),
|
||||||
.SYNC_CLKS (0 ),
|
.SYNC_CLKS (0),
|
||||||
.AXIS_CTRL_MST_EN (CTRLPORT_SLV_EN),
|
.AXIS_CTRL_MST_EN (1),
|
||||||
.AXIS_CTRL_SLV_EN (CTRLPORT_MST_EN),
|
.AXIS_CTRL_SLV_EN (1),
|
||||||
.SLAVE_FIFO_SIZE (CTRL_FIFO_SIZE )
|
.SLAVE_FIFO_SIZE ($clog2(512))
|
||||||
) ctrlport_ep_i (
|
) ctrlport_endpoint_i (
|
||||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
||||||
.ctrlport_clk (ctrlport_clk ),
|
.ctrlport_clk (ctrlport_clk),
|
||||||
.ctrlport_rst (ctrlport_rst ),
|
.ctrlport_rst (ctrlport_rst),
|
||||||
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata ),
|
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
|
||||||
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast ),
|
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
|
||||||
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid ),
|
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
|
||||||
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready ),
|
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
|
||||||
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata ),
|
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
|
||||||
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast ),
|
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
||||||
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid ),
|
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
||||||
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready ),
|
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
||||||
.m_ctrlport_req_wr (m_ctrlport_req_wr ),
|
.m_ctrlport_req_wr (m_ctrlport_req_wr),
|
||||||
.m_ctrlport_req_rd (m_ctrlport_req_rd ),
|
.m_ctrlport_req_rd (m_ctrlport_req_rd),
|
||||||
.m_ctrlport_req_addr (m_ctrlport_req_addr ),
|
.m_ctrlport_req_addr (m_ctrlport_req_addr),
|
||||||
.m_ctrlport_req_data (m_ctrlport_req_data ),
|
.m_ctrlport_req_data (m_ctrlport_req_data),
|
||||||
.m_ctrlport_req_byte_en (m_ctrlport_req_byte_en ),
|
.m_ctrlport_req_byte_en (m_ctrlport_req_byte_en),
|
||||||
.m_ctrlport_req_has_time (m_ctrlport_req_has_time ),
|
.m_ctrlport_req_has_time (m_ctrlport_req_has_time),
|
||||||
.m_ctrlport_req_time (m_ctrlport_req_time ),
|
.m_ctrlport_req_time (m_ctrlport_req_time),
|
||||||
.m_ctrlport_resp_ack (m_ctrlport_resp_ack ),
|
.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
|
||||||
.m_ctrlport_resp_status (m_ctrlport_resp_status ),
|
.m_ctrlport_resp_status (m_ctrlport_resp_status),
|
||||||
.m_ctrlport_resp_data (m_ctrlport_resp_data ),
|
.m_ctrlport_resp_data (m_ctrlport_resp_data),
|
||||||
.s_ctrlport_req_wr (s_ctrlport_req_wr ),
|
.s_ctrlport_req_wr (s_ctrlport_req_wr),
|
||||||
.s_ctrlport_req_rd (s_ctrlport_req_rd ),
|
.s_ctrlport_req_rd (s_ctrlport_req_rd),
|
||||||
.s_ctrlport_req_addr (s_ctrlport_req_addr ),
|
.s_ctrlport_req_addr (s_ctrlport_req_addr),
|
||||||
.s_ctrlport_req_portid (s_ctrlport_req_portid ),
|
.s_ctrlport_req_portid (s_ctrlport_req_portid),
|
||||||
.s_ctrlport_req_rem_epid (s_ctrlport_req_rem_epid ),
|
.s_ctrlport_req_rem_epid (s_ctrlport_req_rem_epid),
|
||||||
.s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
|
.s_ctrlport_req_rem_portid (s_ctrlport_req_rem_portid),
|
||||||
.s_ctrlport_req_data (s_ctrlport_req_data ),
|
.s_ctrlport_req_data (s_ctrlport_req_data),
|
||||||
.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en ),
|
.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en),
|
||||||
.s_ctrlport_req_has_time (s_ctrlport_req_has_time ),
|
.s_ctrlport_req_has_time (s_ctrlport_req_has_time),
|
||||||
.s_ctrlport_req_time (s_ctrlport_req_time ),
|
.s_ctrlport_req_time (s_ctrlport_req_time),
|
||||||
.s_ctrlport_resp_ack (s_ctrlport_resp_ack ),
|
.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
|
||||||
.s_ctrlport_resp_status (s_ctrlport_resp_status ),
|
.s_ctrlport_resp_status (s_ctrlport_resp_status),
|
||||||
.s_ctrlport_resp_data (s_ctrlport_resp_data )
|
.s_ctrlport_resp_data (s_ctrlport_resp_data)
|
||||||
);
|
);
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@@ -216,75 +235,87 @@ module noc_shell_radio #(
|
|||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
genvar i;
|
genvar i;
|
||||||
generate
|
|
||||||
|
|
||||||
for (i = 0; i < NUM_DATA_I; i = i + 1) begin: chdr_to_data
|
assign axis_data_clk = radio_clk;
|
||||||
chdr_to_axis_data #(
|
assign axis_data_rst = radio_rst;
|
||||||
.CHDR_W (CHDR_W),
|
|
||||||
.ITEM_W (ITEM_W),
|
//---------------------
|
||||||
.NIPC (NIPC),
|
// Input Data Paths
|
||||||
.SYNC_CLKS (0),
|
//---------------------
|
||||||
.INFO_FIFO_SIZE (SNK_INFO_FIFO_SIZE),
|
|
||||||
.PYLD_FIFO_SIZE (SNK_PYLD_FIFO_SIZE)
|
|
||||||
) chdr_to_axis_data_i (
|
|
||||||
.axis_chdr_clk (rfnoc_chdr_clk),
|
|
||||||
.axis_chdr_rst (rfnoc_chdr_rst),
|
|
||||||
.axis_data_clk (axis_data_clk),
|
|
||||||
.axis_data_rst (axis_data_rst),
|
|
||||||
.s_axis_chdr_tdata (s_rfnoc_chdr_tdata [(i*CHDR_W)+:CHDR_W]),
|
|
||||||
.s_axis_chdr_tlast (s_rfnoc_chdr_tlast [i]),
|
|
||||||
.s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid [i]),
|
|
||||||
.s_axis_chdr_tready (s_rfnoc_chdr_tready [i]),
|
|
||||||
.m_axis_tdata (m_axis_tdata [i*ITEM_W*NIPC +: ITEM_W*NIPC]),
|
|
||||||
.m_axis_tkeep (m_axis_tkeep [i*NIPC +: NIPC]),
|
|
||||||
.m_axis_tlast (m_axis_tlast [i]),
|
|
||||||
.m_axis_tvalid (m_axis_tvalid [i]),
|
|
||||||
.m_axis_tready (m_axis_tready [i]),
|
|
||||||
.m_axis_ttimestamp (m_axis_ttimestamp [i*64 +: 64]),
|
|
||||||
.m_axis_thas_time (m_axis_thas_time [i]),
|
|
||||||
.m_axis_tlength (),
|
|
||||||
.m_axis_teov (m_axis_teov [i]),
|
|
||||||
.m_axis_teob (m_axis_teob [i]),
|
|
||||||
.flush_en (data_i_flush_en),
|
|
||||||
.flush_timeout (data_i_flush_timeout),
|
|
||||||
.flush_active (data_i_flush_active [i]),
|
|
||||||
.flush_done (data_i_flush_done [i])
|
|
||||||
);
|
|
||||||
end
|
|
||||||
|
|
||||||
for (i = 0; i < NUM_DATA_O; i = i + 1) begin: data_to_chdr
|
for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_input_in
|
||||||
axis_data_to_chdr #(
|
chdr_to_axis_data #(
|
||||||
.CHDR_W (CHDR_W),
|
.CHDR_W (CHDR_W),
|
||||||
.ITEM_W (ITEM_W),
|
.ITEM_W (ITEM_W),
|
||||||
.NIPC (NIPC),
|
.NIPC (NIPC),
|
||||||
.SYNC_CLKS (0),
|
.SYNC_CLKS (0),
|
||||||
.INFO_FIFO_SIZE (4),
|
.INFO_FIFO_SIZE ($clog2(32)),
|
||||||
.PYLD_FIFO_SIZE (SRC_INFO_FIFO_SIZE),
|
.PYLD_FIFO_SIZE ($clog2(MTU))
|
||||||
.MTU (SRC_PYLD_FIFO_SIZE)
|
) chdr_to_axis_data_in_in (
|
||||||
) axis_data_to_chdr_i (
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
.axis_chdr_clk (rfnoc_chdr_clk),
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
.axis_chdr_rst (rfnoc_chdr_rst),
|
.axis_data_clk (axis_data_clk),
|
||||||
.axis_data_clk (axis_data_clk),
|
.axis_data_rst (axis_data_rst),
|
||||||
.axis_data_rst (axis_data_rst),
|
.s_axis_chdr_tdata (s_rfnoc_chdr_tdata[((0+i)*CHDR_W)+:CHDR_W]),
|
||||||
.m_axis_chdr_tdata (m_rfnoc_chdr_tdata [i*CHDR_W +: CHDR_W]),
|
.s_axis_chdr_tlast (s_rfnoc_chdr_tlast[0+i]),
|
||||||
.m_axis_chdr_tlast (m_rfnoc_chdr_tlast [i]),
|
.s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[0+i]),
|
||||||
.m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid [i]),
|
.s_axis_chdr_tready (s_rfnoc_chdr_tready[0+i]),
|
||||||
.m_axis_chdr_tready (m_rfnoc_chdr_tready [i]),
|
.m_axis_tdata (m_in_axis_tdata[(ITEM_W*NIPC)*i+:(ITEM_W*NIPC)]),
|
||||||
.s_axis_tdata (s_axis_tdata [i*ITEM_W*NIPC +: ITEM_W*NIPC]),
|
.m_axis_tkeep (m_in_axis_tkeep[NIPC*i+:NIPC]),
|
||||||
.s_axis_tkeep (s_axis_tkeep [i*NIPC +: NIPC]),
|
.m_axis_tlast (m_in_axis_tlast[i]),
|
||||||
.s_axis_tlast (s_axis_tlast [i]),
|
.m_axis_tvalid (m_in_axis_tvalid[i]),
|
||||||
.s_axis_tvalid (s_axis_tvalid [i]),
|
.m_axis_tready (m_in_axis_tready[i]),
|
||||||
.s_axis_tready (s_axis_tready [i]),
|
.m_axis_ttimestamp (m_in_axis_ttimestamp[64*i+:64]),
|
||||||
.s_axis_ttimestamp (s_axis_ttimestamp [i*64 +: 64]),
|
.m_axis_thas_time (m_in_axis_thas_time[i]),
|
||||||
.s_axis_thas_time (s_axis_thas_time [i]),
|
.m_axis_tlength (m_in_axis_tlength[i*16+:16]),
|
||||||
.s_axis_teov (s_axis_teov [i]),
|
.m_axis_teov (m_in_axis_teov[i]),
|
||||||
.s_axis_teob (s_axis_teob [i]),
|
.m_axis_teob (m_in_axis_teob[i]),
|
||||||
.flush_en (data_o_flush_en),
|
.flush_en (data_i_flush_en),
|
||||||
.flush_timeout (data_o_flush_timeout),
|
.flush_timeout (data_i_flush_timeout),
|
||||||
.flush_active (data_o_flush_active [i]),
|
.flush_active (data_i_flush_active[0+i]),
|
||||||
.flush_done (data_o_flush_done [i])
|
.flush_done (data_i_flush_done[0+i])
|
||||||
);
|
);
|
||||||
end
|
end
|
||||||
endgenerate
|
|
||||||
|
|
||||||
endmodule
|
//---------------------
|
||||||
|
// Output Data Paths
|
||||||
|
//---------------------
|
||||||
|
|
||||||
|
for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_output_out
|
||||||
|
axis_data_to_chdr #(
|
||||||
|
.CHDR_W (CHDR_W),
|
||||||
|
.ITEM_W (ITEM_W),
|
||||||
|
.NIPC (NIPC),
|
||||||
|
.SYNC_CLKS (0),
|
||||||
|
.INFO_FIFO_SIZE ($clog2(32)),
|
||||||
|
.PYLD_FIFO_SIZE ($clog2(MTU)),
|
||||||
|
.MTU (MTU)
|
||||||
|
) axis_data_to_chdr_out_out (
|
||||||
|
.axis_chdr_clk (rfnoc_chdr_clk),
|
||||||
|
.axis_chdr_rst (rfnoc_chdr_rst),
|
||||||
|
.axis_data_clk (axis_data_clk),
|
||||||
|
.axis_data_rst (axis_data_rst),
|
||||||
|
.m_axis_chdr_tdata (m_rfnoc_chdr_tdata[(0+i)*CHDR_W+:CHDR_W]),
|
||||||
|
.m_axis_chdr_tlast (m_rfnoc_chdr_tlast[0+i]),
|
||||||
|
.m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[0+i]),
|
||||||
|
.m_axis_chdr_tready (m_rfnoc_chdr_tready[0+i]),
|
||||||
|
.s_axis_tdata (s_out_axis_tdata[(ITEM_W*NIPC)*i+:(ITEM_W*NIPC)]),
|
||||||
|
.s_axis_tkeep (s_out_axis_tkeep[NIPC*i+:NIPC]),
|
||||||
|
.s_axis_tlast (s_out_axis_tlast[i]),
|
||||||
|
.s_axis_tvalid (s_out_axis_tvalid[i]),
|
||||||
|
.s_axis_tready (s_out_axis_tready[i]),
|
||||||
|
.s_axis_ttimestamp (s_out_axis_ttimestamp[64*i+:64]),
|
||||||
|
.s_axis_thas_time (s_out_axis_thas_time[i]),
|
||||||
|
.s_axis_teov (s_out_axis_teov[i]),
|
||||||
|
.s_axis_teob (s_out_axis_teob[i]),
|
||||||
|
.flush_en (data_o_flush_en),
|
||||||
|
.flush_timeout (data_o_flush_timeout),
|
||||||
|
.flush_active (data_o_flush_active[0+i]),
|
||||||
|
.flush_done (data_o_flush_done[0+i])
|
||||||
|
);
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule // noc_shell_radio
|
||||||
|
|
||||||
|
|
||||||
|
`default_nettype wire
|
||||||
|
|||||||
@@ -16,8 +16,6 @@
|
|||||||
// NUM_PORTS : Number of radio channels (RX/TX pairs)
|
// NUM_PORTS : Number of radio channels (RX/TX pairs)
|
||||||
// MTU : Maximum transmission unit (i.e., maximum packet size)
|
// MTU : Maximum transmission unit (i.e., maximum packet size)
|
||||||
// in CHDR words is 2**MTU.
|
// in CHDR words is 2**MTU.
|
||||||
// CTRL_FIFO_SIZE : Size of the Control Port slave FIFO. This affects the
|
|
||||||
// number of outstanding commands that can be pending.
|
|
||||||
// PERIPH_BASE_ADDR : CTRL port peripheral window base address
|
// PERIPH_BASE_ADDR : CTRL port peripheral window base address
|
||||||
// PERIPH_ADDR_W : CTRL port peripheral address space = 2**PERIPH_ADDR_W
|
// PERIPH_ADDR_W : CTRL port peripheral address space = 2**PERIPH_ADDR_W
|
||||||
//
|
//
|
||||||
@@ -30,7 +28,6 @@ module rfnoc_block_radio #(
|
|||||||
parameter ITEM_W = 32,
|
parameter ITEM_W = 32,
|
||||||
parameter NUM_PORTS = 2,
|
parameter NUM_PORTS = 2,
|
||||||
parameter MTU = 10,
|
parameter MTU = 10,
|
||||||
parameter CTRL_FIFO_SIZE = 9,
|
|
||||||
parameter PERIPH_BASE_ADDR = 20'h80000,
|
parameter PERIPH_BASE_ADDR = 20'h80000,
|
||||||
parameter PERIPH_ADDR_W = 19
|
parameter PERIPH_ADDR_W = 19
|
||||||
) (
|
) (
|
||||||
@@ -115,7 +112,6 @@ module rfnoc_block_radio #(
|
|||||||
`include "rfnoc_block_radio_regs.vh"
|
`include "rfnoc_block_radio_regs.vh"
|
||||||
`include "../../core/rfnoc_axis_ctrl_utils.vh"
|
`include "../../core/rfnoc_axis_ctrl_utils.vh"
|
||||||
|
|
||||||
localparam NOC_ID = 32'h12AD1000;
|
|
||||||
localparam RADIO_W = NIPC*ITEM_W;
|
localparam RADIO_W = NIPC*ITEM_W;
|
||||||
|
|
||||||
|
|
||||||
@@ -144,8 +140,10 @@ module rfnoc_block_radio #(
|
|||||||
wire ctrlport_reg_has_time;
|
wire ctrlport_reg_has_time;
|
||||||
wire [63:0] ctrlport_reg_time;
|
wire [63:0] ctrlport_reg_time;
|
||||||
wire [31:0] ctrlport_reg_req_data;
|
wire [31:0] ctrlport_reg_req_data;
|
||||||
|
wire [ 3:0] ctrlport_reg_req_byte_en;
|
||||||
wire [31:0] ctrlport_reg_resp_data;
|
wire [31:0] ctrlport_reg_resp_data;
|
||||||
wire ctrlport_reg_resp_ack;
|
wire ctrlport_reg_resp_ack;
|
||||||
|
wire [ 1:0] ctrlport_reg_resp_status;
|
||||||
|
|
||||||
// Control port signals used for error reporting (user logic masters to NoC shell)
|
// Control port signals used for error reporting (user logic masters to NoC shell)
|
||||||
wire ctrlport_err_req_wr;
|
wire ctrlport_err_req_wr;
|
||||||
@@ -163,27 +161,22 @@ module rfnoc_block_radio #(
|
|||||||
// NoC Shell
|
// NoC Shell
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
wire rfnoc_chdr_rst;
|
|
||||||
wire radio_rst;
|
wire radio_rst;
|
||||||
|
|
||||||
noc_shell_radio #(
|
noc_shell_radio #(
|
||||||
.NOC_ID (NOC_ID),
|
|
||||||
.THIS_PORTID (THIS_PORTID),
|
.THIS_PORTID (THIS_PORTID),
|
||||||
.CHDR_W (CHDR_W),
|
.CHDR_W (CHDR_W),
|
||||||
.CTRLPORT_SLV_EN (1),
|
.MTU (MTU),
|
||||||
.CTRLPORT_MST_EN (1),
|
.NUM_PORTS (NUM_PORTS),
|
||||||
.CTRL_FIFO_SIZE (CTRL_FIFO_SIZE),
|
|
||||||
.NUM_DATA_I (NUM_PORTS),
|
|
||||||
.NUM_DATA_O (NUM_PORTS),
|
|
||||||
.ITEM_W (ITEM_W),
|
|
||||||
.NIPC (NIPC),
|
.NIPC (NIPC),
|
||||||
.PYLD_FIFO_SIZE (MTU),
|
.ITEM_W (ITEM_W)
|
||||||
.MTU (MTU)
|
|
||||||
) noc_shell_radio_i (
|
) noc_shell_radio_i (
|
||||||
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
||||||
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
|
||||||
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
||||||
|
.radio_clk (radio_clk),
|
||||||
|
.rfnoc_chdr_rst (),
|
||||||
.rfnoc_ctrl_rst (),
|
.rfnoc_ctrl_rst (),
|
||||||
|
.radio_rst (radio_rst),
|
||||||
.rfnoc_core_config (rfnoc_core_config),
|
.rfnoc_core_config (rfnoc_core_config),
|
||||||
.rfnoc_core_status (rfnoc_core_status),
|
.rfnoc_core_status (rfnoc_core_status),
|
||||||
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
|
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
|
||||||
@@ -202,17 +195,17 @@ module rfnoc_block_radio #(
|
|||||||
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
|
||||||
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
|
||||||
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
|
||||||
.ctrlport_clk (radio_clk),
|
.ctrlport_clk (),
|
||||||
.ctrlport_rst (radio_rst),
|
.ctrlport_rst (),
|
||||||
.m_ctrlport_req_wr (ctrlport_reg_req_wr),
|
.m_ctrlport_req_wr (ctrlport_reg_req_wr),
|
||||||
.m_ctrlport_req_rd (ctrlport_reg_req_rd),
|
.m_ctrlport_req_rd (ctrlport_reg_req_rd),
|
||||||
.m_ctrlport_req_addr (ctrlport_reg_req_addr),
|
.m_ctrlport_req_addr (ctrlport_reg_req_addr),
|
||||||
.m_ctrlport_req_data (ctrlport_reg_req_data),
|
.m_ctrlport_req_data (ctrlport_reg_req_data),
|
||||||
.m_ctrlport_req_byte_en (),
|
.m_ctrlport_req_byte_en (ctrlport_reg_req_byte_en),
|
||||||
.m_ctrlport_req_has_time (ctrlport_reg_has_time),
|
.m_ctrlport_req_has_time (ctrlport_reg_has_time),
|
||||||
.m_ctrlport_req_time (ctrlport_reg_time),
|
.m_ctrlport_req_time (ctrlport_reg_time),
|
||||||
.m_ctrlport_resp_ack (ctrlport_reg_resp_ack),
|
.m_ctrlport_resp_ack (ctrlport_reg_resp_ack),
|
||||||
.m_ctrlport_resp_status (AXIS_CTRL_STS_OKAY),
|
.m_ctrlport_resp_status (ctrlport_reg_resp_status),
|
||||||
.m_ctrlport_resp_data (ctrlport_reg_resp_data),
|
.m_ctrlport_resp_data (ctrlport_reg_resp_data),
|
||||||
.s_ctrlport_req_wr (ctrlport_err_req_wr),
|
.s_ctrlport_req_wr (ctrlport_err_req_wr),
|
||||||
.s_ctrlport_req_rd (1'b0),
|
.s_ctrlport_req_rd (1'b0),
|
||||||
@@ -227,38 +220,27 @@ module rfnoc_block_radio #(
|
|||||||
.s_ctrlport_resp_ack (ctrlport_err_resp_ack),
|
.s_ctrlport_resp_ack (ctrlport_err_resp_ack),
|
||||||
.s_ctrlport_resp_status (),
|
.s_ctrlport_resp_status (),
|
||||||
.s_ctrlport_resp_data (),
|
.s_ctrlport_resp_data (),
|
||||||
.axis_data_clk (radio_clk),
|
.axis_data_clk (),
|
||||||
.axis_data_rst (radio_rst),
|
.axis_data_rst (),
|
||||||
.m_axis_tdata (axis_tx_tdata),
|
.m_in_axis_tdata (axis_tx_tdata),
|
||||||
.m_axis_tkeep (), // Radio only transmits full words
|
.m_in_axis_tkeep (), // Radio only transmits full words
|
||||||
.m_axis_tlast (axis_tx_tlast),
|
.m_in_axis_tlast (axis_tx_tlast),
|
||||||
.m_axis_tvalid (axis_tx_tvalid),
|
.m_in_axis_tvalid (axis_tx_tvalid),
|
||||||
.m_axis_tready (axis_tx_tready),
|
.m_in_axis_tready (axis_tx_tready),
|
||||||
.m_axis_ttimestamp (axis_tx_ttimestamp),
|
.m_in_axis_ttimestamp (axis_tx_ttimestamp),
|
||||||
.m_axis_thas_time (axis_tx_thas_time),
|
.m_in_axis_thas_time (axis_tx_thas_time),
|
||||||
.m_axis_teov (),
|
.m_in_axis_tlength (),
|
||||||
.m_axis_teob (axis_tx_teob),
|
.m_in_axis_teov (),
|
||||||
.s_axis_tdata (axis_rx_tdata),
|
.m_in_axis_teob (axis_tx_teob),
|
||||||
.s_axis_tkeep ({NUM_PORTS*NIPC{1'b1}}), // Radio only receives full words
|
.s_out_axis_tdata (axis_rx_tdata),
|
||||||
.s_axis_tlast (axis_rx_tlast),
|
.s_out_axis_tkeep ({NUM_PORTS*NIPC{1'b1}}), // Radio only receives full words
|
||||||
.s_axis_tvalid (axis_rx_tvalid),
|
.s_out_axis_tlast (axis_rx_tlast),
|
||||||
.s_axis_tready (axis_rx_tready),
|
.s_out_axis_tvalid (axis_rx_tvalid),
|
||||||
.s_axis_ttimestamp (axis_rx_ttimestamp),
|
.s_out_axis_tready (axis_rx_tready),
|
||||||
.s_axis_thas_time (axis_rx_thas_time),
|
.s_out_axis_ttimestamp (axis_rx_ttimestamp),
|
||||||
.s_axis_teov ({NUM_PORTS{1'b0}}),
|
.s_out_axis_thas_time (axis_rx_thas_time),
|
||||||
.s_axis_teob (axis_rx_teob)
|
.s_out_axis_teov ({NUM_PORTS{1'b0}}),
|
||||||
);
|
.s_out_axis_teob (axis_rx_teob)
|
||||||
|
|
||||||
// Cross the CHDR reset to the radio_clk domain
|
|
||||||
pulse_synchronizer #(
|
|
||||||
.MODE ("POSEDGE")
|
|
||||||
) ctrl_rst_sync_i (
|
|
||||||
.clk_a (rfnoc_chdr_clk),
|
|
||||||
.rst_a (1'b0),
|
|
||||||
.pulse_a (rfnoc_chdr_rst),
|
|
||||||
.busy_a (),
|
|
||||||
.clk_b (radio_clk),
|
|
||||||
.pulse_b (radio_rst)
|
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
@@ -304,11 +286,11 @@ module rfnoc_block_radio #(
|
|||||||
.s_ctrlport_req_rd (ctrlport_reg_req_rd),
|
.s_ctrlport_req_rd (ctrlport_reg_req_rd),
|
||||||
.s_ctrlport_req_addr (ctrlport_reg_req_addr),
|
.s_ctrlport_req_addr (ctrlport_reg_req_addr),
|
||||||
.s_ctrlport_req_data (ctrlport_reg_req_data),
|
.s_ctrlport_req_data (ctrlport_reg_req_data),
|
||||||
.s_ctrlport_req_byte_en (4'b0),
|
.s_ctrlport_req_byte_en (ctrlport_reg_req_byte_en),
|
||||||
.s_ctrlport_req_has_time (ctrlport_reg_has_time),
|
.s_ctrlport_req_has_time (ctrlport_reg_has_time),
|
||||||
.s_ctrlport_req_time (ctrlport_reg_time),
|
.s_ctrlport_req_time (ctrlport_reg_time),
|
||||||
.s_ctrlport_resp_ack (ctrlport_reg_resp_ack),
|
.s_ctrlport_resp_ack (ctrlport_reg_resp_ack),
|
||||||
.s_ctrlport_resp_status (),
|
.s_ctrlport_resp_status (ctrlport_reg_resp_status),
|
||||||
.s_ctrlport_resp_data (ctrlport_reg_resp_data),
|
.s_ctrlport_resp_data (ctrlport_reg_resp_data),
|
||||||
.m_ctrlport_req_wr ({m_ctrlport_req_wr,
|
.m_ctrlport_req_wr ({m_ctrlport_req_wr,
|
||||||
ctrlport_core_req_wr,
|
ctrlport_core_req_wr,
|
||||||
|
|||||||
@@ -34,6 +34,7 @@ module rfnoc_block_radio_tb #(
|
|||||||
|
|
||||||
|
|
||||||
// Simulation Parameters
|
// Simulation Parameters
|
||||||
|
localparam int NOC_ID = 32'h12AD1000;
|
||||||
localparam logic [ 9:0] THIS_PORTID = 10'h17;
|
localparam logic [ 9:0] THIS_PORTID = 10'h17;
|
||||||
localparam logic [15:0] THIS_EPID = 16'hDEAD;
|
localparam logic [15:0] THIS_EPID = 16'hDEAD;
|
||||||
localparam int MTU = 8;
|
localparam int MTU = 8;
|
||||||
@@ -555,11 +556,9 @@ module rfnoc_block_radio_tb #(
|
|||||||
test.start_test("Verify Block Info", 2us);
|
test.start_test("Verify Block Info", 2us);
|
||||||
|
|
||||||
// Get static block info and validate it
|
// Get static block info and validate it
|
||||||
`ASSERT_ERROR(blk_ctrl.get_noc_id() == rfnoc_block_radio_i.NOC_ID, "Incorrect noc_id Value");
|
`ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect noc_id Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect num_data_i Value");
|
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect num_data_i Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect num_data_o Value");
|
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect num_data_o Value");
|
||||||
`ASSERT_ERROR(blk_ctrl.get_ctrl_fifosize() == rfnoc_block_radio_i.noc_shell_radio_i.CTRL_FIFO_SIZE,
|
|
||||||
"Incorrect ctrl_fifosize Value");
|
|
||||||
`ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect mtu Value");
|
`ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect mtu Value");
|
||||||
|
|
||||||
test.end_test();
|
test.end_test();
|
||||||
|
|||||||
Reference in New Issue
Block a user