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rfnoc: Update blocks to use autogenerated noc_shell

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Original-commit: b746819769e6a960f8227981ea10c7ed9c3d826a
This commit is contained in:
Wade Fife
2020-02-06 14:50:33 -06:00
committed by Wade Fife
parent a69290143b
commit 59adae6252
23 changed files with 2411 additions and 1829 deletions
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lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/noc_shell_axi_ram_fifo.v
+199 -249
View File
@@ -1,123 +1,110 @@
//
// Copyright 2019 Ettus Research, A National Instruments Company
// Copyright 2019 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: noc_shell_axi_ram_fifo
//
// Description: A NoC Shell for the RFNoC AXI RAM FIFO. This NoC Shell
// implements the control port interface but does nothing to the
// data path other than moving it to the requested clock domain.
// Description:
//
// This is a tool-generated NoC-shell for the axi_ram_fifo block.
// See the RFNoC specification for more information about NoC shells.
//
// Parameters:
//
// THIS_PORTID : Control crossbar port to which this block is connected
// CHDR_W : AXIS-CHDR data bus width
// MTU : Maximum transmission unit (i.e., maximum packet size in
//
`define MAX(X,Y) ((X) > (Y) ? (X) : (Y))
`default_nettype none
module noc_shell_axi_ram_fifo #(
parameter [31:0] NOC_ID = 32'h0,
parameter [ 9:0] THIS_PORTID = 10'd0,
parameter CHDR_W = 64,
parameter DATA_W = 64,
parameter [ 5:0] CTRL_FIFO_SIZE = 0,
parameter [ 0:0] CTRLPORT_MST_EN = 1,
parameter [ 0:0] CTRLPORT_SLV_EN = 1,
parameter [ 5:0] NUM_DATA_I = 1,
parameter [ 5:0] NUM_DATA_O = 1,
parameter [ 5:0] MTU = 10,
parameter SYNC_DATA_CLOCKS = 0
parameter [9:0] THIS_PORTID = 10'd0,
parameter CHDR_W = 64,
parameter [5:0] MTU = 10,
parameter NUM_PORTS = 2,
parameter MEM_DATA_W = 64,
parameter MEM_ADDR_W = 30,
parameter FIFO_ADDR_BASE = {30'h02000000, 30'h00000000},
parameter FIFO_ADDR_MASK = {30'h01FFFFFF, 30'h01FFFFFF},
parameter MEM_CLK_RATE = 300e6
) (
//---------------------------------------------------------------------------
//---------------------
// Framework Interface
//---------------------------------------------------------------------------
//---------------------
// RFNoC Framework Clocks
input wire rfnoc_chdr_clk,
input wire rfnoc_ctrl_clk,
input wire mem_clk,
// NoC Shell Generated Resets
output wire rfnoc_chdr_rst,
output wire rfnoc_ctrl_rst,
output wire mem_rst,
// RFNoC Framework Clocks and Resets
input wire rfnoc_chdr_clk,
output wire rfnoc_chdr_rst,
input wire rfnoc_ctrl_clk,
output wire rfnoc_ctrl_rst,
// RFNoC Backend Interface
input wire [ 511:0] rfnoc_core_config,
output wire [ 511:0] rfnoc_core_status,
// CHDR Input Ports (from framework)
input wire [(CHDR_W*NUM_DATA_I)-1:0] s_rfnoc_chdr_tdata,
input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tlast,
input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tvalid,
output wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tready,
// CHDR Output Ports (to framework)
output wire [(CHDR_W*NUM_DATA_O)-1:0] m_rfnoc_chdr_tdata,
output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tlast,
output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tvalid,
input wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tready,
// AXIS-Ctrl Input Port (from framework)
input wire [ 31:0] s_rfnoc_ctrl_tdata,
input wire s_rfnoc_ctrl_tlast,
input wire s_rfnoc_ctrl_tvalid,
output wire s_rfnoc_ctrl_tready,
// AXIS-Ctrl Output Port (to framework)
output wire [ 31:0] m_rfnoc_ctrl_tdata,
output wire m_rfnoc_ctrl_tlast,
output wire m_rfnoc_ctrl_tvalid,
input wire m_rfnoc_ctrl_tready,
input wire [511:0] rfnoc_core_config,
output wire [511:0] rfnoc_core_status,
//---------------------------------------------------------------------------
// Client Control Port Interface
//---------------------------------------------------------------------------
// AXIS-CHDR Input Ports (from framework)
input wire [(0+NUM_PORTS)*CHDR_W-1:0] s_rfnoc_chdr_tdata,
input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tlast,
input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tvalid,
output wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tready,
// AXIS-CHDR Output Ports (to framework)
output wire [(0+NUM_PORTS)*CHDR_W-1:0] m_rfnoc_chdr_tdata,
output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tlast,
output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tvalid,
input wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tready,
// Clock
input wire ctrlport_clk,
input wire ctrlport_rst,
// Master
output wire m_ctrlport_req_wr,
output wire m_ctrlport_req_rd,
output wire [19:0] m_ctrlport_req_addr,
output wire [31:0] m_ctrlport_req_data,
output wire [ 3:0] m_ctrlport_req_byte_en,
output wire m_ctrlport_req_has_time,
output wire [63:0] m_ctrlport_req_time,
input wire m_ctrlport_resp_ack,
input wire [ 1:0] m_ctrlport_resp_status,
input wire [31:0] m_ctrlport_resp_data,
// Slave
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [ 9:0] s_ctrlport_req_portid,
input wire [15:0] s_ctrlport_req_rem_epid,
input wire [ 9:0] s_ctrlport_req_rem_portid,
input wire [31:0] s_ctrlport_req_data,
input wire [ 3:0] s_ctrlport_req_byte_en,
input wire s_ctrlport_req_has_time,
input wire [63:0] s_ctrlport_req_time,
output wire s_ctrlport_resp_ack,
output wire [ 1:0] s_ctrlport_resp_status,
output wire [31:0] s_ctrlport_resp_data,
// AXIS-Ctrl Control Input Port (from framework)
input wire [31:0] s_rfnoc_ctrl_tdata,
input wire s_rfnoc_ctrl_tlast,
input wire s_rfnoc_ctrl_tvalid,
output wire s_rfnoc_ctrl_tready,
// AXIS-Ctrl Control Output Port (to framework)
output wire [31:0] m_rfnoc_ctrl_tdata,
output wire m_rfnoc_ctrl_tlast,
output wire m_rfnoc_ctrl_tvalid,
input wire m_rfnoc_ctrl_tready,
//---------------------------------------------------------------------------
// Client Data Interface
//---------------------------------------------------------------------------
//---------------------
// Client Interface
//---------------------
// Clock
input wire axis_data_clk,
input wire axis_data_rst,
// CtrlPort Clock and Reset
output wire ctrlport_clk,
output wire ctrlport_rst,
// CtrlPort Master
output wire m_ctrlport_req_wr,
output wire m_ctrlport_req_rd,
output wire [19:0] m_ctrlport_req_addr,
output wire [31:0] m_ctrlport_req_data,
input wire m_ctrlport_resp_ack,
input wire [31:0] m_ctrlport_resp_data,
// Output data stream (to user logic)
output wire [ (NUM_DATA_I*DATA_W)-1:0] m_axis_tdata,
output wire [(NUM_DATA_I*`MAX(DATA_W/CHDR_W, 1))-1:0] m_axis_tkeep,
output wire [ NUM_DATA_I-1:0] m_axis_tlast,
output wire [ NUM_DATA_I-1:0] m_axis_tvalid,
input wire [ NUM_DATA_I-1:0] m_axis_tready,
// Input data stream (from user logic)
input wire [ (NUM_DATA_O*DATA_W)-1:0] s_axis_tdata,
input wire [(NUM_DATA_O*`MAX(DATA_W/CHDR_W, 1))-1:0] s_axis_tkeep,
input wire [ NUM_DATA_O-1:0] s_axis_tlast,
input wire [ NUM_DATA_O-1:0] s_axis_tvalid,
output wire [ NUM_DATA_O-1:0] s_axis_tready
// AXIS-CHDR Clock and Reset
output wire axis_chdr_clk,
output wire axis_chdr_rst,
// Framework to User Logic: in
output wire [NUM_PORTS*CHDR_W-1:0] m_in_chdr_tdata,
output wire [NUM_PORTS-1:0] m_in_chdr_tlast,
output wire [NUM_PORTS-1:0] m_in_chdr_tvalid,
input wire [NUM_PORTS-1:0] m_in_chdr_tready,
// User Logic to Framework: out
input wire [NUM_PORTS*CHDR_W-1:0] s_out_chdr_tdata,
input wire [NUM_PORTS-1:0] s_out_chdr_tlast,
input wire [NUM_PORTS-1:0] s_out_chdr_tvalid,
output wire [NUM_PORTS-1:0] s_out_chdr_tready
);
//---------------------------------------------------------------------------
// Backend Interface
//---------------------------------------------------------------------------
wire data_i_flush_en;
wire [31:0] data_i_flush_timeout;
wire [63:0] data_i_flush_active;
@@ -128,18 +115,18 @@ module noc_shell_axi_ram_fifo #(
wire [63:0] data_o_flush_done;
backend_iface #(
.NOC_ID (NOC_ID),
.NUM_DATA_I (NUM_DATA_I),
.NUM_DATA_O (NUM_DATA_O),
.CTRL_FIFOSIZE (CTRL_FIFO_SIZE),
.NOC_ID (32'hF1F00000),
.NUM_DATA_I (0+NUM_PORTS),
.NUM_DATA_O (0+NUM_PORTS),
.CTRL_FIFOSIZE ($clog2(32)),
.MTU (MTU)
) backend_iface_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.rfnoc_core_config (rfnoc_core_config),
.rfnoc_core_status (rfnoc_core_status),
.rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.data_i_flush_en (data_i_flush_en),
.data_i_flush_timeout (data_i_flush_timeout),
.data_i_flush_active (data_i_flush_active),
@@ -151,169 +138,132 @@ module noc_shell_axi_ram_fifo #(
);
//---------------------------------------------------------------------------
// Control Path
// Reset Generation
//---------------------------------------------------------------------------
ctrlport_endpoint #(
.THIS_PORTID (THIS_PORTID ),
.SYNC_CLKS (0 ),
.AXIS_CTRL_MST_EN (CTRLPORT_SLV_EN),
.AXIS_CTRL_SLV_EN (CTRLPORT_MST_EN),
.SLAVE_FIFO_SIZE (CTRL_FIFO_SIZE )
) ctrlport_ep_i (
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst ),
.ctrlport_clk (ctrlport_clk ),
.ctrlport_rst (ctrlport_rst ),
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid ),
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready ),
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid ),
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready ),
.m_ctrlport_req_wr (m_ctrlport_req_wr ),
.m_ctrlport_req_rd (m_ctrlport_req_rd ),
.m_ctrlport_req_addr (m_ctrlport_req_addr ),
.m_ctrlport_req_data (m_ctrlport_req_data ),
.m_ctrlport_req_byte_en (m_ctrlport_req_byte_en ),
.m_ctrlport_req_has_time (m_ctrlport_req_has_time ),
.m_ctrlport_req_time (m_ctrlport_req_time ),
.m_ctrlport_resp_ack (m_ctrlport_resp_ack ),
.m_ctrlport_resp_status (m_ctrlport_resp_status ),
.m_ctrlport_resp_data (m_ctrlport_resp_data ),
.s_ctrlport_req_wr (s_ctrlport_req_wr ),
.s_ctrlport_req_rd (s_ctrlport_req_rd ),
.s_ctrlport_req_addr (s_ctrlport_req_addr ),
.s_ctrlport_req_portid (s_ctrlport_req_portid ),
.s_ctrlport_req_rem_epid (s_ctrlport_req_rem_epid ),
.s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
.s_ctrlport_req_data (s_ctrlport_req_data ),
.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en ),
.s_ctrlport_req_has_time (s_ctrlport_req_has_time ),
.s_ctrlport_req_time (s_ctrlport_req_time ),
.s_ctrlport_resp_ack (s_ctrlport_resp_ack ),
.s_ctrlport_resp_status (s_ctrlport_resp_status ),
.s_ctrlport_resp_data (s_ctrlport_resp_data )
wire mem_rst_pulse;
pulse_synchronizer #(.MODE ("POSEDGE")) pulse_synchronizer_mem (
.clk_a(rfnoc_chdr_clk), .rst_a(1'b0), .pulse_a (rfnoc_chdr_rst), .busy_a (),
.clk_b(mem_clk), .pulse_b (mem_rst_pulse)
);
pulse_stretch_min #(.LENGTH(32)) pulse_stretch_min_mem (
.clk(mem_clk), .rst(1'b0),
.pulse_in(mem_rst_pulse), .pulse_out(mem_rst)
);
//---------------------------------------------------------------------------
// Data Path
// Control Path
//---------------------------------------------------------------------------
// Set WORD_W to the smaller of DATA_W and CHDR_W. This will be our common
// word size between the CHDR and user data ports.
localparam WORD_W = DATA_W < CHDR_W ? DATA_W : CHDR_W;
localparam KEEP_W = `MAX(DATA_W/CHDR_W, 1);
assign ctrlport_clk = mem_clk;
assign ctrlport_rst = mem_rst;
ctrlport_endpoint #(
.THIS_PORTID (THIS_PORTID),
.SYNC_CLKS (0),
.AXIS_CTRL_MST_EN (0),
.AXIS_CTRL_SLV_EN (1),
.SLAVE_FIFO_SIZE ($clog2(32))
) ctrlport_endpoint_i (
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.ctrlport_clk (ctrlport_clk),
.ctrlport_rst (ctrlport_rst),
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
.m_ctrlport_req_wr (m_ctrlport_req_wr),
.m_ctrlport_req_rd (m_ctrlport_req_rd),
.m_ctrlport_req_addr (m_ctrlport_req_addr),
.m_ctrlport_req_data (m_ctrlport_req_data),
.m_ctrlport_req_byte_en (),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
.m_ctrlport_resp_status (2'b0),
.m_ctrlport_resp_data (m_ctrlport_resp_data),
.s_ctrlport_req_wr (1'b0),
.s_ctrlport_req_rd (1'b0),
.s_ctrlport_req_addr (20'b0),
.s_ctrlport_req_portid (10'b0),
.s_ctrlport_req_rem_epid (16'b0),
.s_ctrlport_req_rem_portid (10'b0),
.s_ctrlport_req_data (32'b0),
.s_ctrlport_req_byte_en (4'hF),
.s_ctrlport_req_has_time (1'b0),
.s_ctrlport_req_time (64'b0),
.s_ctrlport_resp_ack (),
.s_ctrlport_resp_status (),
.s_ctrlport_resp_data ()
);
//---------------------------------------------------------------------------
// Data Path
//---------------------------------------------------------------------------
genvar i;
for (i = 0; i < NUM_DATA_I; i = i + 1) begin : gen_in
wire [CHDR_W-1:0] temp_in_tdata;
wire temp_in_tlast;
wire temp_in_tvalid;
wire temp_in_tready;
assign axis_chdr_clk = rfnoc_chdr_clk;
assign axis_chdr_rst = rfnoc_chdr_rst;
//---------------------
// Input Data Paths
//---------------------
axis_packet_flush #(
.WIDTH (CHDR_W),
.FLUSH_PARTIAL_PKTS (0),
.TIMEOUT_W (32),
.PIPELINE ("IN")
) in_packet_flush_i (
.clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst),
.enable (data_i_flush_en),
.timeout (data_i_flush_timeout),
.flushing (data_i_flush_active[i]),
.done (data_i_flush_done[i]),
.s_axis_tdata (s_rfnoc_chdr_tdata[i*CHDR_W +: CHDR_W]),
.s_axis_tlast (s_rfnoc_chdr_tlast[i]),
.s_axis_tvalid (s_rfnoc_chdr_tvalid[i]),
.s_axis_tready (s_rfnoc_chdr_tready[i]),
.m_axis_tdata (temp_in_tdata),
.m_axis_tlast (temp_in_tlast),
.m_axis_tvalid (temp_in_tvalid),
.m_axis_tready (temp_in_tready)
);
axis_width_conv #(
.WORD_W (WORD_W),
.IN_WORDS (CHDR_W/WORD_W),
.OUT_WORDS (DATA_W/WORD_W),
.SYNC_CLKS (SYNC_DATA_CLOCKS),
.PIPELINE ("NONE")
) in_width_conv_i (
.s_axis_aclk (rfnoc_chdr_clk),
.s_axis_rst (rfnoc_chdr_rst),
.s_axis_tdata (temp_in_tdata),
.s_axis_tkeep ({CHDR_W/WORD_W{1'b1}}),
.s_axis_tlast (temp_in_tlast),
.s_axis_tvalid (temp_in_tvalid),
.s_axis_tready (temp_in_tready),
.m_axis_aclk (axis_data_clk),
.m_axis_rst (axis_data_rst),
.m_axis_tdata (m_axis_tdata[i*DATA_W +: DATA_W]),
.m_axis_tkeep (m_axis_tkeep[i*KEEP_W +: KEEP_W]),
.m_axis_tlast (m_axis_tlast[i]),
.m_axis_tvalid (m_axis_tvalid[i]),
.m_axis_tready (m_axis_tready[i])
for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_input_in
chdr_to_chdr_data #(
.CHDR_W (CHDR_W)
) chdr_to_chdr_data_in_in (
.axis_chdr_clk (rfnoc_chdr_clk),
.axis_chdr_rst (rfnoc_chdr_rst),
.s_axis_chdr_tdata (s_rfnoc_chdr_tdata[(0+i)*CHDR_W+:CHDR_W]),
.s_axis_chdr_tlast (s_rfnoc_chdr_tlast[0+i]),
.s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[0+i]),
.s_axis_chdr_tready (s_rfnoc_chdr_tready[0+i]),
.m_axis_chdr_tdata (m_in_chdr_tdata[i*CHDR_W+:CHDR_W]),
.m_axis_chdr_tlast (m_in_chdr_tlast[i]),
.m_axis_chdr_tvalid (m_in_chdr_tvalid[i]),
.m_axis_chdr_tready (m_in_chdr_tready[i]),
.flush_en (data_i_flush_en),
.flush_timeout (data_i_flush_timeout),
.flush_active (data_i_flush_active[0+i]),
.flush_done (data_i_flush_done[0+i])
);
end
//---------------------
// Output Data Paths
//---------------------
for (i = 0; i < NUM_DATA_O; i = i + 1) begin : gen_out
wire [ CHDR_W-1:0] temp_out_tdata;
wire [CHDR_W/WORD_W-1:0] temp_out_tkeep;
wire temp_out_tlast;
wire temp_out_tvalid;
wire temp_out_tready;
axis_width_conv #(
.WORD_W (WORD_W),
.IN_WORDS (DATA_W/WORD_W),
.OUT_WORDS (CHDR_W/WORD_W),
.SYNC_CLKS (SYNC_DATA_CLOCKS),
.PIPELINE ("NONE")
) out_width_conv_i (
.s_axis_aclk (axis_data_clk),
.s_axis_rst (axis_data_rst),
.s_axis_tdata (s_axis_tdata[i*DATA_W +: DATA_W]),
.s_axis_tkeep (s_axis_tkeep[i*KEEP_W +: KEEP_W]),
.s_axis_tlast (s_axis_tlast[i]),
.s_axis_tvalid (s_axis_tvalid[i]),
.s_axis_tready (s_axis_tready[i]),
.m_axis_aclk (rfnoc_chdr_clk),
.m_axis_rst (rfnoc_chdr_rst),
.m_axis_tdata (temp_out_tdata),
.m_axis_tkeep (),
.m_axis_tlast (temp_out_tlast),
.m_axis_tvalid (temp_out_tvalid),
.m_axis_tready (temp_out_tready)
for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_output_out
chdr_to_chdr_data #(
.CHDR_W (CHDR_W)
) chdr_to_chdr_data_out_out (
.axis_chdr_clk (rfnoc_chdr_clk),
.axis_chdr_rst (rfnoc_chdr_rst),
.m_axis_chdr_tdata (m_rfnoc_chdr_tdata[(0+i)*CHDR_W+:CHDR_W]),
.m_axis_chdr_tlast (m_rfnoc_chdr_tlast[0+i]),
.m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[0+i]),
.m_axis_chdr_tready (m_rfnoc_chdr_tready[0+i]),
.s_axis_chdr_tdata (s_out_chdr_tdata[i*CHDR_W+:CHDR_W]),
.s_axis_chdr_tlast (s_out_chdr_tlast[i]),
.s_axis_chdr_tvalid (s_out_chdr_tvalid[i]),
.s_axis_chdr_tready (s_out_chdr_tready[i]),
.flush_en (data_o_flush_en),
.flush_timeout (data_o_flush_timeout),
.flush_active (data_o_flush_active[0+i]),
.flush_done (data_o_flush_done[0+i])
);
axis_packet_flush #(
.WIDTH (CHDR_W),
.FLUSH_PARTIAL_PKTS (0),
.TIMEOUT_W (32),
.PIPELINE ("OUT")
) out_packet_flush_i (
.clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst),
.enable (data_o_flush_en),
.timeout (data_o_flush_timeout),
.flushing (data_o_flush_active[i]),
.done (data_o_flush_done[i]),
.s_axis_tdata (temp_out_tdata),
.s_axis_tlast (temp_out_tlast),
.s_axis_tvalid (temp_out_tvalid),
.s_axis_tready (temp_out_tready),
.m_axis_tdata (m_rfnoc_chdr_tdata[i*CHDR_W +: CHDR_W]),
.m_axis_tlast (m_rfnoc_chdr_tlast[i]),
.m_axis_tvalid (m_rfnoc_chdr_tvalid[i]),
.m_axis_tready (m_rfnoc_chdr_tready[i])
);
end
endmodule
endmodule // noc_shell_axi_ram_fifo
`default_nettype wire
lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo.v
+145 -108
View File
@@ -182,13 +182,15 @@ module rfnoc_block_axi_ram_fifo #(
`include "axi_ram_fifo_regs.vh"
localparam NOC_ID = 'hF1F0_0000;
// If the memory width is larger than the CHDR width, then we need to use
// tkeep to track which CHDR words are valid as they go through the FIFO.
// Calculate the TKEEP width here. Set to 1 if it's not needed.
localparam KEEP_W = (MEM_DATA_W/CHDR_W) > 1 ? (MEM_DATA_W/CHDR_W) : 1;
// Set WORD_W to the smaller of MEM_DATA_W and CHDR_W. This will be our
// common word size when resizing between CHDR and memory words.
localparam WORD_W = (MEM_DATA_W < CHDR_W) ? MEM_DATA_W : CHDR_W;
//---------------------------------------------------------------------------
// Parameter Checks
@@ -205,7 +207,7 @@ module rfnoc_block_axi_ram_fifo #(
// NoC Shell
//---------------------------------------------------------------------------
wire rfnoc_chdr_rst;
wire mem_rst;
wire ctrlport_req_wr;
wire ctrlport_req_rd;
@@ -214,110 +216,74 @@ module rfnoc_block_axi_ram_fifo #(
wire ctrlport_resp_ack;
wire [31:0] ctrlport_resp_data;
wire [NUM_PORTS*MEM_DATA_W-1:0] m_axis_data_tdata;
wire [ NUM_PORTS*KEEP_W-1:0] m_axis_data_tkeep;
wire [ NUM_PORTS-1:0] m_axis_data_tlast;
wire [ NUM_PORTS-1:0] m_axis_data_tvalid;
wire [ NUM_PORTS-1:0] m_axis_data_tready;
wire axis_chdr_clk;
wire axis_chdr_rst;
wire [NUM_PORTS*MEM_DATA_W-1:0] s_axis_data_tdata;
wire [ NUM_PORTS*KEEP_W-1:0] s_axis_data_tkeep;
wire [ NUM_PORTS-1:0] s_axis_data_tlast;
wire [ NUM_PORTS-1:0] s_axis_data_tvalid;
wire [ NUM_PORTS-1:0] s_axis_data_tready;
wire [NUM_PORTS*CHDR_W-1:0] m_axis_chdr_tdata;
wire [ NUM_PORTS-1:0] m_axis_chdr_tlast;
wire [ NUM_PORTS-1:0] m_axis_chdr_tvalid;
wire [ NUM_PORTS-1:0] m_axis_chdr_tready;
wire [NUM_PORTS*CHDR_W-1:0] s_axis_chdr_tdata;
wire [ NUM_PORTS-1:0] s_axis_chdr_tlast;
wire [ NUM_PORTS-1:0] s_axis_chdr_tvalid;
wire [ NUM_PORTS-1:0] s_axis_chdr_tready;
noc_shell_axi_ram_fifo #(
.NOC_ID (NOC_ID),
.THIS_PORTID (THIS_PORTID),
.CHDR_W (CHDR_W),
.DATA_W (MEM_DATA_W),
.CTRL_FIFO_SIZE (5),
.CTRLPORT_MST_EN (1),
.CTRLPORT_SLV_EN (0),
.NUM_DATA_I (NUM_PORTS),
.NUM_DATA_O (NUM_PORTS),
.MTU (MTU),
.SYNC_DATA_CLOCKS (0)
.THIS_PORTID (THIS_PORTID),
.CHDR_W (CHDR_W),
.NUM_PORTS (NUM_PORTS),
.MTU (MTU)
) noc_shell_axi_ram_fifo_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (),
.rfnoc_core_config (rfnoc_core_config),
.rfnoc_core_status (rfnoc_core_status),
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
.ctrlport_clk (mem_clk),
.ctrlport_rst (axi_rst),
.m_ctrlport_req_wr (ctrlport_req_wr),
.m_ctrlport_req_rd (ctrlport_req_rd),
.m_ctrlport_req_addr (ctrlport_req_addr),
.m_ctrlport_req_data (ctrlport_req_data),
.m_ctrlport_req_byte_en (),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack (ctrlport_resp_ack),
.m_ctrlport_resp_status (2'b0),
.m_ctrlport_resp_data (ctrlport_resp_data),
.s_ctrlport_req_wr (1'b0),
.s_ctrlport_req_rd (1'b0),
.s_ctrlport_req_addr (20'b0),
.s_ctrlport_req_portid (10'b0),
.s_ctrlport_req_rem_epid (16'b0),
.s_ctrlport_req_rem_portid (10'b0),
.s_ctrlport_req_data (32'b0),
.s_ctrlport_req_byte_en (4'b0),
.s_ctrlport_req_has_time (1'b0),
.s_ctrlport_req_time (64'b0),
.s_ctrlport_resp_ack (),
.s_ctrlport_resp_status (),
.s_ctrlport_resp_data (),
.axis_data_clk (mem_clk),
.axis_data_rst (axi_rst),
.m_axis_tdata (m_axis_data_tdata),
.m_axis_tkeep (m_axis_data_tkeep),
.m_axis_tlast (m_axis_data_tlast),
.m_axis_tvalid (m_axis_data_tvalid),
.m_axis_tready (m_axis_data_tready),
.s_axis_tdata (s_axis_data_tdata),
.s_axis_tkeep (s_axis_data_tkeep),
.s_axis_tlast (s_axis_data_tlast),
.s_axis_tvalid (s_axis_data_tvalid),
.s_axis_tready (s_axis_data_tready)
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.mem_clk (mem_clk),
.rfnoc_chdr_rst (),
.rfnoc_ctrl_rst (),
.mem_rst (mem_rst),
.rfnoc_core_config (rfnoc_core_config),
.rfnoc_core_status (rfnoc_core_status),
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
.ctrlport_clk (),
.ctrlport_rst (),
.m_ctrlport_req_wr (ctrlport_req_wr),
.m_ctrlport_req_rd (ctrlport_req_rd),
.m_ctrlport_req_addr (ctrlport_req_addr),
.m_ctrlport_req_data (ctrlport_req_data),
.m_ctrlport_resp_ack (ctrlport_resp_ack),
.m_ctrlport_resp_data (ctrlport_resp_data),
.axis_chdr_clk (axis_chdr_clk),
.axis_chdr_rst (axis_chdr_rst),
.m_in_chdr_tdata (m_axis_chdr_tdata),
.m_in_chdr_tlast (m_axis_chdr_tlast),
.m_in_chdr_tvalid (m_axis_chdr_tvalid),
.m_in_chdr_tready (m_axis_chdr_tready),
.s_out_chdr_tdata (s_axis_chdr_tdata),
.s_out_chdr_tlast (s_axis_chdr_tlast),
.s_out_chdr_tvalid (s_axis_chdr_tvalid),
.s_out_chdr_tready (s_axis_chdr_tready)
);
wire rfnoc_chdr_rst_mem_clk;
reg mem_rst_block;
// Cross the CHDR reset to the mem_clk domain
pulse_synchronizer #(
.MODE ("POSEDGE")
) ctrl_rst_sync_i (
.clk_a (rfnoc_chdr_clk),
.rst_a (1'b0),
.pulse_a (rfnoc_chdr_rst),
.busy_a (),
.clk_b (mem_clk),
.pulse_b (rfnoc_chdr_rst_mem_clk)
);
// Combine the resets in a glitch-free manner
always @(posedge mem_clk) begin
mem_rst_block <= axi_rst | rfnoc_chdr_rst_mem_clk;
mem_rst_block <= axi_rst | mem_rst;
end
@@ -363,12 +329,83 @@ module rfnoc_block_axi_ram_fifo #(
//---------------------------------------------------------------------------
// FIFO Instances
// AXI RAM Port Instances
//---------------------------------------------------------------------------
genvar i;
for (i = 0; i < NUM_PORTS; i = i + 1) begin : gen_ram_fifos
wire [MEM_DATA_W-1:0] m_axis_mem_tdata;
wire [ KEEP_W-1:0] m_axis_mem_tkeep;
wire m_axis_mem_tlast;
wire m_axis_mem_tvalid;
wire m_axis_mem_tready;
wire [MEM_DATA_W-1:0] s_axis_mem_tdata;
wire [ KEEP_W-1:0] s_axis_mem_tkeep;
wire s_axis_mem_tlast;
wire s_axis_mem_tvalid;
wire s_axis_mem_tready;
//-------------------------------------------------------------------------
// Width Conversion
//-------------------------------------------------------------------------
//
// Resize Data between CHDR_W and MEM_DATA_W. Cross between rfnoc_chdr_clk
// and mem_clk.
//
//-------------------------------------------------------------------------
axis_width_conv #(
.WORD_W (WORD_W),
.IN_WORDS (CHDR_W/WORD_W),
.OUT_WORDS (MEM_DATA_W/WORD_W),
.SYNC_CLKS (0),
.PIPELINE ("NONE")
) axis_width_conv_to_mem_i (
.s_axis_aclk (axis_chdr_clk),
.s_axis_rst (axis_chdr_rst),
.s_axis_tdata (m_axis_chdr_tdata[i*CHDR_W +: CHDR_W]),
.s_axis_tkeep ({CHDR_W/WORD_W{1'b1}}),
.s_axis_tlast (m_axis_chdr_tlast[i]),
.s_axis_tvalid (m_axis_chdr_tvalid[i]),
.s_axis_tready (m_axis_chdr_tready[i]),
.m_axis_aclk (mem_clk),
.m_axis_rst (mem_rst),
.m_axis_tdata (m_axis_mem_tdata),
.m_axis_tkeep (m_axis_mem_tkeep),
.m_axis_tlast (m_axis_mem_tlast),
.m_axis_tvalid (m_axis_mem_tvalid),
.m_axis_tready (m_axis_mem_tready)
);
axis_width_conv #(
.WORD_W (WORD_W),
.IN_WORDS (MEM_DATA_W/WORD_W),
.OUT_WORDS (CHDR_W/WORD_W),
.SYNC_CLKS (0),
.PIPELINE ("NONE")
) axis_width_conv_to_chdr_i (
.s_axis_aclk (mem_clk),
.s_axis_rst (mem_rst),
.s_axis_tdata (s_axis_mem_tdata),
.s_axis_tkeep (s_axis_mem_tkeep),
.s_axis_tlast (s_axis_mem_tlast),
.s_axis_tvalid (s_axis_mem_tvalid),
.s_axis_tready (s_axis_mem_tready),
.m_axis_aclk (axis_chdr_clk),
.m_axis_rst (axis_chdr_rst),
.m_axis_tdata (s_axis_chdr_tdata[i*CHDR_W +: CHDR_W]),
.m_axis_tkeep (),
.m_axis_tlast (s_axis_chdr_tlast[i]),
.m_axis_tvalid (s_axis_chdr_tvalid[i]),
.m_axis_tready (s_axis_chdr_tready[i])
);
//---------------------------------------------------------------------------
// AXI RAM FIFO Instance
//---------------------------------------------------------------------------
wire [MEM_ADDR_W-1:0] m_axi_awaddr_int;
wire [MEM_ADDR_W-1:0] m_axi_araddr_int;
@@ -408,18 +445,18 @@ module rfnoc_block_axi_ram_fifo #(
//-----------------------------------------------------------------------
// AXI-Stream Input
.s_tdata (m_axis_data_tdata[MEM_DATA_W*i +: MEM_DATA_W]),
.s_tkeep (m_axis_data_tkeep[KEEP_W*i +: KEEP_W]),
.s_tlast (m_axis_data_tlast[i]),
.s_tvalid (m_axis_data_tvalid[i]),
.s_tready (m_axis_data_tready[i]),
.s_tdata (m_axis_mem_tdata),
.s_tkeep (m_axis_mem_tkeep),
.s_tlast (m_axis_mem_tlast),
.s_tvalid (m_axis_mem_tvalid),
.s_tready (m_axis_mem_tready),
//
// AXI-Stream Output
.m_tdata (s_axis_data_tdata[MEM_DATA_W*i +: MEM_DATA_W]),
.m_tkeep (s_axis_data_tkeep[KEEP_W*i +: KEEP_W]),
.m_tlast (s_axis_data_tlast[i]),
.m_tvalid (s_axis_data_tvalid[i]),
.m_tready (s_axis_data_tready[i]),
.m_tdata (s_axis_mem_tdata),
.m_tkeep (s_axis_mem_tkeep),
.m_tlast (s_axis_mem_tlast),
.m_tvalid (s_axis_mem_tvalid),
.m_tready (s_axis_mem_tready),
//-----------------------------------------------------------------------
// AXI4 Memory Interface
lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_tb.sv
+3 -2
View File
@@ -45,6 +45,7 @@ module rfnoc_block_axi_ram_fifo_tb #(
localparam int STALL_PROB = 25; // BFM stall probability
// Block configuration
localparam int NOC_ID = 'hF1F0_0000;
localparam int THIS_PORTID = 'h123;
localparam int MTU = 12;
localparam int NUM_HB = 3;
@@ -74,7 +75,7 @@ module rfnoc_block_axi_ram_fifo_tb #(
rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
sim_clock_gen #(.PERIOD(CTRL_CLK_PER), .AUTOSTART(0))
rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
sim_clock_gen #(.PERIOD(MEM_CLK_PER), .AUOSTART(0))
sim_clock_gen #(.PERIOD(MEM_CLK_PER), .AUTOSTART(0))
mem_clk_gen (.clk(mem_clk), .rst(mem_rst));
@@ -379,7 +380,7 @@ module rfnoc_block_axi_ram_fifo_tb #(
task test_block_info();
test.start_test("Verify Block Info", 2us);
`ASSERT_ERROR(blk_ctrl.get_noc_id() == rfnoc_block_axi_ram_fifo_i.NOC_ID, "Incorrect NOC_ID Value");
`ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");
`ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I Value");
`ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O Value");
`ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");