fpga: x400: Add timed commands support for all radio ctrlport endpoints
Extends timed command support to all endpoints
addressable by the radio ctrlport interface.
Previously supported endpoints:
- Daughterboard GPIO interface
- RFDC timing control
Newly supported endpoints:
- DIO ATR control
- DIO SPI control
- DIO Source control
Original-commit: e51f18925a566f152c4e8622aac6376efe46c6eb
This commit is contained in:
committed by
Wade Fife
parent
1c5b744a4d
commit
57e460af22
+53
-46
@@ -124,9 +124,6 @@ module x4xx_core_common #(
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output wire [ 1*NUM_DBOARDS-1:0] m_radio_ctrlport_req_rd,
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output wire [ 20*NUM_DBOARDS-1:0] m_radio_ctrlport_req_addr,
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output wire [ 32*NUM_DBOARDS-1:0] m_radio_ctrlport_req_data,
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output wire [ 4*NUM_DBOARDS-1:0] m_radio_ctrlport_req_byte_en,
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output wire [ 1*NUM_DBOARDS-1:0] m_radio_ctrlport_req_has_time,
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output wire [ 64*NUM_DBOARDS-1:0] m_radio_ctrlport_req_time,
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input wire [ 1*NUM_DBOARDS-1:0] m_radio_ctrlport_resp_ack,
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input wire [ 2*NUM_DBOARDS-1:0] m_radio_ctrlport_resp_status,
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input wire [ 32*NUM_DBOARDS-1:0] m_radio_ctrlport_resp_data,
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@@ -355,9 +352,6 @@ module x4xx_core_common #(
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wire [ 1*NUM_DBOARDS-1:0] rf_ctrlport_req_rd;
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wire [ 20*NUM_DBOARDS-1:0] rf_ctrlport_req_addr;
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wire [ 32*NUM_DBOARDS-1:0] rf_ctrlport_req_data;
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wire [ 4*NUM_DBOARDS-1:0] rf_ctrlport_req_byte_en;
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wire [ 1*NUM_DBOARDS-1:0] rf_ctrlport_req_has_time;
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wire [ 64*NUM_DBOARDS-1:0] rf_ctrlport_req_time;
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wire [ 1*NUM_DBOARDS-1:0] rf_ctrlport_resp_ack;
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wire [ 2*NUM_DBOARDS-1:0] rf_ctrlport_resp_status;
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wire [ 32*NUM_DBOARDS-1:0] rf_ctrlport_resp_data;
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@@ -366,9 +360,6 @@ module x4xx_core_common #(
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wire [ 1*NUM_DBOARDS-1:0] radio_dio_req_rd;
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wire [ 20*NUM_DBOARDS-1:0] radio_dio_req_addr;
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wire [ 32*NUM_DBOARDS-1:0] radio_dio_req_data;
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wire [ 4*NUM_DBOARDS-1:0] radio_dio_req_byte_en;
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wire [ 1*NUM_DBOARDS-1:0] radio_dio_req_has_time;
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wire [ 64*NUM_DBOARDS-1:0] radio_dio_req_time;
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wire [ 1*NUM_DBOARDS-1:0] radio_dio_resp_ack;
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wire [ 2*NUM_DBOARDS-1:0] radio_dio_resp_status;
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wire [ 32*NUM_DBOARDS-1:0] radio_dio_resp_data;
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@@ -377,9 +368,6 @@ module x4xx_core_common #(
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wire [ 1*NUM_DBOARDS-1:0] gpio_atr_ctrlport_req_rd;
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wire [ 20*NUM_DBOARDS-1:0] gpio_atr_ctrlport_req_addr;
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wire [ 32*NUM_DBOARDS-1:0] gpio_atr_ctrlport_req_data;
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wire [ 4*NUM_DBOARDS-1:0] gpio_atr_ctrlport_req_byte_en;
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wire [ 1*NUM_DBOARDS-1:0] gpio_atr_ctrlport_req_has_time;
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wire [ 64*NUM_DBOARDS-1:0] gpio_atr_ctrlport_req_time;
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wire [ 1*NUM_DBOARDS-1:0] gpio_atr_ctrlport_resp_ack;
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wire [ 2*NUM_DBOARDS-1:0] gpio_atr_ctrlport_resp_status;
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wire [ 32*NUM_DBOARDS-1:0] gpio_atr_ctrlport_resp_data;
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@@ -388,9 +376,6 @@ module x4xx_core_common #(
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wire [ 1*NUM_DBOARDS-1:0] gpio_spi_ctrlport_req_rd;
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wire [ 20*NUM_DBOARDS-1:0] gpio_spi_ctrlport_req_addr;
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wire [ 32*NUM_DBOARDS-1:0] gpio_spi_ctrlport_req_data;
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wire [ 4*NUM_DBOARDS-1:0] gpio_spi_ctrlport_req_byte_en;
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wire [ 1*NUM_DBOARDS-1:0] gpio_spi_ctrlport_req_has_time;
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wire [ 64*NUM_DBOARDS-1:0] gpio_spi_ctrlport_req_time;
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wire [ 1*NUM_DBOARDS-1:0] gpio_spi_ctrlport_resp_ack;
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wire [ 2*NUM_DBOARDS-1:0] gpio_spi_ctrlport_resp_status;
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wire [ 32*NUM_DBOARDS-1:0] gpio_spi_ctrlport_resp_data;
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@@ -407,6 +392,46 @@ module x4xx_core_common #(
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generate
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for (db = 0; db < NUM_DBOARDS; db = db+1) begin : gen_radio_ctrlport
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//----------------------------------------------------------------------------
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// Timed command processing
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//----------------------------------------------------------------------------
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wire [19:0] ctrlport_timed_req_addr;
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wire [31:0] ctrlport_timed_req_data;
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wire ctrlport_timed_req_rd;
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wire ctrlport_timed_req_wr;
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wire ctrlport_timed_resp_ack;
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wire [31:0] ctrlport_timed_resp_data;
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wire [ 1:0] ctrlport_timed_resp_status;
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ctrlport_timer #(
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.EXEC_LATE_CMDS(1)
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) ctrlport_timer_i (
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.clk (radio_clk),
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.rst (radio_rst),
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.time_now (radio_time),
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.time_now_stb (sample_rx_stb),
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.time_ignore_bits (time_ignore_bits),
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.s_ctrlport_req_wr (s_radio_ctrlport_req_wr [ 1*db+: 1]),
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.s_ctrlport_req_rd (s_radio_ctrlport_req_rd [ 1*db+: 1]),
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.s_ctrlport_req_addr (s_radio_ctrlport_req_addr [20*db+:20]),
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.s_ctrlport_req_data (s_radio_ctrlport_req_data [32*db+:32]),
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.s_ctrlport_req_byte_en (s_radio_ctrlport_req_byte_en [ 4*db+: 4]),
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.s_ctrlport_req_has_time (s_radio_ctrlport_req_has_time [ 1*db+: 1]),
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.s_ctrlport_req_time (s_radio_ctrlport_req_time [64*db+:64]),
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.s_ctrlport_resp_ack (s_radio_ctrlport_resp_ack [ 1*db+: 1]),
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.s_ctrlport_resp_status (s_radio_ctrlport_resp_status [ 2*db+: 2]),
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.s_ctrlport_resp_data (s_radio_ctrlport_resp_data [32*db+:32]),
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.m_ctrlport_req_wr (ctrlport_timed_req_wr),
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.m_ctrlport_req_rd (ctrlport_timed_req_rd),
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.m_ctrlport_req_addr (ctrlport_timed_req_addr),
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.m_ctrlport_req_data (ctrlport_timed_req_data),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_resp_ack (ctrlport_timed_resp_ack),
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.m_ctrlport_resp_status (ctrlport_timed_resp_status),
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.m_ctrlport_resp_data (ctrlport_timed_resp_data)
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);
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//-----------------------------------------------------------------------
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// Radio Block CtrlPort Splitter
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//-----------------------------------------------------------------------
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@@ -448,16 +473,16 @@ module x4xx_core_common #(
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) ctrlport_decoder_param_i (
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.ctrlport_clk ( radio_clk ),
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.ctrlport_rst ( radio_rst ),
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.s_ctrlport_req_wr ( s_radio_ctrlport_req_wr [ 1*db+: 1] ),
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.s_ctrlport_req_rd ( s_radio_ctrlport_req_rd [ 1*db+: 1] ),
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.s_ctrlport_req_addr ( s_radio_ctrlport_req_addr [20*db+:20] ),
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.s_ctrlport_req_data ( s_radio_ctrlport_req_data [32*db+:32] ),
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.s_ctrlport_req_byte_en ( s_radio_ctrlport_req_byte_en [ 4*db+: 4] ),
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.s_ctrlport_req_has_time ( s_radio_ctrlport_req_has_time [ 1*db+: 1] ),
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.s_ctrlport_req_time ( s_radio_ctrlport_req_time [64*db+:64] ),
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.s_ctrlport_resp_ack ( s_radio_ctrlport_resp_ack [ 1*db+: 1] ),
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.s_ctrlport_resp_status ( s_radio_ctrlport_resp_status [ 2*db+: 2] ),
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.s_ctrlport_resp_data ( s_radio_ctrlport_resp_data [32*db+:32] ),
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.s_ctrlport_req_wr ( ctrlport_timed_req_wr),
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.s_ctrlport_req_rd ( ctrlport_timed_req_rd),
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.s_ctrlport_req_addr ( ctrlport_timed_req_addr),
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.s_ctrlport_req_data ( ctrlport_timed_req_data),
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.s_ctrlport_req_byte_en ( 4'hF),
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.s_ctrlport_req_has_time ( 1'b0),
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.s_ctrlport_req_time ( 64'h0),
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.s_ctrlport_resp_ack ( ctrlport_timed_resp_ack),
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.s_ctrlport_resp_status ( ctrlport_timed_resp_status),
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.s_ctrlport_resp_data ( ctrlport_timed_resp_data),
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.m_ctrlport_req_wr ({ gpio_spi_ctrlport_req_wr [ 1*db+: 1],
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radio_dio_req_wr [ 1*db+: 1],
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gpio_atr_ctrlport_req_wr [ 1*db+: 1],
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@@ -478,21 +503,9 @@ module x4xx_core_common #(
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gpio_atr_ctrlport_req_data [32*db+:32],
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rf_ctrlport_req_data [32*db+:32],
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m_radio_ctrlport_req_data [32*db+:32] }),
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.m_ctrlport_req_byte_en ({ gpio_spi_ctrlport_req_byte_en [ 4*db+: 4],
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radio_dio_req_byte_en [ 4*db+: 4],
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gpio_atr_ctrlport_req_byte_en [ 4*db+: 4],
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rf_ctrlport_req_byte_en [ 4*db+: 4],
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m_radio_ctrlport_req_byte_en [ 4*db+: 4] }),
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.m_ctrlport_req_has_time ({ gpio_spi_ctrlport_req_has_time [ 1*db+: 1],
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radio_dio_req_has_time [ 1*db+: 1],
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gpio_atr_ctrlport_req_has_time [ 1*db+: 1],
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rf_ctrlport_req_has_time [ 1*db+: 1],
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m_radio_ctrlport_req_has_time [ 1*db+: 1] }),
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.m_ctrlport_req_time ({ gpio_spi_ctrlport_req_time [64*db+:64],
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radio_dio_req_time [64*db+:64],
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gpio_atr_ctrlport_req_time [64*db+:64],
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rf_ctrlport_req_time [64*db+:64],
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m_radio_ctrlport_req_time [64*db+:64] }),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack ({ gpio_spi_ctrlport_resp_ack [ 1*db+: 1],
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radio_dio_resp_ack [ 1*db+: 1],
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gpio_atr_ctrlport_resp_ack [ 1*db+: 1],
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@@ -565,16 +578,10 @@ module x4xx_core_common #(
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) rfdc_timing_control_i (
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.clk (radio_clk),
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.rst (radio_rst),
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.time_now (radio_time),
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.time_now_stb (sample_rx_stb),
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.time_ignore_bits (time_ignore_bits),
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.s_ctrlport_req_wr (rf_ctrlport_req_wr),
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.s_ctrlport_req_rd (rf_ctrlport_req_rd),
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.s_ctrlport_req_addr (rf_ctrlport_req_addr),
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.s_ctrlport_req_data (rf_ctrlport_req_data),
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.s_ctrlport_req_byte_en (rf_ctrlport_req_byte_en),
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.s_ctrlport_req_has_time (rf_ctrlport_req_has_time),
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.s_ctrlport_req_time (rf_ctrlport_req_time),
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.s_ctrlport_resp_ack (rf_ctrlport_resp_ack),
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.s_ctrlport_resp_status (rf_ctrlport_resp_status),
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.s_ctrlport_resp_data (rf_ctrlport_resp_data),
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