diff --git a/top/x400/doc/X4XX_FPGA_right.htm b/top/x400/doc/X4XX_FPGA_right.htm index b7495d6..0d8ec1c 100644 --- a/top/x400/doc/X4XX_FPGA_right.htm +++ b/top/x400/doc/X4XX_FPGA_right.htm @@ -24131,9 +24131,9 @@ FPGA version.
- 570500626 + 570565649 - 0x22012612 + 0x22022411

FPGA_VERSION_LAST_MODIFIED_TIME

diff --git a/top/x400/regmap/versioning_regs_regmap_utils.vh b/top/x400/regmap/versioning_regs_regmap_utils.vh index 9d9eb39..8928f06 100644 --- a/top/x400/regmap/versioning_regs_regmap_utils.vh +++ b/top/x400/regmap/versioning_regs_regmap_utils.vh @@ -85,7 +85,7 @@ localparam FPGA_CURRENT_VERSION_MINOR = 'h6; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR localparam FPGA_CURRENT_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR - localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h22012612; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME + localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h22022411; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME // Enumerated type RF_CORE_100M_VERSION localparam RF_CORE_100M_VERSION_SIZE = 7; diff --git a/top/x400/x4xx.v b/top/x400/x4xx.v index 5c05b9e..c16f551 100644 --- a/top/x400/x4xx.v +++ b/top/x400/x4xx.v @@ -2289,7 +2289,7 @@ endmodule // // // -// +// // // // diff --git a/top/x400/x4xx_gpio_spi.v b/top/x400/x4xx_gpio_spi.v index b5866f8..a037ae1 100644 --- a/top/x400/x4xx_gpio_spi.v +++ b/top/x400/x4xx_gpio_spi.v @@ -342,13 +342,18 @@ module x4xx_gpio_spi #( // Register set_stb for use in 2x domain. reg set_stb_2x = 1'b0; - reg ctrlport_clk_phase = 1'b0; + reg ctrlport_clk_phase = 1'b1; always @ (posedge ctrlport_clk_2x) begin - // Assert strobe only during a single 2x cycle of the - // 1x pulse. - set_stb_2x <= ctrlport_clk_phase & set_stb; - ctrlport_clk_phase <= ~ctrlport_clk_phase; + if (ctrlport_rst) begin + ctrlport_clk_phase <= 1'b1; + set_stb_2x <= 1'b0; + end else begin + // Assert strobe only during a single 2x cycle of the + // 1x pulse, when 1x clock is low. + set_stb_2x <= ctrlport_clk_phase & set_stb; + ctrlport_clk_phase <= ~ctrlport_clk_phase; + end end simple_spi_core #(