miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: lib: Fix IPv4 CHDR TUSER width

Browse Source 
Fix the TUSER width for some buses in eth_ipv4_chdr_adapter. This
allows wider CHDR widths to be used with 10 GbE.


Original-commit: f0ed58f7518410fc174a6356c072dfb21e3de253
This commit is contained in:
Wade Fife
2023-06-11 12:58:25 -05:00
parent 9ed8bb22d6
commit 564944ea93
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/rfnoc/xport_sv/eth_ipv4_chdr_adapter.sv
+2 -2
View File
@@ -259,10 +259,10 @@ module eth_ipv4_chdr_adapter #(
//--------------------------------------- //---------------------------------------
// tUser = {*not used*} // tUser = {*not used*}
AxiStreamIf #(.DATA_WIDTH(CHDR_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0)) AxiStreamIf #(.DATA_WIDTH(CHDR_W),.USER_WIDTH(CHDR_USER_W),.TKEEP(0))
v2e1D(v2e.clk,v2e.rst); v2e1D(v2e.clk,v2e.rst);
// tUser = {*not used*} // tUser = {*not used*}
AxiStreamIf #(.DATA_WIDTH(CHDR_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0)) AxiStreamIf #(.DATA_WIDTH(CHDR_W),.USER_WIDTH(CHDR_USER_W),.TKEEP(0))
v2e1(v2e.clk,v2e.rst); v2e1(v2e.clk,v2e.rst);
// tUser = {*not used*} // tUser = {*not used*}
AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0)) AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0))