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fpga: rfnoc: Add support for 512-bit CHDR widths

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This fixes the rfnoc_null_src_sink, chdr_crossbar_nxn, and
chdr_stream_endpoint blocks so that wider CHDR widths are properly
supported. It also updates PkgChdrBfm to able to properly test these
blocks. The testbenches have been updated to test both 64 and 512-bit
widths.


Original-commit: 3af8dcaacfa4bf36dcae3bdbf0b353385b7063c6
This commit is contained in:
Andrew Moch
2020-06-18 09:09:34 -05:00
committed by Wade Fife
parent 8875582763
commit 55881469ac
19 changed files with 599 additions and 420 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/rfnoc/core/chdr_stream_output.v
+2 -2
View File
@@ -411,7 +411,7 @@ module chdr_stream_output #(
if (CHDR_W < 128)
state <= ST_STRC_W1;
else
state <= ST_STRC_WAIT;
state <= fc_resync_req ? ST_PASS_DATA : ST_STRC_WAIT;
end
// ST_STRC_W1
@@ -527,7 +527,7 @@ module chdr_stream_output #(
assign msg_o_tready = msg_o_tvalid && (state == ST_PASS_DATA || state == ST_STRC_WAIT);
// Acknowledge a flow control resync command
assign fc_resync_ack = fc_resync_req && (state == ST_STRC_W1) &&
assign fc_resync_ack = fc_resync_req && (state == ST_STRC_W1 || state == ST_STRC_W0) &&
chdr_out_tvalid && chdr_out_tready && chdr_out_tlast;
// ---------------------------------------------------
lib/rfnoc/core/chdr_to_axis_ctrl.v
+45 -42
View File
@@ -116,7 +116,7 @@ module chdr_to_axis_ctrl #(
ST_CHDR_HDR: begin
ch2ct_nmdata <= chdr_get_num_mdata(ch2ct_tdata[63:0]) - 5'd1;
if (!ch2ct_tlast)
ch2ct_state <= (chdr_get_num_mdata(ch2ct_tdata[63:0]) == 5'd0) ?
ch2ct_state <= (chdr_get_num_mdata(ch2ct_tdata[63:0]) == 5'd0) ?
ST_CTRL_HDR : ST_CHDR_MDATA;
else
ch2ct_state <= ST_CHDR_HDR; // Premature termination
@@ -152,7 +152,7 @@ module chdr_to_axis_ctrl #(
);
// Create the first two lines of the Ctrl word (wide)
// using data from CHDR packet
// using data from CHDR packet
wire [CHDR_W-1:0] ch2ct_new_ctrl_hdr;
assign ch2ct_new_ctrl_hdr[63:0] = {
axis_ctrl_build_hdr_hi(
@@ -172,7 +172,7 @@ module chdr_to_axis_ctrl #(
assign ch2ct_new_ctrl_hdr[CHDR_W-1:64] = ch2ct_tdata[CHDR_W-1:64];
end endgenerate
wire [CHDR_W-1:0] ch2ct_wctrl_tdata =
wire [CHDR_W-1:0] ch2ct_wctrl_tdata =
(ch2ct_state == ST_CTRL_HDR) ? ch2ct_new_ctrl_hdr : ch2ct_tdata;
axis_width_conv #(
@@ -205,7 +205,7 @@ module chdr_to_axis_ctrl #(
// - Use the Ctrl RemDstPort as the CHDR DstPort (forward the master's request)
// - Use the this_epid as CHDR SrcEPID (return path for the CHDR packet)
// - Use the Ctrl SrcPort as the CHDR SrcPort (return path to the master)
// - Ignore the Ctrl DstPort because the packet has already been routed
// - Ignore the Ctrl DstPort because the packet has already been routed
wire [CHDR_W-1:0] ct2ch_wctrl_tdata;
wire ct2ch_wctrl_tlast, ct2ch_wctrl_tvalid, ct2ch_wctrl_tready;
@@ -238,8 +238,7 @@ module chdr_to_axis_ctrl #(
end else if (ct2ch_tvalid && ct2ch_tready) begin
case (ct2ch_state)
ST_CHDR_HDR: begin
if (!ct2ch_tlast)
ct2ch_state <= ST_CTRL_HDR;
ct2ch_state <= ST_CTRL_HDR;
end
ST_CTRL_HDR: begin
if (ct2ch_tlast)
@@ -264,56 +263,60 @@ module chdr_to_axis_ctrl #(
// Hold the first line to generate info for the outgoing CHDR header
assign ct2ch_wctrl_tready = (ct2ch_state == ST_CTRL_HDR || ct2ch_state == ST_CTRL_BODY) ? ct2ch_tready : 1'b0;
wire [7:0] ct2ch_32bit_lines = 8'd3 + // Header + OpWord
(axis_ctrl_get_has_time(ct2ch_wctrl_tdata[31:0]) ? 8'd2 : 8'd0) + // Timestamp
({4'h0, axis_ctrl_get_num_data(ct2ch_wctrl_tdata[31:0])}); // Data words
wire [7:0] ct2ch_num_data = {4'h0, axis_ctrl_get_num_data(ct2ch_wctrl_tdata[31:0])};
wire [7:0] ct2ch_timestamp = axis_ctrl_get_has_time(ct2ch_wctrl_tdata[31:0]) ? 8'd2 : 8'd0;
wire [7:0] ct2ch_32bit_lines = CHDR_W/32 + // CHDR header
8'd3 + // CTL Header + OpWord
ct2ch_timestamp + // Timestamp
ct2ch_num_data; // Data words
wire [15:0] ct2ch_chdr_lines = 16'd1 + // CHDR header
ct2ch_32bit_lines[7:$clog2(CHDR_W/32)] + // Convert 32-bit lines to CHDR_W
(|ct2ch_32bit_lines[$clog2(CHDR_W/32)-1:0]); // Residue
reg [CHDR_W-1:0] ct2ch_sm_tdata,ct2ch_chdr_hdr;
reg [63:0] ct2ch_ctrl_hdr;
reg [63:0] ct2ch_chdr_tdata;
always @(*) begin
ct2ch_chdr_hdr = 0;
ct2ch_chdr_hdr = chdr_build_header(
6'd0, /* VC */
1'b0, 1'b0, /* eob, eov */
CHDR_PKT_TYPE_CTRL,
CHDR_NO_MDATA,
ct2ch_seqnum,
(ct2ch_32bit_lines << $clog2(32/8)), /* length in bytes */
axis_ctrl_get_rem_dst_epid(ct2ch_wctrl_tdata[63:32]));
ct2ch_ctrl_hdr = {
axis_ctrl_build_hdr_hi(
10'd0, /* Unused in CHDR Control payload */
this_epid /* This is the SrcEPID */
),
axis_ctrl_build_hdr_lo(
axis_ctrl_get_is_ack (ct2ch_wctrl_tdata[31:0]),
axis_ctrl_get_has_time(ct2ch_wctrl_tdata[31:0]),
axis_ctrl_get_seq_num (ct2ch_wctrl_tdata[31:0]),
axis_ctrl_get_num_data(ct2ch_wctrl_tdata[31:0]),
axis_ctrl_get_src_port(ct2ch_wctrl_tdata[31:0]),
axis_ctrl_get_rem_dst_port(ct2ch_wctrl_tdata[63:32])
)
};
end
always @(*) begin
case (ct2ch_state)
ST_CHDR_HDR: begin
ct2ch_chdr_tdata = chdr_build_header(
6'd0, /* VC */
1'b0, 1'b0, /* eob, eov */
CHDR_PKT_TYPE_CTRL,
CHDR_NO_MDATA,
ct2ch_seqnum,
(ct2ch_chdr_lines << $clog2(CHDR_W/8)), /* length in bytes */
axis_ctrl_get_rem_dst_epid(ct2ch_wctrl_tdata[63:32])
);
// regardless of width CHDR is always a full word
ct2ch_sm_tdata = ct2ch_chdr_hdr;
end
ST_CTRL_HDR: begin
ct2ch_chdr_tdata = {
axis_ctrl_build_hdr_hi(
10'd0, /* Unused in CHDR Control payload */
this_epid /* This is the SrcEPID */
),
axis_ctrl_build_hdr_lo(
axis_ctrl_get_is_ack (ct2ch_wctrl_tdata[31:0]),
axis_ctrl_get_has_time(ct2ch_wctrl_tdata[31:0]),
axis_ctrl_get_seq_num (ct2ch_wctrl_tdata[31:0]),
axis_ctrl_get_num_data(ct2ch_wctrl_tdata[31:0]),
axis_ctrl_get_src_port(ct2ch_wctrl_tdata[31:0]),
axis_ctrl_get_rem_dst_port(ct2ch_wctrl_tdata[63:32])
)
};
ct2ch_sm_tdata = ct2ch_wctrl_tdata;
ct2ch_sm_tdata[63:0] = ct2ch_ctrl_hdr;
end
default: begin
ct2ch_chdr_tdata = ct2ch_wctrl_tdata[63:0];
ct2ch_sm_tdata = ct2ch_wctrl_tdata;
end
endcase
end
// Output signals
assign ct2ch_tdata[63:0] = ct2ch_chdr_tdata;
assign ct2ch_tlast = ct2ch_wctrl_tlast;
assign ct2ch_tdata = ct2ch_sm_tdata;
assign ct2ch_tlast = ct2ch_wctrl_tlast && (ct2ch_state != ST_CHDR_HDR);
assign ct2ch_tvalid = ct2ch_wctrl_tvalid;
generate if (CHDR_W > 64) begin
assign ct2ch_tdata[CHDR_W-1:64] = ct2ch_wctrl_tdata[CHDR_W-1:64];
end endgenerate
endmodule // chdr_to_axis_ctrl