fpga: x400: Add SPI bus support for GPIO ports
Original-commit: 38c549d1f7672e38773fc6624539cc166285a1df
This commit is contained in:
Javier Valenzuela
committed by
Wade Fife
Wade Fife
parent
962d01e583
commit
5237e5778c
@@ -0,0 +1,534 @@
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//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: x4xx_gpio_spi
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//
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// Description:
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//
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// This block enables control of a SPI master engine via CtrlPort
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// transactions.
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// It also enables customization on how signals from the SPI buses
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// connected to the master are mapped to the GPIO Ports.
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// This block supports configuring communication to up to 4 SPI slaves.
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//
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// Parameters:
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//
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// NUM_SLAVES : Number of SPI slaves to be supported. Values from 1 to 4
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// are supported. SPI transfers can only target one slave
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// at a time.
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// BASE_ADDRESS : Start address for this register block.
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// SIZE_ADDRESS : Size of the CtrlPort window to consider in this block.
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//
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`default_nettype none
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module x4xx_gpio_spi #(
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parameter NUM_SLAVES = 4,
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parameter [19:0] BASE_ADDRESS = 0,
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parameter [19:0] SIZE_ADDRESS = 19'h20
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) (
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input wire ctrlport_clk,
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input wire ctrlport_clk_2x,
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input wire ctrlport_rst,
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// Request
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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// Response
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output reg s_ctrlport_resp_ack = 1'b0,
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output reg [ 1:0] s_ctrlport_resp_status = 2'b0,
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output reg [31:0] s_ctrlport_resp_data = 32'b0,
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// GPIO control/status
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output wire [31:0] gpio_out,
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output wire [31:0] gpio_ddr,
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input wire [31:0] gpio_in
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);
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`include "../../lib/rfnoc/core/ctrlport.vh"
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`include "regmap/dig_ifc_regmap_utils.vh"
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// Registers / wires for SPI core communication
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reg [31:0] set_data = 0;
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reg [ 7:0] set_addr = 0;
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reg set_stb = 1'b0;
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wire [31:0] readback;
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wire readback_stb;
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wire readback_stb_extended;
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wire sclk;
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wire mosi;
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wire miso;
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// This array is set to the maximum supported SPI slaves instead of
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// the provided NUM_SLAVES to facilitate concurrent re-mapping.
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// See section(GPIO Mapping) of this file.
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wire [3:0] ss;
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// Auxiliary signals to compute which GPIO lines are outputs
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reg [31:0] gpio_is_mosi = 32'b0;
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reg [31:0] gpio_is_sclk = 32'b0;
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reg [31:0] gpio_is_cs = 32'b0;
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// SPI-to-GPIO mapping signals.
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// These arrays are set to the maximum supported SPI slaves instead of
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// the provided NUM_SLAVES to facilitate concurrent re-mapping.
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// See section(GPIO Mapping) of this file.
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reg [ SLAVE_CLK_SIZE-1:0] sclk_mapping [3:0];
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reg [SLAVE_MOSI_SIZE-1:0] mosi_mapping [3:0];
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reg [SLAVE_MISO_SIZE-1:0] miso_mapping [3:0];
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reg [ SLAVE_CS_SIZE-1:0] ss_mapping [3:0];
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//---------------------------------------------------------------------------
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// Address calculation
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//---------------------------------------------------------------------------
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wire address_in_range =
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(s_ctrlport_req_addr >= BASE_ADDRESS) &&
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(s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);
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// Check that address is targeting slave configuration.
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wire address_is_slave =
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(s_ctrlport_req_addr >= BASE_ADDRESS + SPI_SLAVE_CONFIG(0)) &&
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(s_ctrlport_req_addr <= BASE_ADDRESS + SPI_SLAVE_CONFIG(3));
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// Decode the slave being addressed.
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wire [1:0]slave_address = s_ctrlport_req_addr[3:2];
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//---------------------------------------------------------------------------
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// Slave configuration signals
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//---------------------------------------------------------------------------
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// These settings are registered individually for each slave
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reg [ NUM_SLAVES-1:0] data_in_edge = {NUM_SLAVES{1'b0}};
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reg [ NUM_SLAVES-1:0] data_out_edge = {NUM_SLAVES{1'b0}};
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reg [SPI_LENGTH_SIZE-1:0] slave_spi_length [NUM_SLAVES-1:0];
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// One-hot encoding to indicate active slave
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reg [NUM_SLAVES-1:0] slave_select = {NUM_SLAVES{1'b0}};
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//---------------------------------------------------------------------------
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// FSM to handle transfers
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//---------------------------------------------------------------------------
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localparam IDLE = 3'd0;
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localparam SET_DIVIDER = 3'd1;
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localparam WRITE_SPI = 3'd2;
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localparam CONFIG_TRANSFER = 3'd3;
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localparam WAIT_SPI = 3'd4;
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localparam DIVIDER_ADDRESS = 8'd0;
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localparam CTRL_ADDRESS = 8'd1;
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localparam DATA_ADDRESS = 8'd2;
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reg [ 2:0] state = IDLE;
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reg [ 31:0] data_cache;
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reg [SPI_CLK_DIV_SIZE-1:0] divider;
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reg [ 1:0] cs;
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reg spi_go = 1'b0;
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reg spi_ready = 1'b0;
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integer slave_i;
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//---------------------------------------------------------------------------
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// CtrlPort Register endpoints
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//---------------------------------------------------------------------------
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always @ (posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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s_ctrlport_resp_ack <= 1'b0;
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spi_go <= 1'b0;
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spi_ready <= 1'b0;
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divider <= {SPI_CLK_DIV_SIZE{1'b0}};
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cs <= 2'b0;
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// Assigned to unassigned mapping. This avoids overwriting
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// signals with those from uninitialized slaves.
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for (slave_i=0; slave_i<4; slave_i=slave_i+1) begin
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sclk_mapping[slave_i] <= 5'h31;
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mosi_mapping[slave_i] <= 5'h31;
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miso_mapping[slave_i] <= 5'h31;
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ss_mapping [slave_i] <= 5'h31;
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end
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for (slave_i=0; slave_i<NUM_SLAVES; slave_i=slave_i+1) begin
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slave_spi_length[slave_i] <= {SPI_LENGTH_SIZE{1'b0}};
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end
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end else begin
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// Default assignments
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s_ctrlport_resp_ack <= 1'b0;
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spi_go <= 1'b0;
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// Requests appear
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if (s_ctrlport_req_wr) begin
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_data <= {32{1'bx}};
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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// Address spi configuration writes
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if(address_is_slave) begin
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// GPIO mapping
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sclk_mapping [slave_address] <= s_ctrlport_req_data[SLAVE_CLK_MSB:SLAVE_CLK];
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mosi_mapping [slave_address] <= s_ctrlport_req_data[SLAVE_MOSI_MSB:SLAVE_MOSI];
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miso_mapping [slave_address] <= s_ctrlport_req_data[SLAVE_MISO_MSB:SLAVE_MISO];
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ss_mapping [slave_address] <= s_ctrlport_req_data[SLAVE_CS_MSB:SLAVE_CS];
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// Transfer Configuration
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slave_spi_length [slave_address] <= s_ctrlport_req_data[SPI_LENGTH_MSB:SPI_LENGTH];
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data_in_edge [slave_address] <= s_ctrlport_req_data[MISO_EDGE];
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data_out_edge [slave_address] <= s_ctrlport_req_data[MOSI_EDGE];
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end else begin
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case (s_ctrlport_req_addr)
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BASE_ADDRESS + SPI_TRANSACTION_CONFIG: begin
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divider <= s_ctrlport_req_data[SPI_CLK_DIV_MSB:SPI_CLK_DIV];
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cs <= s_ctrlport_req_data[SPI_SLAVE_SELECT_MSB:SPI_SLAVE_SELECT];
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end
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BASE_ADDRESS + SPI_TRANSACTION_GO: begin
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spi_ready <= 1'b0;
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spi_go <= 1'b1;
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end
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// No register implementation for provided address
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default: begin
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// Acknowledge and provide error status if address is in range
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// No response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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end
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end else if(s_ctrlport_req_rd) begin
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// default assumption: valid request
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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s_ctrlport_resp_data <= {32{1'b0}};
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case (s_ctrlport_req_addr)
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BASE_ADDRESS + SPI_TRANSACTION_CONFIG: begin
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s_ctrlport_resp_data[SPI_CLK_DIV_MSB:SPI_CLK_DIV] <= divider;
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end
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BASE_ADDRESS + SPI_STATUS: begin
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s_ctrlport_resp_data[SPI_READY] <= spi_ready;
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s_ctrlport_resp_data[SPI_RESPONSE_MSB:SPI_RESPONSE] <= readback[SPI_RESPONSE_MSB:SPI_RESPONSE];
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end
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// No register implementation for provided address
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default: begin
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// Acknowledge and provide error status if address is in range
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// No response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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end
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if (readback_stb_extended) begin
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spi_ready <= 1'b1;
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end
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end
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end
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//---------------------------------------------------------------------------
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// SPI Control FSM
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//---------------------------------------------------------------------------
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always @ (posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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state <= IDLE;
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set_stb <= 1'b0;
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data_cache <= 32'h0;
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end else begin
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// Default Assignments
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set_stb <= 1'b0;
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case (state)
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IDLE: begin
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// Save data and address for further steps
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data_cache <= s_ctrlport_req_data;
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if (spi_go) begin
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state <= CONFIG_TRANSFER;
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slave_select <= {NUM_SLAVES{1'b0}};
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slave_select[cs] <= 1'b1;
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end
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end
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// Set slave select
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CONFIG_TRANSFER: begin
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state <= SET_DIVIDER;
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set_stb <= 1'b1;
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set_addr <= CTRL_ADDRESS;
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set_data <= { data_out_edge[cs], // 1 bit
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data_in_edge[cs], // 1 bit
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slave_spi_length[cs], // 6 bits
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{24-NUM_SLAVES{1'b0}}, // Padding for slaves
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slave_select // NUM_SLAVES bits
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};
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end
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// Write divider to SPI core
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SET_DIVIDER: begin
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state <= WRITE_SPI;
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set_stb <= 1'b1;
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set_addr <= DIVIDER_ADDRESS;
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set_data <= {16'b0, divider};
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end
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// Write data bits to SPI core (aligned to MSB)
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WRITE_SPI: begin
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state <= WAIT_SPI;
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set_stb <= 1'b1;
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set_addr <= DATA_ADDRESS;
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set_data <= data_cache;
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end
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// Wait for transaction to complete and translate to ctrlport response
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WAIT_SPI: begin
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if (readback_stb_extended) begin
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state <= IDLE;
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end
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end
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default: begin
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state <= IDLE;
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end
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endcase
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// Update Auxiliary signals
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gpio_is_mosi <= 32'h0;
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gpio_is_sclk <= 32'h0;
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gpio_is_cs <= 32'h0;
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for (slave_i=0; slave_i<NUM_SLAVES; slave_i=slave_i+1) begin
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gpio_is_mosi [mosi_mapping[slave_i]] <= 1'b1;
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gpio_is_sclk [sclk_mapping[slave_i]] <= 1'b1;
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gpio_is_cs [ ss_mapping[slave_i]] <= 1'b1;
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end
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end
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end
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//---------------------------------------------------------------------------
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// SPI master
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//---------------------------------------------------------------------------
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// Register set_stb for use in 2x domain.
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reg set_stb_2x = 1'b0;
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reg ctrlport_clk_phase = 1'b0;
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always @ (posedge ctrlport_clk_2x) begin
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// Assert strobe only during a single 2x cycle of the
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// 1x pulse.
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set_stb_2x <= ctrlport_clk_phase & set_stb;
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ctrlport_clk_phase <= ~ctrlport_clk_phase;
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end
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simple_spi_core #(
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.BASE (0),
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.WIDTH (NUM_SLAVES),
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.CLK_IDLE (0),
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.SEN_IDLE ({NUM_SLAVES{1'b1}})
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) simple_spi_core_i (
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.clock (ctrlport_clk_2x),
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.reset (ctrlport_rst),
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.set_stb (set_stb_2x),
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.set_addr (set_addr),
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.set_data (set_data),
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.readback (readback),
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.readback_stb (readback_stb),
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.ready (),
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.sen (ss[NUM_SLAVES-1:0]),
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.sclk (sclk),
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.mosi (mosi),
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.miso (miso),
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.debug ()
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);
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// Delay and extend signal for use in 1x domain.
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reg readback_stb_dly = 1'b0;
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always @ (posedge ctrlport_clk_2x) begin
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readback_stb_dly <= readback_stb;
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end
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assign readback_stb_extended = readback_stb_dly | readback_stb;
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//---------------------------------------------------------------------------
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// GPIO Mapping
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//---------------------------------------------------------------------------
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wire [31:0] mosi_mux_out;
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reg [31:0] mosi_mux_out_dlyd;
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wire [31:0] ss_mux_out;
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wire [31:0] gated_sclk;
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reg [31:0] gated_sclk_dlyd;
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reg [31:0] gpio_is_sclk_dlyd;
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genvar i;
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generate
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for (i = 0; i < 32; i = i + 1) begin: dio_output_gen
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// Indicate which GPIO lines are outputs
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assign gpio_ddr[i] = gpio_is_mosi[i] | gpio_is_sclk[i] | gpio_is_cs[i];
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// CS re-mapping
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assign ss_mux_out[i] = ( i == ss_mapping[0] ) ? ss[0] :
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( i == ss_mapping[1] ) ? ss[1] :
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( i == ss_mapping[2] ) ? ss[2] :
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( i == ss_mapping[3] ) ? ss[3] :
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1'b0;
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assign mosi_mux_out[i] = gpio_is_mosi[i] ? mosi : ss_mux_out[i];
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assign gated_sclk[i] = gpio_is_sclk[i] ? sclk : 1'b0;
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// register signals once remapping logic is resolved
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always @ (posedge ctrlport_clk_2x) begin
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mosi_mux_out_dlyd[i] <= mosi_mux_out[i];
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gpio_is_sclk_dlyd[i] <= gpio_is_sclk[i];
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gated_sclk_dlyd[i] <= gated_sclk[i];
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end
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// Choose between SCLK and MOSI/SS mux.
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glitch_free_mux glitch_free_gpio_out (
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.select (gpio_is_sclk_dlyd[i]),
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.signal0 (mosi_mux_out_dlyd[i]),
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.signal1 (gated_sclk_dlyd[i]),
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.muxed_signal (gpio_out[i])
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);
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end
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endgenerate
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assign miso = ( ~ss[0] ) ? gpio_in[miso_mapping[0]] :
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( ~ss[1] ) ? gpio_in[miso_mapping[1]] :
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( ~ss[2] ) ? gpio_in[miso_mapping[2]] :
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( ~ss[3] ) ? gpio_in[miso_mapping[3]] :
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1'b0;
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endmodule
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`default_nettype wire
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//XmlParse xml_on
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//<regmap name="DIG_IFC_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
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// <group name="SPI_OVER_GPIO_REGS">
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// <info>
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// </info>
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// <regtype name="SPI_SETUP" size="32">
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// <info>
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// Controls SPI Transaction
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// </info>
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// <bitfield name="SLAVE_CLK" range="0..4" initialvalue="0">
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// <info>
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// Indicates which GPIO line to use for the SCLK signal.</br>
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// 0-11 : Port A GPIO</br>
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// 16-27: Port B GPIO
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// </info>
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// </bitfield>
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// <bitfield name="SLAVE_MOSI" range="5..9" initialvalue="0">
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// <info>
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// Indicates which GPIO line to use for the MOSI signal.</br>
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// 0-11 : Port A GPIO</br>
|
||||
// 16-27: Port B GPIO
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="SLAVE_MISO" range="10..14" initialvalue="0">
|
||||
// <info>
|
||||
// Indicates which GPIO line to use for the MISO signal.</br>
|
||||
// 0-11 : Port A GPIO</br>
|
||||
// 16-27: Port B GPIO
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="SLAVE_CS" range="15..19" initialvalue="0">
|
||||
// <info>
|
||||
// Indicates which GPIO line to use for the CS signal.</br>
|
||||
// 0-11 : Port A GPIO</br>
|
||||
// 16-27: Port B GPIO
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="SPI_LENGTH" range="20..25" initialvalue="0">
|
||||
// <info>
|
||||
// Indicates the length of SPI transactions to this slave.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="MISO_EDGE" range="26" initialvalue="0">
|
||||
// <info>
|
||||
// Controls the edge in which the MISO line is latched.</br>
|
||||
// 0 = falling edge of SCLK.</br>
|
||||
// 1 = rising edge of SCLK.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="MOSI_EDGE" range="27" initialvalue="0">
|
||||
// <info>
|
||||
// Controls the edge in which the MOSI line is updated.</br>
|
||||
// 0 = falling edge of SCLK.</br>
|
||||
// 1 = rising edge of SCLK.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </regtype>
|
||||
// <register name="SPI_SLAVE_CONFIG" typename="SPI_SETUP" offset="0x00" count="4" options="--step 4">
|
||||
// <info> Set of configuration registers for the supported slaves. </info>
|
||||
// </register>
|
||||
// <register name="SPI_TRANSACTION_CONFIG" offset="0x10" size="32">
|
||||
// <info>
|
||||
// Controls clock rate and target for subsequent SPI transactions.
|
||||
// </info>
|
||||
// <bitfield name="SPI_CLK_DIV" range="0..15" initialvalue="0">
|
||||
// <info> Controls the rate for subsequent SPI transactions. SCLK = DataClk/[(SPI_CLK_DIV+1)]</info>
|
||||
// </bitfield>
|
||||
// <bitfield name="SPI_SLAVE_SELECT" range="16..17" initialvalue="0"/>
|
||||
// </register>
|
||||
// <register name="SPI_TRANSACTION_GO" offset="0x14" size="32" readable="false">
|
||||
// <info>
|
||||
// Starts a SPI transaction
|
||||
// </info>
|
||||
// <bitfield name="SPI_DATA" range="0..31" initialvalue="0">
|
||||
// <info> Payload to be sent for the SPI transaction. If the payload is shorter than 32 bits,
|
||||
// it must be aligned to the MSbs in this field. LSbs are ignored in this scenario.</info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// <register name="SPI_STATUS" offset="0x18" size="32" writable="false">
|
||||
// <info>
|
||||
// Contains the status of the SPI engine.
|
||||
// </info>
|
||||
// <bitfield name="SPI_READY" range="24" initialvalue="0">
|
||||
// <info> Indicates the SPI engine is ready to start a new SPI transaction. </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="SPI_RESPONSE" range="0..23" initialvalue="0">
|
||||
// <info> Records the response of the last completed SPI transaction. </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
Reference in New Issue
Block a user