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fpga: x400: Add SPI bus support for GPIO ports

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Original-commit: 38c549d1f7672e38773fc6624539cc166285a1df
This commit is contained in:
Javier Valenzuela
2022-01-25 10:18:47 -07:00
committed by Wade Fife
parent 962d01e583
commit 5237e5778c
9 changed files with 1338 additions and 60 deletions
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top/x400/doc/X4XX_FPGA_right.htm
+551 -2
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@@ -3229,6 +3229,492 @@ Total Offset =</td></tr>
</div>
</div>
<div class="regmap">
<a name="DIG_IFC_REGMAP"></a>
<h1 class="regmap">DIG_IFC_REGMAP</h1>
<div class="group"><a name="DIG_IFC_REGMAP|SPI_OVER_GPIO_REGS"></a><h2 class="group">SPI_OVER_GPIO_REGS</h2>
<div class="register">
<a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG"></a>
<h3 class="register">Offset 0x0000: SPI_SLAVE_CONFIG(3:0) Register Array (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('DIG_IFC_REGMAP|SPI_SLAVE_CONFIG_in')">(<span id="show_DIG_IFC_REGMAP|SPI_SLAVE_CONFIG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIG_IFC_REGMAP|SPI_SLAVE_CONFIG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIGITAL_IFC_REGS">RADIO_DIO_REGMAP|DIGITAL_IFC_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SPI_SLAVE_CONFIG</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0000 + i*4</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Cannot determine accessibility through this path</td></tr>
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x00E000 + i*4
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info"><B>Initial Values</B><BR/>
<table>
<tr><td>default</td><td>=&gt;</td><td>0x00000000</td></tr>
</table>
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_gpio_spi.v.<BR/>
It uses RegType <b>SPI_SETUP</b> which is defined in HDL source file x4xx_gpio_spi.v.</p>
</div>
<div class="info">
Controls SPI Transaction<BR/>
Set of configuration registers for the supported slaves.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..28</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">27</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG|MOSI_EDGE"></a>MOSI_EDGE</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
<p>Controls the edge in which the MOSI line is updated.</br>
0 = falling edge of SCLK.</br>
1 = rising edge of SCLK.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">26</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG|MISO_EDGE"></a>MISO_EDGE</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
<p>Controls the edge in which the MISO line is latched.</br>
0 = falling edge of SCLK.</br>
1 = rising edge of SCLK.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">25..20</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG|SPI_LENGTH"></a>SPI_LENGTH</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
<p>Indicates the length of SPI transactions to this slave.</p>
</td>
</tr>
<tr valign="top">
<td class="bits">19..15</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG|SLAVE_CS"></a>SLAVE_CS</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
<p>Indicates which GPIO line to use for the CS signal.</br>
0-11 : Port A GPIO</br>
16-27: Port B GPIO</p>
</td>
</tr>
<tr valign="top">
<td class="bits">14..10</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG|SLAVE_MISO"></a>SLAVE_MISO</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
<p>Indicates which GPIO line to use for the MISO signal.</br>
0-11 : Port A GPIO</br>
16-27: Port B GPIO</p>
</td>
</tr>
<tr valign="top">
<td class="bits">9..5</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG|SLAVE_MOSI"></a>SLAVE_MOSI</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
<p>Indicates which GPIO line to use for the MOSI signal.</br>
0-11 : Port A GPIO</br>
16-27: Port B GPIO</p>
</td>
</tr>
<tr valign="top">
<td class="bits">4..0</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_SLAVE_CONFIG|SLAVE_CLK"></a>SLAVE_CLK</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
<p>Indicates which GPIO line to use for the SCLK signal.</br>
0-11 : Port A GPIO</br>
16-27: Port B GPIO</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG"></a>
<h3 class="register">Offset 0x0010: SPI_TRANSACTION_CONFIG Register (R|W)</h3>
<a class="sh_addrs" href="javascript:sa('DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG_in')">(<span id="show_DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIGITAL_IFC_REGS">RADIO_DIO_REGMAP|DIGITAL_IFC_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SPI_TRANSACTION_CONFIG</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0010</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x00E010
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_gpio_spi.v.</p>
</div>
<div class="info">
Controls clock rate and target for subsequent SPI transactions.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..24</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..18</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">17..16</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG|SPI_SLAVE_SELECT"></a>SPI_SLAVE_SELECT</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
<p></p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">15..0</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG|SPI_CLK_DIV"></a>SPI_CLK_DIV</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
<p>Controls the rate for subsequent SPI transactions. SCLK = DataClk/[(SPI_CLK_DIV+1)]</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="DIG_IFC_REGMAP|SPI_TRANSACTION_GO"></a>
<h3 class="register">Offset 0x0014: SPI_TRANSACTION_GO Register (W)</h3>
<a class="sh_addrs" href="javascript:sa('DIG_IFC_REGMAP|SPI_TRANSACTION_GO_in')">(<span id="show_DIG_IFC_REGMAP|SPI_TRANSACTION_GO_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIG_IFC_REGMAP|SPI_TRANSACTION_GO_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIGITAL_IFC_REGS">RADIO_DIO_REGMAP|DIGITAL_IFC_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SPI_TRANSACTION_GO</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0014</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x00E014
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_gpio_spi.v.</p>
</div>
<div class="info">
Starts a SPI transaction
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..0w</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_TRANSACTION_GO|SPI_DATA"></a>SPI_DATA</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
<p>Payload to be sent for the SPI transaction. If the payload is shorter than 32 bits,
it must be aligned to the MSbs in this field. LSbs are ignored in this scenario.</p>
</td>
</tr>
</table>
</div>
<div class="register">
<a name="DIG_IFC_REGMAP|SPI_STATUS"></a>
<h3 class="register">Offset 0x0018: SPI_STATUS Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('DIG_IFC_REGMAP|SPI_STATUS_in')">(<span id="show_DIG_IFC_REGMAP|SPI_STATUS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_DIG_IFC_REGMAP|SPI_STATUS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIGITAL_IFC_REGS">RADIO_DIO_REGMAP|DIGITAL_IFC_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">SPI_STATUS</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0018</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x00E018
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_gpio_spi.v.</p>
</div>
<div class="info">
Contains the status of the SPI engine.
</div>
<table class="bitfields" border="0" cellspacing="0" cellpadding="0">
<tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
<tr valign="top">
<td class="bits">31..25</td>
<td>
<p><span class="name">Reserved</span><span class="attr"> </span></p>
<p></p>
</td>
</tr>
<tr valign="top">
<td class="bits">24</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_STATUS|SPI_READY"></a>SPI_READY</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
<p>Indicates the SPI engine is ready to start a new SPI transaction.</p>
</td>
</tr>
<tr class='byte' valign="top">
<td class="bits">23..0</td>
<td>
<p><span class="name"><a name="DIG_IFC_REGMAP|SPI_STATUS|SPI_RESPONSE"></a>SPI_RESPONSE</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
<p>Records the response of the last completed SPI transaction.</p>
</td>
</tr>
</table>
</div>
</div>
</div>
<div class="regmap">
@@ -8020,7 +8506,7 @@ Total Offset =</td></tr>
Controls whether GPIO lines use the TX and RX state of an RF channel
(Classic ATR) or the daughterboard state the selector for the
@.GPIO_ATR_STATE.
<a href="#GPIO_ATR_REGMAP|ATR_STATE">ATR_STATE</a>.
</div>
@@ -8069,7 +8555,7 @@ Controls whether GPIO lines use the TX and RX state of an RF channel
<p><span class="name"><a name="GPIO_ATR_REGMAP|ATR_OPTION_REGISTRER|ATR_OPTION"></a>ATR_OPTION</span><span class="attr"> &nbsp;&nbsp;(initialvalue=0)</span></p>
<p>Sets the scheme in which RF states in the radio will control GPIO
lines. 0 = DB state is used. RF states are combined and the
GPIO state is driven based on all 16 @.GPIO_ATR_STATE registers.
GPIO state is driven based on all 16 <a href="#GPIO_ATR_REGMAP|ATR_STATE">ATR_STATE</a> registers.
1 = Each RF channel has its separate ATR state(Classic ATR).
Use register <a href="#GPIO_ATR_REGMAP|CLASSIC_ATR_CONFIG">CLASSIC_ATR_CONFIG</a> to indicate the RF channel
to which each GPIO line responds to.</p>
@@ -16322,6 +16808,69 @@ Window to access the DIO register map through the control port from the radio bl
</div>
</div>
<div class="register">
<a name="RADIO_DIO_REGMAP|DIGITAL_IFC_REGS"></a>
<h3 class="register">Offset 0x2000: DIGITAL_IFC_REGS Window (R|W)</h3>
<p class="offset_info">&nbsp;&nbsp;Target regmap = <a href="#DIG_IFC_REGMAP">DIG_IFC_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('RADIO_DIO_REGMAP|DIGITAL_IFC_REGS_in')">(<span id="show_RADIO_DIO_REGMAP|DIGITAL_IFC_REGS_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RADIO_DIO_REGMAP|DIGITAL_IFC_REGS_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIGITAL_IFC_REGS</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x2000</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;size=0x1000 (4 Kbytes)</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x00E000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p>
</div>
<div class="info">
Register space reserved for configuring a digital interface over the GPIO lines.
Currently, SPI is the only supported protocol.
</div>
</div>
</div>