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fpga: Add Replay Block to RFNoC Core Image

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Add the Replay RFNoC block to the RFNoC core image for x300, x310, n300,
n310, n320/n321, and e320. The Replay block is contained within its own
static connection, so previous default behavior is still supported.

Signed-off-by: mattprost <matt.prost@ni.com>


Original-commit: 437381bd2cfe137c5e7e2a70aab8226bfb1c70cd
This commit is contained in:
mattprost
2020-09-03 15:26:33 -05:00
committed by Aaron Rossetto
parent eab91d8ed0
commit 52172aaaf3
20 changed files with 2584 additions and 589 deletions
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top/e320/e320_rfnoc_image_core.yml
+16 -19
View File
@@ -25,11 +25,11 @@ stream_endpoints:
ep2: # Stream endpoint name
ctrl: False # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 8192 # Ingress buffer size for data
buff_size: 4096 # Ingress buffer size for data
ep3: # Stream endpoint name
ctrl: False # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 8192 # Ingress buffer size for data
buff_size: 4096 # Ingress buffer size for data
# A list of all NoC blocks in design
# ----------------------------------
@@ -44,16 +44,11 @@ noc_blocks:
NUM_PORTS: 2
radio0:
block_desc: 'radio_2x64.yml'
fifo0:
block_desc: 'axi_ram_fifo_2x64.yml'
replay0:
block_desc: 'replay.yml'
parameters:
# These parameters correspond to the memory interface on the E320
MEM_ADDR_W: 31
MEM_DATA_W: 64
MEM_CLK_RATE: "300e6"
# Create two non-overlapping 32 MB buffers by default
FIFO_ADDR_BASE: "{31'h02000000, 31'h00000000}"
FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF}"
NUM_PORTS: 2
MEM_ADDR_W: 31
# A list of all static connections in design
# ------------------------------------------
@@ -75,17 +70,19 @@ connections:
# radio0(1) to ep1 - RF1 RX
- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
- { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
# ep2 to fifo0(0)
- { srcblk: ep2, srcport: out0, dstblk: fifo0, dstport: in_0 }
- { srcblk: fifo0, srcport: out_0, dstblk: ep2, dstport: in0 }
# ep3 to fifo0(1)
- { srcblk: ep3, srcport: out0, dstblk: fifo0, dstport: in_1 }
- { srcblk: fifo0, srcport: out_1, dstblk: ep3, dstport: in0 }
# ep2 to replay0(0)
- { srcblk: ep2, srcport: out0, dstblk: replay0, dstport: in_0 }
# replay0(0) to ep2
- { srcblk: replay0, srcport: out_0, dstblk: ep2, dstport: in0 }
# ep3 to replay0(1)
- { srcblk: ep3, srcport: out0, dstblk: replay0, dstport: in_1 }
# replay0(1) to ep3
- { srcblk: replay0, srcport: out_1, dstblk: ep3, dstport: in0 }
# BSP Connections
- { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrl_port }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
- { srcblk: _device_, srcport: x300_radio, dstblk: radio0, dstport: x300_radio }
- { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper }
- { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram }
# A list of all clock domain connections in design
# ------------------------------------------------
@@ -98,4 +95,4 @@ clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }