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fpga: Add Replay Block to RFNoC Core Image

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Add the Replay RFNoC block to the RFNoC core image for x300, x310, n300,
n310, n320/n321, and e320. The Replay block is contained within its own
static connection, so previous default behavior is still supported.

Signed-off-by: mattprost <matt.prost@ni.com>


Original-commit: 437381bd2cfe137c5e7e2a70aab8226bfb1c70cd
This commit is contained in:
mattprost
2020-09-03 15:26:33 -05:00
committed by Aaron Rossetto
parent eab91d8ed0
commit 52172aaaf3
20 changed files with 2584 additions and 589 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/e320/Makefile.e320.inc
+3 -1
View File
@@ -34,12 +34,13 @@ include $(LIB_DIR)/dsp/Makefile.srcs
include $(LIB_DIR)/io_cap_gen/Makefile.srcs
include $(LIB_DIR)/rfnoc/Makefile.srcs
# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
# DUC, and of course the radio. Any other block needs to use the
# DUC, Replay, and of course the radio. Any other block needs to use the
# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
# If out-of-tree modules want to be compiled into this image, then they need to
# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
@@ -117,6 +118,7 @@ $(RFNOC_FRAMEWORK_SRCS) \
$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \
$(RFNOC_BLOCK_RADIO_SRCS) \
$(RFNOC_BLOCK_REPLAY_SRCS) \
$(abspath $(MB_XDC))
EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
top/e320/e320_rfnoc_image_core.v
+245 -248
View File
@@ -1,5 +1,5 @@
//
// Copyright 2019 Ettus Research, A National Instruments Brand
// Copyright 2020 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -7,9 +7,9 @@
// Module: rfnoc_image_core (for e320)
// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder)
// Re-running that tool will overwrite this file!
// File generated on: 2019-11-08T15:58:14.818480
// Source: ./e320/e320_rfnoc_image_core.yml
// Source SHA256: a2a7b213b5764ef6cb83fed9d744a415bf8a7f18a955fbe1f867590f5d8c5142
// File generated on: 2020-09-02T12:03:19.552358
// Source: ./e320_rfnoc_image_core.yml
// Source SHA256: c9b4c8ff60f4b6829b45cbb0beae5dbbb6ef64db4e20a54be556a99dd88a48cf
module rfnoc_image_core #(
parameter [15:0] PROTOVER = {8'd1, 8'd0}
@@ -45,50 +45,50 @@ module rfnoc_image_core #(
output wire [ 2-1:0] radio_tx_running,
// dram
input wire [ 1-1:0] axi_rst,
output wire [ 2-1:0] m_axi_awid,
output wire [ 64-1:0] m_axi_awaddr,
output wire [ 16-1:0] m_axi_awlen,
output wire [ 6-1:0] m_axi_awsize,
output wire [ 4-1:0] m_axi_awburst,
output wire [ 2-1:0] m_axi_awlock,
output wire [ 8-1:0] m_axi_awcache,
output wire [ 6-1:0] m_axi_awprot,
output wire [ 8-1:0] m_axi_awqos,
output wire [ 8-1:0] m_axi_awregion,
output wire [ 2-1:0] m_axi_awuser,
output wire [ 2-1:0] m_axi_awvalid,
input wire [ 2-1:0] m_axi_awready,
output wire [128-1:0] m_axi_wdata,
output wire [ 16-1:0] m_axi_wstrb,
output wire [ 2-1:0] m_axi_wlast,
output wire [ 2-1:0] m_axi_wuser,
output wire [ 2-1:0] m_axi_wvalid,
input wire [ 2-1:0] m_axi_wready,
input wire [ 2-1:0] m_axi_bid,
input wire [ 4-1:0] m_axi_bresp,
input wire [ 2-1:0] m_axi_buser,
input wire [ 2-1:0] m_axi_bvalid,
output wire [ 2-1:0] m_axi_bready,
output wire [ 2-1:0] m_axi_arid,
output wire [ 64-1:0] m_axi_araddr,
output wire [ 16-1:0] m_axi_arlen,
output wire [ 6-1:0] m_axi_arsize,
output wire [ 4-1:0] m_axi_arburst,
output wire [ 2-1:0] m_axi_arlock,
output wire [ 8-1:0] m_axi_arcache,
output wire [ 6-1:0] m_axi_arprot,
output wire [ 8-1:0] m_axi_arqos,
output wire [ 8-1:0] m_axi_arregion,
output wire [ 2-1:0] m_axi_aruser,
output wire [ 2-1:0] m_axi_arvalid,
input wire [ 2-1:0] m_axi_arready,
input wire [ 2-1:0] m_axi_rid,
input wire [128-1:0] m_axi_rdata,
input wire [ 4-1:0] m_axi_rresp,
input wire [ 2-1:0] m_axi_rlast,
input wire [ 2-1:0] m_axi_ruser,
input wire [ 2-1:0] m_axi_rvalid,
output wire [ 2-1:0] m_axi_rready,
output wire [ 4-1:0] m_axi_awid,
output wire [128-1:0] m_axi_awaddr,
output wire [ 32-1:0] m_axi_awlen,
output wire [ 12-1:0] m_axi_awsize,
output wire [ 8-1:0] m_axi_awburst,
output wire [ 4-1:0] m_axi_awlock,
output wire [ 16-1:0] m_axi_awcache,
output wire [ 12-1:0] m_axi_awprot,
output wire [ 16-1:0] m_axi_awqos,
output wire [ 16-1:0] m_axi_awregion,
output wire [ 4-1:0] m_axi_awuser,
output wire [ 4-1:0] m_axi_awvalid,
input wire [ 4-1:0] m_axi_awready,
output wire [256-1:0] m_axi_wdata,
output wire [ 32-1:0] m_axi_wstrb,
output wire [ 4-1:0] m_axi_wlast,
output wire [ 4-1:0] m_axi_wuser,
output wire [ 4-1:0] m_axi_wvalid,
input wire [ 4-1:0] m_axi_wready,
input wire [ 4-1:0] m_axi_bid,
input wire [ 8-1:0] m_axi_bresp,
input wire [ 4-1:0] m_axi_buser,
input wire [ 4-1:0] m_axi_bvalid,
output wire [ 4-1:0] m_axi_bready,
output wire [ 4-1:0] m_axi_arid,
output wire [128-1:0] m_axi_araddr,
output wire [ 32-1:0] m_axi_arlen,
output wire [ 12-1:0] m_axi_arsize,
output wire [ 8-1:0] m_axi_arburst,
output wire [ 4-1:0] m_axi_arlock,
output wire [ 16-1:0] m_axi_arcache,
output wire [ 12-1:0] m_axi_arprot,
output wire [ 16-1:0] m_axi_arqos,
output wire [ 16-1:0] m_axi_arregion,
output wire [ 4-1:0] m_axi_aruser,
output wire [ 4-1:0] m_axi_arvalid,
input wire [ 4-1:0] m_axi_arready,
input wire [ 4-1:0] m_axi_rid,
input wire [256-1:0] m_axi_rdata,
input wire [ 8-1:0] m_axi_rresp,
input wire [ 4-1:0] m_axi_rlast,
input wire [ 4-1:0] m_axi_ruser,
input wire [ 4-1:0] m_axi_rvalid,
output wire [ 4-1:0] m_axi_rready,
// Transport 0 (eth 10G)
input wire [64-1:0] s_eth_tdata,
input wire s_eth_tlast,
@@ -329,7 +329,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1),
.INST_NUM (2),
.CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (13),
.INGRESS_BUFF_SIZE (12),
.MTU (MTU),
.REPORT_STRM_ERRS (1)
) ep2_i (
@@ -390,7 +390,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1),
.INST_NUM (3),
.CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (13),
.INGRESS_BUFF_SIZE (12),
.MTU (MTU),
.REPORT_STRM_ERRS (1)
) ep3_i (
@@ -451,10 +451,10 @@ module rfnoc_image_core #(
wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ;
wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid;
wire m_radio0_ctrl_tready, s_radio0_ctrl_tready;
wire [31:0] m_fifo0_ctrl_tdata , s_fifo0_ctrl_tdata ;
wire m_fifo0_ctrl_tlast , s_fifo0_ctrl_tlast ;
wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid;
wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready;
wire [31:0] m_replay0_ctrl_tdata , s_replay0_ctrl_tdata ;
wire m_replay0_ctrl_tlast , s_replay0_ctrl_tlast ;
wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid;
wire m_replay0_ctrl_tready, s_replay0_ctrl_tready;
axis_ctrl_crossbar_nxn #(
.WIDTH (32),
@@ -467,14 +467,14 @@ module rfnoc_image_core #(
) ctrl_xb_i (
.clk (rfnoc_ctrl_clk),
.reset (rfnoc_ctrl_rst),
.s_axis_tdata ({m_fifo0_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
.s_axis_tvalid ({m_fifo0_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
.s_axis_tlast ({m_fifo0_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
.s_axis_tready ({m_fifo0_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
.m_axis_tdata ({s_fifo0_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
.m_axis_tvalid ({s_fifo0_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
.m_axis_tlast ({s_fifo0_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
.m_axis_tready ({s_fifo0_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
.s_axis_tdata ({m_replay0_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
.s_axis_tvalid ({m_replay0_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
.s_axis_tlast ({m_replay0_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
.s_axis_tready ({m_replay0_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
.m_axis_tdata ({s_replay0_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
.m_axis_tvalid ({s_replay0_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
.m_axis_tlast ({s_replay0_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
.m_axis_tready ({s_replay0_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
.deadlock_detected()
);
@@ -702,144 +702,141 @@ module rfnoc_image_core #(
// ----------------------------------------------------
// fifo0
// replay0
// ----------------------------------------------------
wire fifo0_mem_clk;
wire [CHDR_W-1:0] s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ;
wire s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ;
wire s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid;
wire s_fifo0_in_1_tready, s_fifo0_in_0_tready;
wire [CHDR_W-1:0] m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ;
wire m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ;
wire m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid;
wire m_fifo0_out_1_tready, m_fifo0_out_0_tready;
wire replay0_mem_clk;
wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
wire s_replay0_in_1_tready, s_replay0_in_0_tready;
wire [CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
wire m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram
wire [ 1-1:0] fifo0_axi_rst;
wire [ 2-1:0] fifo0_m_axi_awid;
wire [ 64-1:0] fifo0_m_axi_awaddr;
wire [ 16-1:0] fifo0_m_axi_awlen;
wire [ 6-1:0] fifo0_m_axi_awsize;
wire [ 4-1:0] fifo0_m_axi_awburst;
wire [ 2-1:0] fifo0_m_axi_awlock;
wire [ 8-1:0] fifo0_m_axi_awcache;
wire [ 6-1:0] fifo0_m_axi_awprot;
wire [ 8-1:0] fifo0_m_axi_awqos;
wire [ 8-1:0] fifo0_m_axi_awregion;
wire [ 2-1:0] fifo0_m_axi_awuser;
wire [ 2-1:0] fifo0_m_axi_awvalid;
wire [ 2-1:0] fifo0_m_axi_awready;
wire [128-1:0] fifo0_m_axi_wdata;
wire [ 16-1:0] fifo0_m_axi_wstrb;
wire [ 2-1:0] fifo0_m_axi_wlast;
wire [ 2-1:0] fifo0_m_axi_wuser;
wire [ 2-1:0] fifo0_m_axi_wvalid;
wire [ 2-1:0] fifo0_m_axi_wready;
wire [ 2-1:0] fifo0_m_axi_bid;
wire [ 4-1:0] fifo0_m_axi_bresp;
wire [ 2-1:0] fifo0_m_axi_buser;
wire [ 2-1:0] fifo0_m_axi_bvalid;
wire [ 2-1:0] fifo0_m_axi_bready;
wire [ 2-1:0] fifo0_m_axi_arid;
wire [ 64-1:0] fifo0_m_axi_araddr;
wire [ 16-1:0] fifo0_m_axi_arlen;
wire [ 6-1:0] fifo0_m_axi_arsize;
wire [ 4-1:0] fifo0_m_axi_arburst;
wire [ 2-1:0] fifo0_m_axi_arlock;
wire [ 8-1:0] fifo0_m_axi_arcache;
wire [ 6-1:0] fifo0_m_axi_arprot;
wire [ 8-1:0] fifo0_m_axi_arqos;
wire [ 8-1:0] fifo0_m_axi_arregion;
wire [ 2-1:0] fifo0_m_axi_aruser;
wire [ 2-1:0] fifo0_m_axi_arvalid;
wire [ 2-1:0] fifo0_m_axi_arready;
wire [ 2-1:0] fifo0_m_axi_rid;
wire [128-1:0] fifo0_m_axi_rdata;
wire [ 4-1:0] fifo0_m_axi_rresp;
wire [ 2-1:0] fifo0_m_axi_rlast;
wire [ 2-1:0] fifo0_m_axi_ruser;
wire [ 2-1:0] fifo0_m_axi_rvalid;
wire [ 2-1:0] fifo0_m_axi_rready;
wire [ 1-1:0] replay0_axi_rst;
wire [ 4-1:0] replay0_m_axi_awid;
wire [128-1:0] replay0_m_axi_awaddr;
wire [ 32-1:0] replay0_m_axi_awlen;
wire [ 12-1:0] replay0_m_axi_awsize;
wire [ 8-1:0] replay0_m_axi_awburst;
wire [ 4-1:0] replay0_m_axi_awlock;
wire [ 16-1:0] replay0_m_axi_awcache;
wire [ 12-1:0] replay0_m_axi_awprot;
wire [ 16-1:0] replay0_m_axi_awqos;
wire [ 16-1:0] replay0_m_axi_awregion;
wire [ 4-1:0] replay0_m_axi_awuser;
wire [ 4-1:0] replay0_m_axi_awvalid;
wire [ 4-1:0] replay0_m_axi_awready;
wire [256-1:0] replay0_m_axi_wdata;
wire [ 32-1:0] replay0_m_axi_wstrb;
wire [ 4-1:0] replay0_m_axi_wlast;
wire [ 4-1:0] replay0_m_axi_wuser;
wire [ 4-1:0] replay0_m_axi_wvalid;
wire [ 4-1:0] replay0_m_axi_wready;
wire [ 4-1:0] replay0_m_axi_bid;
wire [ 8-1:0] replay0_m_axi_bresp;
wire [ 4-1:0] replay0_m_axi_buser;
wire [ 4-1:0] replay0_m_axi_bvalid;
wire [ 4-1:0] replay0_m_axi_bready;
wire [ 4-1:0] replay0_m_axi_arid;
wire [128-1:0] replay0_m_axi_araddr;
wire [ 32-1:0] replay0_m_axi_arlen;
wire [ 12-1:0] replay0_m_axi_arsize;
wire [ 8-1:0] replay0_m_axi_arburst;
wire [ 4-1:0] replay0_m_axi_arlock;
wire [ 16-1:0] replay0_m_axi_arcache;
wire [ 12-1:0] replay0_m_axi_arprot;
wire [ 16-1:0] replay0_m_axi_arqos;
wire [ 16-1:0] replay0_m_axi_arregion;
wire [ 4-1:0] replay0_m_axi_aruser;
wire [ 4-1:0] replay0_m_axi_arvalid;
wire [ 4-1:0] replay0_m_axi_arready;
wire [ 4-1:0] replay0_m_axi_rid;
wire [256-1:0] replay0_m_axi_rdata;
wire [ 8-1:0] replay0_m_axi_rresp;
wire [ 4-1:0] replay0_m_axi_rlast;
wire [ 4-1:0] replay0_m_axi_ruser;
wire [ 4-1:0] replay0_m_axi_rvalid;
wire [ 4-1:0] replay0_m_axi_rready;
rfnoc_block_axi_ram_fifo #(
rfnoc_block_replay #(
.THIS_PORTID(5),
.CHDR_W(CHDR_W),
.NUM_PORTS(2),
.MEM_ADDR_W(31),
.MEM_DATA_W(64),
.MEM_CLK_RATE(300e6),
.FIFO_ADDR_BASE({31'h02000000, 31'h00000000}),
.FIFO_ADDR_MASK({31'h01FFFFFF, 31'h01FFFFFF}),
.NUM_PORTS(2),
.MTU(MTU)
) b_fifo0_3 (
) b_replay0_3 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.mem_clk(fifo0_mem_clk),
.mem_clk(replay0_mem_clk),
.rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]),
.rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]),
.axi_rst(fifo0_axi_rst),
.m_axi_awid(fifo0_m_axi_awid),
.m_axi_awaddr(fifo0_m_axi_awaddr),
.m_axi_awlen(fifo0_m_axi_awlen),
.m_axi_awsize(fifo0_m_axi_awsize),
.m_axi_awburst(fifo0_m_axi_awburst),
.m_axi_awlock(fifo0_m_axi_awlock),
.m_axi_awcache(fifo0_m_axi_awcache),
.m_axi_awprot(fifo0_m_axi_awprot),
.m_axi_awqos(fifo0_m_axi_awqos),
.m_axi_awregion(fifo0_m_axi_awregion),
.m_axi_awuser(fifo0_m_axi_awuser),
.m_axi_awvalid(fifo0_m_axi_awvalid),
.m_axi_awready(fifo0_m_axi_awready),
.m_axi_wdata(fifo0_m_axi_wdata),
.m_axi_wstrb(fifo0_m_axi_wstrb),
.m_axi_wlast(fifo0_m_axi_wlast),
.m_axi_wuser(fifo0_m_axi_wuser),
.m_axi_wvalid(fifo0_m_axi_wvalid),
.m_axi_wready(fifo0_m_axi_wready),
.m_axi_bid(fifo0_m_axi_bid),
.m_axi_bresp(fifo0_m_axi_bresp),
.m_axi_buser(fifo0_m_axi_buser),
.m_axi_bvalid(fifo0_m_axi_bvalid),
.m_axi_bready(fifo0_m_axi_bready),
.m_axi_arid(fifo0_m_axi_arid),
.m_axi_araddr(fifo0_m_axi_araddr),
.m_axi_arlen(fifo0_m_axi_arlen),
.m_axi_arsize(fifo0_m_axi_arsize),
.m_axi_arburst(fifo0_m_axi_arburst),
.m_axi_arlock(fifo0_m_axi_arlock),
.m_axi_arcache(fifo0_m_axi_arcache),
.m_axi_arprot(fifo0_m_axi_arprot),
.m_axi_arqos(fifo0_m_axi_arqos),
.m_axi_arregion(fifo0_m_axi_arregion),
.m_axi_aruser(fifo0_m_axi_aruser),
.m_axi_arvalid(fifo0_m_axi_arvalid),
.m_axi_arready(fifo0_m_axi_arready),
.m_axi_rid(fifo0_m_axi_rid),
.m_axi_rdata(fifo0_m_axi_rdata),
.m_axi_rresp(fifo0_m_axi_rresp),
.m_axi_rlast(fifo0_m_axi_rlast),
.m_axi_ruser(fifo0_m_axi_ruser),
.m_axi_rvalid(fifo0_m_axi_rvalid),
.m_axi_rready(fifo0_m_axi_rready),
.axi_rst(replay0_axi_rst),
.m_axi_awid(replay0_m_axi_awid),
.m_axi_awaddr(replay0_m_axi_awaddr),
.m_axi_awlen(replay0_m_axi_awlen),
.m_axi_awsize(replay0_m_axi_awsize),
.m_axi_awburst(replay0_m_axi_awburst),
.m_axi_awlock(replay0_m_axi_awlock),
.m_axi_awcache(replay0_m_axi_awcache),
.m_axi_awprot(replay0_m_axi_awprot),
.m_axi_awqos(replay0_m_axi_awqos),
.m_axi_awregion(replay0_m_axi_awregion),
.m_axi_awuser(replay0_m_axi_awuser),
.m_axi_awvalid(replay0_m_axi_awvalid),
.m_axi_awready(replay0_m_axi_awready),
.m_axi_wdata(replay0_m_axi_wdata),
.m_axi_wstrb(replay0_m_axi_wstrb),
.m_axi_wlast(replay0_m_axi_wlast),
.m_axi_wuser(replay0_m_axi_wuser),
.m_axi_wvalid(replay0_m_axi_wvalid),
.m_axi_wready(replay0_m_axi_wready),
.m_axi_bid(replay0_m_axi_bid),
.m_axi_bresp(replay0_m_axi_bresp),
.m_axi_buser(replay0_m_axi_buser),
.m_axi_bvalid(replay0_m_axi_bvalid),
.m_axi_bready(replay0_m_axi_bready),
.m_axi_arid(replay0_m_axi_arid),
.m_axi_araddr(replay0_m_axi_araddr),
.m_axi_arlen(replay0_m_axi_arlen),
.m_axi_arsize(replay0_m_axi_arsize),
.m_axi_arburst(replay0_m_axi_arburst),
.m_axi_arlock(replay0_m_axi_arlock),
.m_axi_arcache(replay0_m_axi_arcache),
.m_axi_arprot(replay0_m_axi_arprot),
.m_axi_arqos(replay0_m_axi_arqos),
.m_axi_arregion(replay0_m_axi_arregion),
.m_axi_aruser(replay0_m_axi_aruser),
.m_axi_arvalid(replay0_m_axi_arvalid),
.m_axi_arready(replay0_m_axi_arready),
.m_axi_rid(replay0_m_axi_rid),
.m_axi_rdata(replay0_m_axi_rdata),
.m_axi_rresp(replay0_m_axi_rresp),
.m_axi_rlast(replay0_m_axi_rlast),
.m_axi_ruser(replay0_m_axi_ruser),
.m_axi_rvalid(replay0_m_axi_rvalid),
.m_axi_rready(replay0_m_axi_rready),
.s_rfnoc_chdr_tdata ({s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }),
.s_rfnoc_chdr_tvalid({s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}),
.s_rfnoc_chdr_tready({s_fifo0_in_1_tready, s_fifo0_in_0_tready}),
.m_rfnoc_chdr_tdata ({m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }),
.m_rfnoc_chdr_tlast ({m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }),
.m_rfnoc_chdr_tvalid({m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}),
.m_rfnoc_chdr_tready({m_fifo0_out_1_tready, m_fifo0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid(s_fifo0_ctrl_tvalid),
.s_rfnoc_ctrl_tready(s_fifo0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid(m_fifo0_ctrl_tvalid),
.m_rfnoc_ctrl_tready(m_fifo0_ctrl_tready)
.s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
.s_rfnoc_chdr_tvalid({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
.s_rfnoc_chdr_tready({s_replay0_in_1_tready, s_replay0_in_0_tready}),
.m_rfnoc_chdr_tdata ({m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
.m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
.m_rfnoc_chdr_tvalid({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
.m_rfnoc_chdr_tready({m_replay0_out_1_tready, m_replay0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid(s_replay0_ctrl_tvalid),
.s_rfnoc_ctrl_tready(s_replay0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid(m_replay0_ctrl_tvalid),
.m_rfnoc_ctrl_tready(m_replay0_ctrl_tready)
);
@@ -886,25 +883,25 @@ module rfnoc_image_core #(
assign s_ep1_in0_tvalid = m_ddc0_out_1_tvalid;
assign m_ddc0_out_1_tready = s_ep1_in0_tready;
assign s_fifo0_in_0_tdata = m_ep2_out0_tdata ;
assign s_fifo0_in_0_tlast = m_ep2_out0_tlast ;
assign s_fifo0_in_0_tvalid = m_ep2_out0_tvalid;
assign m_ep2_out0_tready = s_fifo0_in_0_tready;
assign s_replay0_in_0_tdata = m_ep2_out0_tdata ;
assign s_replay0_in_0_tlast = m_ep2_out0_tlast ;
assign s_replay0_in_0_tvalid = m_ep2_out0_tvalid;
assign m_ep2_out0_tready = s_replay0_in_0_tready;
assign s_ep2_in0_tdata = m_fifo0_out_0_tdata ;
assign s_ep2_in0_tlast = m_fifo0_out_0_tlast ;
assign s_ep2_in0_tvalid = m_fifo0_out_0_tvalid;
assign m_fifo0_out_0_tready = s_ep2_in0_tready;
assign s_ep2_in0_tdata = m_replay0_out_0_tdata ;
assign s_ep2_in0_tlast = m_replay0_out_0_tlast ;
assign s_ep2_in0_tvalid = m_replay0_out_0_tvalid;
assign m_replay0_out_0_tready = s_ep2_in0_tready;
assign s_fifo0_in_1_tdata = m_ep3_out0_tdata ;
assign s_fifo0_in_1_tlast = m_ep3_out0_tlast ;
assign s_fifo0_in_1_tvalid = m_ep3_out0_tvalid;
assign m_ep3_out0_tready = s_fifo0_in_1_tready;
assign s_replay0_in_1_tdata = m_ep3_out0_tdata ;
assign s_replay0_in_1_tlast = m_ep3_out0_tlast ;
assign s_replay0_in_1_tvalid = m_ep3_out0_tvalid;
assign m_ep3_out0_tready = s_replay0_in_1_tready;
assign s_ep3_in0_tdata = m_fifo0_out_1_tdata ;
assign s_ep3_in0_tlast = m_fifo0_out_1_tlast ;
assign s_ep3_in0_tvalid = m_fifo0_out_1_tvalid;
assign m_fifo0_out_1_tready = s_ep3_in0_tready;
assign s_ep3_in0_tdata = m_replay0_out_1_tdata ;
assign s_ep3_in0_tlast = m_replay0_out_1_tlast ;
assign s_ep3_in0_tvalid = m_replay0_out_1_tvalid;
assign m_replay0_out_1_tready = s_ep3_in0_tready;
// ----------------------------------------------------
@@ -917,7 +914,7 @@ module rfnoc_image_core #(
assign radio0_radio_clk = radio_clk;
assign duc0_ce_clk = rfnoc_chdr_clk;
assign ddc0_ce_clk = rfnoc_chdr_clk;
assign fifo0_mem_clk = dram_clk;
assign replay0_mem_clk = dram_clk;
// ----------------------------------------------------
@@ -935,6 +932,52 @@ module rfnoc_image_core #(
assign radio0_m_ctrlport_resp_status = m_ctrlport_resp_status;
assign radio0_m_ctrlport_resp_data = m_ctrlport_resp_data;
assign replay0_axi_rst = axi_rst;
assign m_axi_awid = replay0_m_axi_awid;
assign m_axi_awaddr = replay0_m_axi_awaddr;
assign m_axi_awlen = replay0_m_axi_awlen;
assign m_axi_awsize = replay0_m_axi_awsize;
assign m_axi_awburst = replay0_m_axi_awburst;
assign m_axi_awlock = replay0_m_axi_awlock;
assign m_axi_awcache = replay0_m_axi_awcache;
assign m_axi_awprot = replay0_m_axi_awprot;
assign m_axi_awqos = replay0_m_axi_awqos;
assign m_axi_awregion = replay0_m_axi_awregion;
assign m_axi_awuser = replay0_m_axi_awuser;
assign m_axi_awvalid = replay0_m_axi_awvalid;
assign replay0_m_axi_awready = m_axi_awready;
assign m_axi_wdata = replay0_m_axi_wdata;
assign m_axi_wstrb = replay0_m_axi_wstrb;
assign m_axi_wlast = replay0_m_axi_wlast;
assign m_axi_wuser = replay0_m_axi_wuser;
assign m_axi_wvalid = replay0_m_axi_wvalid;
assign replay0_m_axi_wready = m_axi_wready;
assign replay0_m_axi_bid = m_axi_bid;
assign replay0_m_axi_bresp = m_axi_bresp;
assign replay0_m_axi_buser = m_axi_buser;
assign replay0_m_axi_bvalid = m_axi_bvalid;
assign m_axi_bready = replay0_m_axi_bready;
assign m_axi_arid = replay0_m_axi_arid;
assign m_axi_araddr = replay0_m_axi_araddr;
assign m_axi_arlen = replay0_m_axi_arlen;
assign m_axi_arsize = replay0_m_axi_arsize;
assign m_axi_arburst = replay0_m_axi_arburst;
assign m_axi_arlock = replay0_m_axi_arlock;
assign m_axi_arcache = replay0_m_axi_arcache;
assign m_axi_arprot = replay0_m_axi_arprot;
assign m_axi_arqos = replay0_m_axi_arqos;
assign m_axi_arregion = replay0_m_axi_arregion;
assign m_axi_aruser = replay0_m_axi_aruser;
assign m_axi_arvalid = replay0_m_axi_arvalid;
assign replay0_m_axi_arready = m_axi_arready;
assign replay0_m_axi_rid = m_axi_rid;
assign replay0_m_axi_rdata = m_axi_rdata;
assign replay0_m_axi_rresp = m_axi_rresp;
assign replay0_m_axi_rlast = m_axi_rlast;
assign replay0_m_axi_ruser = m_axi_ruser;
assign replay0_m_axi_rvalid = m_axi_rvalid;
assign m_axi_rready = replay0_m_axi_rready;
assign radio0_radio_rx_data = radio_rx_data;
assign radio0_radio_rx_stb = radio_rx_stb;
assign radio_rx_running = radio0_radio_rx_running;
@@ -942,52 +985,6 @@ module rfnoc_image_core #(
assign radio0_radio_tx_stb = radio_tx_stb;
assign radio_tx_running = radio0_radio_tx_running;
assign fifo0_axi_rst = axi_rst;
assign m_axi_awid = fifo0_m_axi_awid;
assign m_axi_awaddr = fifo0_m_axi_awaddr;
assign m_axi_awlen = fifo0_m_axi_awlen;
assign m_axi_awsize = fifo0_m_axi_awsize;
assign m_axi_awburst = fifo0_m_axi_awburst;
assign m_axi_awlock = fifo0_m_axi_awlock;
assign m_axi_awcache = fifo0_m_axi_awcache;
assign m_axi_awprot = fifo0_m_axi_awprot;
assign m_axi_awqos = fifo0_m_axi_awqos;
assign m_axi_awregion = fifo0_m_axi_awregion;
assign m_axi_awuser = fifo0_m_axi_awuser;
assign m_axi_awvalid = fifo0_m_axi_awvalid;
assign fifo0_m_axi_awready = m_axi_awready;
assign m_axi_wdata = fifo0_m_axi_wdata;
assign m_axi_wstrb = fifo0_m_axi_wstrb;
assign m_axi_wlast = fifo0_m_axi_wlast;
assign m_axi_wuser = fifo0_m_axi_wuser;
assign m_axi_wvalid = fifo0_m_axi_wvalid;
assign fifo0_m_axi_wready = m_axi_wready;
assign fifo0_m_axi_bid = m_axi_bid;
assign fifo0_m_axi_bresp = m_axi_bresp;
assign fifo0_m_axi_buser = m_axi_buser;
assign fifo0_m_axi_bvalid = m_axi_bvalid;
assign m_axi_bready = fifo0_m_axi_bready;
assign m_axi_arid = fifo0_m_axi_arid;
assign m_axi_araddr = fifo0_m_axi_araddr;
assign m_axi_arlen = fifo0_m_axi_arlen;
assign m_axi_arsize = fifo0_m_axi_arsize;
assign m_axi_arburst = fifo0_m_axi_arburst;
assign m_axi_arlock = fifo0_m_axi_arlock;
assign m_axi_arcache = fifo0_m_axi_arcache;
assign m_axi_arprot = fifo0_m_axi_arprot;
assign m_axi_arqos = fifo0_m_axi_arqos;
assign m_axi_arregion = fifo0_m_axi_arregion;
assign m_axi_aruser = fifo0_m_axi_aruser;
assign m_axi_arvalid = fifo0_m_axi_arvalid;
assign fifo0_m_axi_arready = m_axi_arready;
assign fifo0_m_axi_rid = m_axi_rid;
assign fifo0_m_axi_rdata = m_axi_rdata;
assign fifo0_m_axi_rresp = m_axi_rresp;
assign fifo0_m_axi_rlast = m_axi_rlast;
assign fifo0_m_axi_ruser = m_axi_ruser;
assign fifo0_m_axi_rvalid = m_axi_rvalid;
assign m_axi_rready = fifo0_m_axi_rready;
// Broadcaster/Listener Connections:
assign radio0_radio_time = radio_time;
top/e320/e320_rfnoc_image_core.yml
+16 -19
View File
@@ -25,11 +25,11 @@ stream_endpoints:
ep2: # Stream endpoint name
ctrl: False # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 8192 # Ingress buffer size for data
buff_size: 4096 # Ingress buffer size for data
ep3: # Stream endpoint name
ctrl: False # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 8192 # Ingress buffer size for data
buff_size: 4096 # Ingress buffer size for data
# A list of all NoC blocks in design
# ----------------------------------
@@ -44,16 +44,11 @@ noc_blocks:
NUM_PORTS: 2
radio0:
block_desc: 'radio_2x64.yml'
fifo0:
block_desc: 'axi_ram_fifo_2x64.yml'
replay0:
block_desc: 'replay.yml'
parameters:
# These parameters correspond to the memory interface on the E320
MEM_ADDR_W: 31
MEM_DATA_W: 64
MEM_CLK_RATE: "300e6"
# Create two non-overlapping 32 MB buffers by default
FIFO_ADDR_BASE: "{31'h02000000, 31'h00000000}"
FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF}"
NUM_PORTS: 2
MEM_ADDR_W: 31
# A list of all static connections in design
# ------------------------------------------
@@ -75,17 +70,19 @@ connections:
# radio0(1) to ep1 - RF1 RX
- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
- { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
# ep2 to fifo0(0)
- { srcblk: ep2, srcport: out0, dstblk: fifo0, dstport: in_0 }
- { srcblk: fifo0, srcport: out_0, dstblk: ep2, dstport: in0 }
# ep3 to fifo0(1)
- { srcblk: ep3, srcport: out0, dstblk: fifo0, dstport: in_1 }
- { srcblk: fifo0, srcport: out_1, dstblk: ep3, dstport: in0 }
# ep2 to replay0(0)
- { srcblk: ep2, srcport: out0, dstblk: replay0, dstport: in_0 }
# replay0(0) to ep2
- { srcblk: replay0, srcport: out_0, dstblk: ep2, dstport: in0 }
# ep3 to replay0(1)
- { srcblk: ep3, srcport: out0, dstblk: replay0, dstport: in_1 }
# replay0(1) to ep3
- { srcblk: replay0, srcport: out_1, dstblk: ep3, dstport: in0 }
# BSP Connections
- { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrl_port }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
- { srcblk: _device_, srcport: x300_radio, dstblk: radio0, dstport: x300_radio }
- { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper }
- { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram }
# A list of all clock domain connections in design
# ------------------------------------------------
@@ -98,4 +95,4 @@ clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }