fpga: tools: Add option to save Vivado project

Original-commit: 8f9beccebe54a21d4993f8298c184426671624b0

tools/make/viv_design_builder.mak

@@ -25,6 +25,7 @@ BUILD_VIVADO_DESIGN = \
 	export VIV_TOP_MODULE=$(2); \
 	export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \
 	export VIV_MODE=$(VIVADO_MODE); \
+	export VIV_SAVE=$(VIVADO_SAVE); \
 	export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
 	export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
 	export VIV_INCR_BUILD=$(INCR_BUILD); \

tools/make/viv_preamble.mak

@@ -52,6 +52,15 @@ else
 VIVADO_MODE=batch
 endif
 
+# -------------------------------------------------------------------
+# Project mode switch. Calling with PROJECT:=1 will use Vivado project file
+# -------------------------------------------------------------------
+ifeq ($(PROJECT),1)
+VIVADO_PROJECT=1
+else
+VIVADO_PROJECT=0
+endif
+
 # -------------------------------------------------------------------
 # Toolchain dependency target
 # -------------------------------------------------------------------

tools/scripts/viv_utils.tcl

@@ -26,6 +26,7 @@ namespace eval ::vivado_utils {
     variable g_output_dir   $::env(VIV_OUTPUT_DIR)
     variable g_source_files $::env(VIV_DESIGN_SRCS)
     variable g_vivado_mode  $::env(VIV_MODE)
+    variable g_project_save $::env(VIV_SAVE)
 
     # Optional environment variables
     variable g_verilog_defs ""
@@ -46,12 +47,13 @@ proc ::vivado_utils::initialize_project { {save_to_disk 0} } {
     variable g_part_name
     variable g_output_dir
     variable g_source_files
+    variable g_project_save
 
     variable bd_files ""
 
     file delete -force $g_output_dir/build.rpt
 
-    if {$save_to_disk == 1} {
+    if {$save_to_disk == 1 || $g_project_save == 1} {
         puts "BUILDER: Creating Vivado project ${g_top_module}_project.xpr for part $g_part_name"
         create_project -part $g_part_name ${g_top_module}_project
     } else {