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fpga: tools: Add option to save Vivado project

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Original-commit: 8f9beccebe54a21d4993f8298c184426671624b0
This commit is contained in:
Wade Fife
2024-03-15 20:05:39 -05:00
parent 5c23c71e44
commit 51865aa003
3 changed files with 13 additions and 1 deletions
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tools/make/viv_design_builder.mak
+1
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@@ -25,6 +25,7 @@ BUILD_VIVADO_DESIGN = \
export VIV_TOP_MODULE=$(2); \
export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \
export VIV_MODE=$(VIVADO_MODE); \
export VIV_SAVE=$(VIVADO_SAVE); \
export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
export VIV_INCR_BUILD=$(INCR_BUILD); \
tools/make/viv_preamble.mak
+9
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@@ -52,6 +52,15 @@ else
VIVADO_MODE=batch
endif
# -------------------------------------------------------------------
# Project mode switch. Calling with PROJECT:=1 will use Vivado project file
# -------------------------------------------------------------------
ifeq ($(PROJECT),1)
VIVADO_PROJECT=1
else
VIVADO_PROJECT=0
endif
# -------------------------------------------------------------------
# Toolchain dependency target
# -------------------------------------------------------------------