fpga: x4xx: replace ADC/DAC info by RFDC memory
Original-commit: 6c6d52fd655b144aa5ee581edae7911dc734854e
This commit is contained in:
Max Köhler
committed by
Jörg Hofrichter
Jörg Hofrichter
parent
37b8b0d017
commit
50f20ef4ab
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//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axi_rfdc_info_memory
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//
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// Description:
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//
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// This module is a bridge between the RFDC info memory and the AXI4-Lite bus.
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// The RFDC info memory contains information about the ADC / DAC configuration
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// of the RFDC block and their respective logical RFNoC channels.
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//
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// Parameters:
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//
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// TIMEOUT Control port will timeout after 2^TIMEOUT AXI clock cycles
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// AXI_ADDR_WIDTH Width of the AXI bus. Aliasing occurs if AXI_ADDR_WIDTH > CTRLPORT_AWIDTH
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// CTRLPORT_AWIDTH Number of address LSBs forwarded to m_ctrlport_req_addr
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//
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module axi_rfdc_info_memory #(
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parameter TIMEOUT = 2,
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parameter AXI_ADDR_WIDTH = 6,
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parameter CTRLPORT_AWIDTH = 6
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)(
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//Clock and reset
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input wire s_axi_aclk,
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input wire s_axi_aresetn,
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// AXI4-Lite: Write address port (domain: s_axi_aclk)
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s AWADDR" *)
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input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s AWVALID" *)
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input wire s_axi_awvalid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s AWREADY" *)
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output wire s_axi_awready,
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// AXI4-Lite: Write data port (domain: s_axi_aclk)
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s WDATA" *)
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input wire [31:0] s_axi_wdata,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s WSTRB" *)
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input wire [ 3:0] s_axi_wstrb,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s WVALID" *)
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input wire s_axi_wvalid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s WREADY" *)
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output wire s_axi_wready,
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// AXI4-Lite: Write response port (domain: s_axi_aclk)
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s BRESP" *)
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output wire [ 1:0] s_axi_bresp,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s BVALID" *)
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output wire s_axi_bvalid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s BREADY" *)
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input wire s_axi_bready,
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// AXI4-Lite: Read address port (domain: s_axi_aclk)
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s ARADDR" *)
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input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s ARVALID" *)
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input wire s_axi_arvalid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s ARREADY" *)
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output wire s_axi_arready,
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// AXI4-Lite: Read data port (domain: s_axi_aclk)
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s RDATA" *)
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output wire[31:0] s_axi_rdata,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s RRESP" *)
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output wire[ 1:0] s_axi_rresp,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s RVALID" *)
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output wire s_axi_rvalid,
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s RREADY" *)
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input wire s_axi_rready
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);
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// synchronize reset
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wire resetn;
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reset_sync reset_syncx (
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.clk (s_axi_aclk), //input wire
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.reset_in (s_axi_aresetn), //input wire
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.reset_out(resetn) //output reg
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);
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//ctrlport signals between memory and axi ctrlport bridge
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wire [19:0] ctrlport_req_addr;
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wire [ 3:0] ctrlport_req_byte_en;
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wire [31:0] ctrlport_req_data;
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wire ctrlport_req_rd;
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wire ctrlport_req_wr;
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wire ctrlport_resp_ack;
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wire [31:0] ctrlport_resp_data;
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wire [ 1:0] ctrlport_resp_status;
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axil_ctrlport_master #(
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.TIMEOUT (TIMEOUT), //integer:=10
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.AXI_AWIDTH (AXI_ADDR_WIDTH), //integer:=17
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.CTRLPORT_AWIDTH(CTRLPORT_AWIDTH) //integer:=17
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) axil_ctrlport_masterx (
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.s_axi_aclk (s_axi_aclk), //input wire
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.s_axi_aresetn (s_axi_aresetn), //input wire
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.s_axi_awaddr (s_axi_awaddr), //input wire[(AXI_ADDR_WIDTH-1):0]
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.s_axi_awvalid (s_axi_awvalid), //input wire
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.s_axi_awready (s_axi_awready), //output reg
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.s_axi_wdata (s_axi_wdata), //input wire[31:0]
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.s_axi_wstrb (s_axi_wstrb), //input wire[3:0]
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.s_axi_wvalid (s_axi_wvalid), //input wire
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.s_axi_wready (s_axi_wready), //output reg
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.s_axi_bresp (s_axi_bresp), //output reg[1:0]
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.s_axi_bvalid (s_axi_bvalid), //output reg
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.s_axi_bready (s_axi_bready), //input wire
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.s_axi_araddr (s_axi_araddr), //input wire[(AXI_ADDR_WIDTH-1):0]
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.s_axi_arvalid (s_axi_arvalid), //input wire
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.s_axi_arready (s_axi_arready), //output reg
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.s_axi_rdata (s_axi_rdata), //output reg[31:0]
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.s_axi_rresp (s_axi_rresp), //output reg[1:0]
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.s_axi_rvalid (s_axi_rvalid), //output reg
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.s_axi_rready (s_axi_rready), //input wire
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.m_ctrlport_req_wr (ctrlport_req_wr), //output reg
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.m_ctrlport_req_rd (ctrlport_req_rd), //output reg
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.m_ctrlport_req_addr (ctrlport_req_addr), //output reg[19:0]
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.m_ctrlport_req_portid (), //output wire[9:0]
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.m_ctrlport_req_rem_epid (), //output wire[15:0]
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.m_ctrlport_req_rem_portid(), //output wire[9:0]
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.m_ctrlport_req_data (ctrlport_req_data), //output reg[31:0]
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.m_ctrlport_req_byte_en (ctrlport_req_byte_en), //output reg[3:0]
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.m_ctrlport_req_has_time (), //output wire
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.m_ctrlport_req_time (), //output wire[63:0]
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.m_ctrlport_resp_ack (ctrlport_resp_ack), //input wire
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.m_ctrlport_resp_status (ctrlport_resp_status), //input wire[1:0]
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.m_ctrlport_resp_data (ctrlport_resp_data) //input wire[31:0]
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);
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rfdc_info_memory rfdc_info_memoryx (
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.clk (s_axi_aclk), //input logic
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.rst (~resetn), //input logic
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.s_ctrlport_req_addr (ctrlport_req_addr), //input logic[19:0]
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.s_ctrlport_req_byte_en(ctrlport_req_byte_en), //input logic[3:0]
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.s_ctrlport_req_data (ctrlport_req_data), //input logic[31:0]
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.s_ctrlport_req_rd (ctrlport_req_rd), //input logic
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.s_ctrlport_req_wr (ctrlport_req_wr), //input logic
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.s_ctrlport_resp_ack (ctrlport_resp_ack), //output logic
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.s_ctrlport_resp_data (ctrlport_resp_data), //output logic[31:0]
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.s_ctrlport_resp_status(ctrlport_resp_status) //output logic[1:0]
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);
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endmodule
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