fpga: x4xx: replace ADC/DAC info by RFDC memory
Original-commit: 6c6d52fd655b144aa5ee581edae7911dc734854e
This commit is contained in:
Max Köhler
committed by
Jörg Hofrichter
Jörg Hofrichter
parent
37b8b0d017
commit
50f20ef4ab
@@ -384,126 +384,6 @@
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// </bitfield>
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// </regtype>
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//
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// <regtype name="ADC_TILEMAP_REGTYPE" size="32" writable="false">
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// <info>
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// This register describes how the ADCs map to the respective tiles. It
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// lets us designate an ADC as channel 0, channel 1, etc. depending on
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// how those channels are externally connected to the RFSoC.{BR/}
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//
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// For every channel, this register stores the tile number and the block
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// number of the converter. This can be used to then address the correct
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// converter in the various Xilinx interfaces/APIs.
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// </info>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN0_TILE" range="1..0" initialvalue="0">
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// <info>Tile number of the ADC for channel 0, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN0_BLOCK" range="3..2" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 0, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN1_TILE" range="5..4" initialvalue="0">
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// <info>Tile number of the ADC for channel 1, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN1_BLOCK" range="7..6" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 1, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN2_TILE" range="9..8" initialvalue="0">
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// <info>Tile number of the ADC for channel 2, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN2_BLOCK" range="11..10" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 2, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN3_TILE" range="13..12" initialvalue="0">
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// <info>Tile number of the ADC for channel 3, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN3_BLOCK" range="15..14" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 3, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN0_TILE" range="17..16" initialvalue="0">
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// <info>Tile number of the ADC for channel 0, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN0_BLOCK" range="19..18" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 0, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN1_TILE" range="21..20" initialvalue="0">
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// <info>Tile number of the ADC for channel 1, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN1_BLOCK" range="23..22" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 1, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN2_TILE" range="25..24" initialvalue="0">
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// <info>Tile number of the ADC for channel 2, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN2_BLOCK" range="27..26" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 2, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN3_TILE" range="29..28" initialvalue="0">
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// <info>Tile number of the ADC for channel 3, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN3_BLOCK" range="31..30" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 3, daughterboard 1.</info>
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// </bitfield>
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// </regtype>
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// <regtype name="DAC_TILEMAP_REGTYPE" size="32" writable="false">
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// <info>
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// This register describes how the DACs map to the respective tiles. It
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// lets us designate an DAC as channel 0, channel 1, etc. depending on
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// how those channels are externally connected to the RFSoC.{BR/}
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//
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// For every channel, this register stores the tile number and the block
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// number of the converter. This can be used to then address the correct
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// converter in the various Xilinx interfaces/APIs.
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// </info>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN0_TILE" range="1..0" initialvalue="0">
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// <info>Tile number of the DAC for channel 0, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN0_BLOCK" range="3..2" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 0, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN1_TILE" range="5..4" initialvalue="0">
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// <info>Tile number of the DAC for channel 1, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN1_BLOCK" range="7..6" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 1, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN2_TILE" range="9..8" initialvalue="0">
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// <info>Tile number of the DAC for channel 2, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN2_BLOCK" range="11..10" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 2, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN3_TILE" range="13..12" initialvalue="0">
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// <info>Tile number of the DAC for channel 3, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN3_BLOCK" range="15..14" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 3, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN0_TILE" range="17..16" initialvalue="0">
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// <info>Tile number of the DAC for channel 0, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN0_BLOCK" range="19..18" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 0, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN1_TILE" range="21..20" initialvalue="0">
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// <info>Tile number of the DAC for channel 1, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN1_BLOCK" range="23..22" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 1, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN2_TILE" range="25..24" initialvalue="0">
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// <info>Tile number of the DAC for channel 2, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN2_BLOCK" range="27..26" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 2, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN3_TILE" range="29..28" initialvalue="0">
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// <info>Tile number of the DAC for channel 3, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN3_BLOCK" range="31..30" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 3, daughterboard 1.</info>
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// </bitfield>
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// </regtype>
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//
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//
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// </group>
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//</regmap>
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//XmlParse xml_off
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