diff --git a/lib/ip/Makefile.inc b/lib/ip/Makefile.inc index 0996cac..8814b20 100644 --- a/lib/ip/Makefile.inc +++ b/lib/ip/Makefile.inc @@ -8,6 +8,7 @@ include $(LIB_IP_DIR)/axi_fft/Makefile.inc include $(LIB_IP_DIR)/axi_hb31/Makefile.inc include $(LIB_IP_DIR)/axi_hb47/Makefile.inc include $(LIB_IP_DIR)/complex_to_magphase/Makefile.inc +include $(LIB_IP_DIR)/complex_to_magphase_int17/Makefile.inc include $(LIB_IP_DIR)/complex_to_magphase_int16_int24/Makefile.inc include $(LIB_IP_DIR)/complex_to_magphase_int32/Makefile.inc include $(LIB_IP_DIR)/complex_multiplier/Makefile.inc @@ -28,6 +29,7 @@ $(LIB_IP_AXI_FFT_SRCS) \ $(LIB_IP_AXI_HB31_SRCS) \ $(LIB_IP_AXI_HB47_SRCS) \ $(LIB_IP_COMPLEX_TO_MAGPHASE_SRCS) \ +$(LIB_IP_COMPLEX_TO_MAGPHASE_INT17_SRCS) \ $(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_SRCS) \ $(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_SRCS) \ $(LIB_IP_COMPLEX_MULTIPLIER_SRCS) \ @@ -48,6 +50,7 @@ $(LIB_IP_AXI_FFT_OUTS) \ $(LIB_IP_AXI_HB31_OUTS) \ $(LIB_IP_AXI_HB47_OUTS) \ $(LIB_IP_COMPLEX_TO_MAGPHASE_OUTS) \ +$(LIB_IP_COMPLEX_TO_MAGPHASE_INT17_OUTS) \ $(LIB_IP_COMPLEX_TO_MAGPHASE_INT16_INT24_OUTS) \ $(LIB_IP_COMPLEX_TO_MAGPHASE_INT32_OUTS) \ $(LIB_IP_COMPLEX_MULTIPLIER_OUTS) \ diff --git a/lib/ip/complex_to_magphase_int17/Makefile.inc b/lib/ip/complex_to_magphase_int17/Makefile.inc new file mode 100644 index 0000000..017c3e8 --- /dev/null +++ b/lib/ip/complex_to_magphase_int17/Makefile.inc @@ -0,0 +1,21 @@ +# +# Copyright 2024 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +LIB_IP_COMPLEX_TO_MAGPHASE_INT17_SRCS = $(IP_BUILD_DIR)/complex_to_magphase_int17/complex_to_magphase_int17.xci + +LIB_IP_COMPLEX_TO_MAGPHASE_INT17_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_to_magphase_int17/, \ +complex_to_magphase_int17.xci.out \ +synth/complex_to_magphase_int17.vhd \ +) + +.INTERMEDIATE: LIB_IP_COMPLEX_TO_MAGPHASE_INT17_TRGT +$(LIB_IP_COMPLEX_TO_MAGPHASE_INT17_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_INT17_OUTS): LIB_IP_COMPLEX_TO_MAGPHASE_INT17_TRGT + @: + +LIB_IP_COMPLEX_TO_MAGPHASE_INT17_TRGT: $(LIB_IP_DIR)/complex_to_magphase_int17/complex_to_magphase_int17.xci + $(call BUILD_VIVADO_IP,complex_to_magphase_int17,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0) diff --git a/lib/ip/complex_to_magphase_int17/complex_to_magphase_int17.xci b/lib/ip/complex_to_magphase_int17/complex_to_magphase_int17.xci new file mode 100644 index 0000000..a88c349 --- /dev/null +++ b/lib/ip/complex_to_magphase_int17/complex_to_magphase_int17.xci @@ -0,0 +1,184 @@ + + + xilinx.com + xci + unknown + 1.0 + + + complex_to_magphase_int17 + + + + 1000000 + 0 + 0 + 0.0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.0 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + 2 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 17 + 0 + 48 + 1 + 17 + 1 + -2 + 0 + 2 + 3 + 48 + 1 + 24 + 1 + 2 + 1 + kintex7 + false + true + Parallel + true + Embedded_Multiplier + complex_to_magphase_int17 + SignedFraction + Translate + 17 + 0 + 17 + Scaled_Radians + Maximum + 0 + Round_Pos_Neg_Inf + true + false + 1 + Blocking + Performance + Pass_Cartesian_TLAST + true + false + false + 1 + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 17 + TRUE + . + + . + 2021.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +