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fpga: x400: Connect Radio Blocks to DIO

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Original-commit: 87b2cf09301e90dfaf2a6554c424b62e0558e0b1
This commit is contained in:
Javier Valenzuela
2022-01-25 10:18:47 -07:00
committed by Wade Fife
parent 729d780bd4
commit 4edae39d9e
11 changed files with 627 additions and 232 deletions
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top/x400/doc/X4XX_FPGA_left.htm
+2 -1
View File
@@ -543,7 +543,8 @@
</p>
<div class="sh" id="div_RADIO_CTRLPORT_REGMAP|RADIO_CTRLPORT_WINDOWS">
<p><span class="register" id="a_RADIO_CTRLPORT_REGMAP|DB_WINDOW" onclick="a('RADIO_CTRLPORT_REGMAP|DB_WINDOW');">DB_WINDOW</span></p>
<p><span class="register" id="a_RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW" onclick="a('RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW');">RFDC_TIMING_WINDOW</span></p>
<p><span class="register" id="a_RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW" onclick="a('RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW');">RFDC_TIMING_WINDOW</span></p>
<p><span class="register" id="a_RADIO_CTRLPORT_REGMAP|DIO_WINDOW" onclick="a('RADIO_CTRLPORT_REGMAP|DIO_WINDOW');">DIO_WINDOW</span></p>
</div>
</div>
<p>
top/x400/doc/X4XX_FPGA_right.htm
+177 -11
View File
@@ -3274,7 +3274,7 @@ Total Offset =</td></tr>
</td>
<td class="outercell" rowspan="1">
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIO_MASTER_REGISTER</td></tr>
@@ -3300,6 +3300,38 @@ Total Offset =</td></tr>
</tr>
<tr>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x00C000
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
@@ -3397,7 +3429,7 @@ Sets whether the DIO signal line is driven by this register interface or the use
</td>
<td class="outercell" rowspan="1">
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIO_DIRECTION_REGISTER</td></tr>
@@ -3423,6 +3455,38 @@ Total Offset =</td></tr>
</tr>
<tr>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x00C004
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
@@ -3520,7 +3584,7 @@ Set the direction of FPGA buffer connected to DIO ports on the DIO board.<br/>
</td>
<td class="outercell" rowspan="1">
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIO_INPUT_REGISTER</td></tr>
@@ -3546,6 +3610,38 @@ Total Offset =</td></tr>
</tr>
<tr>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x00C008
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
@@ -3642,7 +3738,7 @@ Status of each bit at the FPGA input.
</td>
<td class="outercell" rowspan="1">
<td class="outercell" rowspan="2">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIO_OUTPUT_REGISTER</td></tr>
@@ -3668,6 +3764,38 @@ Total Offset =</td></tr>
</tr>
<tr>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x00C000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1"></td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x00C00C
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value = 0x00000000
@@ -14357,7 +14485,7 @@ Total Offset =</td></tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file rfdc_timing_control.v.</p>
<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p>
</div>
@@ -14387,7 +14515,7 @@ Daughterboard GPIO interface. Register access within this space
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">RFDC_TIMING_WINDOW</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x8000</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;size=0x8000 (32 Kbytes)</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;size=0x4000 (16 Kbytes)</td></tr>
</table>
</td>
@@ -14396,7 +14524,7 @@ Daughterboard GPIO interface. Register access within this space
</table><p/>
<p class="reg_info">This window is defined in HDL source file rfdc_timing_control.v.</p>
<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p>
</div>
@@ -14406,6 +14534,44 @@ RFDC timing control interface.
</div>
</div>
<div class="register">
<a name="RADIO_CTRLPORT_REGMAP|DIO_WINDOW"></a>
<h3 class="register">Offset 0xC000: DIO_WINDOW Window (R|W)</h3>
<p class="offset_info">&nbsp;&nbsp;Target regmap = <a href="#DIO_REGMAP">DIO_REGMAP</a></p>
<a class="sh_addrs" href="javascript:sa('RADIO_CTRLPORT_REGMAP|DIO_WINDOW_in')">(<span id="show_RADIO_CTRLPORT_REGMAP|DIO_WINDOW_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_RADIO_CTRLPORT_REGMAP|DIO_WINDOW_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">DIO_WINDOW</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0xC000</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;size=0x4000 (16 Kbytes)</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">This window is defined in HDL source file x4xx_core_common.v.</p>
</div>
<div class="info">
DIO control interface
</div>
</div>
</div>
@@ -21627,9 +21793,9 @@ FPGA version.<BR/>
<tr valign="top">
<td class='value'>3</td>
<td class='value'>4</td>
<td class='l'>0x00000003</td>
<td class='l'>0x00000004</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
@@ -21666,9 +21832,9 @@ FPGA version.<BR/>
<tr valign="top">
<td class='value'>553915926</td>
<td class='value'>554176790</td>
<td class='l'>0x21041616</td>
<td class='l'>0x21081116</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME'></a>FPGA_VERSION_LAST_MODIFIED_TIME</p>