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fpga: rfnoc: Add documentation to chdr_xb_routing_table

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Original-commit: 7dc2b620f7cb9dc72b9b77ce9c018823a4015b4e
This commit is contained in:
Wade Fife
2021-10-28 23:15:41 -05:00
parent 78d49a8f0c
commit 4e769632be
1 changed files with 85 additions and 47 deletions
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lib/rfnoc/crossbar/chdr_xb_routing_table.v
+78 -40
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@@ -1,13 +1,31 @@
//
// Copyright 2018 Ettus Research, A National Instruments Company
// Copyright 2021 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: chdr_xb_routing_table
//
// Description:
// A routing table for the CHDR crossbar. This table is designed
// to be shared between all ports. It has an AXI-Stream lookup
// interface and a ctrlport (reduced) configuration interface.
//
// A routing table for the CHDR crossbar. This table is designed to be shared
// between all ports. It has an AXI-Stream lookup interface and two
// simplified ctrlport configuration interfaces, one for crossbar (XB) ports
// and the other for external configuration.
//
// To insert an entry into the routing table, write the desired output port
// number to the EPID address. That is, put the EPID for a route into the
// req_addr field and the corresponding output port number on the req_data
// field.
//
// Parameters:
//
// SIZE : The number entries to support in the routing table.
// NPORTS : The number of output crossbar ports.
// EXT_INS_PORT_EN : Set to 1 to enable the external configuration interface.
//
`default_nettype none
module chdr_xb_routing_table #(
parameter SIZE = 6,
@@ -18,39 +36,43 @@ module chdr_xb_routing_table #(
input wire clk,
input wire reset,
// Insertion Interface (for XB ports)
input wire [NPORTS-1:0] port_req_wr,
input wire [(16*NPORTS)-1:0] port_req_addr,
input wire [(32*NPORTS)-1:0] port_req_data,
output wire [NPORTS-1:0] port_resp_ack,
input wire [ NPORTS-1:0] port_req_wr,
input wire [ (16*NPORTS)-1:0] port_req_addr,
input wire [ (32*NPORTS)-1:0] port_req_data,
output wire [ NPORTS-1:0] port_resp_ack,
// Insertion Interface (External)
input wire ext_req_wr,
input wire [15:0] ext_req_addr,
input wire [31:0] ext_req_data,
input wire [ 15:0] ext_req_addr,
input wire [ 31:0] ext_req_data,
output wire ext_resp_ack,
// Find Interface
input wire [(16*NPORTS)-1:0] axis_find_tdata,
input wire [NPORTS-1:0] axis_find_tvalid,
output wire [NPORTS-1:0] axis_find_tready,
input wire [ (16*NPORTS)-1:0] axis_find_tdata,
input wire [ NPORTS-1:0] axis_find_tvalid,
output wire [ NPORTS-1:0] axis_find_tready,
// Result Interface (for Find)
output wire [($clog2(NPORTS)*NPORTS)-1:0] axis_result_tdata,
output wire [NPORTS-1:0] axis_result_tkeep,
output wire [NPORTS-1:0] axis_result_tvalid,
input wire [NPORTS-1:0] axis_result_tready
output wire [ NPORTS-1:0] axis_result_tkeep,
output wire [ NPORTS-1:0] axis_result_tvalid,
input wire [ NPORTS-1:0] axis_result_tready
);
localparam NPORTS_W = $clog2(NPORTS);
localparam CFG_W = NPORTS_W + 16;
localparam CFG_PORTS = NPORTS + EXT_INS_PORT_EN;
//---------------------------------------------------------------------------
// CAM-based lookup table
//---------------------------------------------------------------------------
wire [15:0] insert_tdest;
wire [ 15:0] insert_tdest;
wire [NPORTS_W-1:0] insert_tdata;
wire insert_tvalid;
wire insert_tready;
axis_muxed_kv_map #(
.KEY_WIDTH(16), .VAL_WIDTH(NPORTS_W),
.SIZE(SIZE), .NUM_PORTS(NPORTS)
.KEY_WIDTH(16 ),
.VAL_WIDTH(NPORTS_W),
.SIZE (SIZE ),
.NUM_PORTS(NPORTS )
) kv_map_i (
.clk (clk ),
.reset (reset ),
@@ -67,35 +89,39 @@ module chdr_xb_routing_table #(
.axis_result_tready(axis_result_tready)
);
// Logic to convert from ctrlport to AXI-Stream
//---------------------------------------------------------------------------
// Logic to convert from CtrlPort to AXI-Stream
//---------------------------------------------------------------------------
wire ins_req_wr [0:CFG_PORTS-1];
wire [15:0] ins_req_addr[0:CFG_PORTS-1];
wire [ 15:0] ins_req_addr[0:CFG_PORTS-1];
wire [NPORTS_W-1:0] ins_req_data[0:CFG_PORTS-1];
wire ins_resp_ack[0:CFG_PORTS-1];
reg [(CFG_PORTS*CFG_W)-1:0] cfg_tdata;
reg [CFG_PORTS-1:0] cfg_tvalid = {CFG_PORTS{1'b0}};
wire [CFG_PORTS-1:0] cfg_tready;
reg [ CFG_PORTS-1:0] cfg_tvalid = {CFG_PORTS{1'b0}};
wire [ CFG_PORTS-1:0] cfg_tready;
genvar i;
generate for (i = 0; i < CFG_PORTS; i=i+1) begin
assign ins_req_wr [i] = (i < NPORTS) ? port_req_wr[i] : ext_req_wr;
generate for (i = 0; i < CFG_PORTS; i=i+1) begin : gen_cfg_ports
assign ins_req_wr[i] = (i < NPORTS) ? port_req_wr[i] : ext_req_wr;
assign ins_req_addr[i] = (i < NPORTS) ? port_req_addr[i*16 +: 16] : ext_req_addr;
assign ins_req_data[i] = (i < NPORTS) ? port_req_data[i*32 +: NPORTS_W] : ext_req_data[NPORTS_W-1:0];
if (i < NPORTS)
assign port_resp_ack[i] = ins_resp_ack[i];
else
assign ext_resp_ack = ins_resp_ack[i];
always @(posedge clk) begin
if (i < NPORTS) begin : gen_port_resp
assign port_resp_ack[i] = ins_resp_ack[i];
end else begin : gen_ext_resp
assign ext_resp_ack = ins_resp_ack[i];
end
always @(posedge clk) begin : cfg_regs
if (reset) begin
cfg_tvalid[i] <= 1'b0;
end else begin
if (~cfg_tvalid[i]) begin
if (ins_req_wr[i]) begin
cfg_tvalid[i] <= 1'b1;
cfg_tdata[(CFG_W*i) +: CFG_W] <= {ins_req_data[i], ins_req_addr[i]};
cfg_tdata[(CFG_W*i)+:CFG_W] <= {ins_req_data[i], ins_req_addr[i]};
end
end else begin
cfg_tvalid[i] <= ~cfg_tready[i];
@@ -105,18 +131,30 @@ module chdr_xb_routing_table #(
assign ins_resp_ack[i] = cfg_tvalid[i] & cfg_tready[i];
end endgenerate
// Multiplexer between XB ports and external cfg
//---------------------------------------------------------------------------
// Multiplexer between XB ports and external configuration
//---------------------------------------------------------------------------
axi_mux #(
.WIDTH(CFG_W), .SIZE(CFG_PORTS),
.PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
) rtcfg_mux_i (
.clk(clk), .reset(reset), .clear(1'b0),
.i_tdata(cfg_tdata), .i_tlast({CFG_PORTS{1'b1}}),
.i_tvalid(cfg_tvalid), .i_tready(cfg_tready),
.o_tdata({insert_tdata, insert_tdest}), .o_tlast(),
.o_tvalid(insert_tvalid), .o_tready(insert_tready)
.WIDTH (CFG_W ),
.SIZE (CFG_PORTS),
.PRE_FIFO_SIZE (0 ),
.POST_FIFO_SIZE(1 )
) axi_mux_i (
.clk (clk ),
.reset (reset ),
.clear (1'b0 ),
.i_tdata (cfg_tdata ),
.i_tlast ({CFG_PORTS{1'b1}} ),
.i_tvalid(cfg_tvalid ),
.i_tready(cfg_tready ),
.o_tdata ({insert_tdata, insert_tdest}),
.o_tlast ( ),
.o_tvalid(insert_tvalid ),
.o_tready(insert_tready )
);
endmodule
`default_nettype wire