fpga: lib: remove reset on non-control signals of ctrlport modules

Original-commit: 8bdca548d1cec4c8ced3edb3c3c2ea7addc4f6e3

lib/rfnoc/utils/ctrlport_combiner.v

@@ -109,15 +109,27 @@ module ctrlport_combiner #(
   reg [   NUM_MASTERS-1:0] req_has_time;
   reg [64*NUM_MASTERS-1:0] req_time;
 
-  always @(posedge ctrlport_clk) begin
+  always @(posedge ctrlport_clk) begin : input_buffer_block
+    integer i;
     if (ctrlport_rst) begin
       req_valid <= 0;
     end else begin : input_reg_gen
-      integer i;
       for (i = 0; i < NUM_MASTERS; i = i + 1) begin
         if (s_ctrlport_req_wr[i] | s_ctrlport_req_rd[i]) begin
           // Mark this slave's request valid and save the request information
           req_valid[i] <= 1'b1;
+        end
+      end
+
+      // Clear the active request when it gets output
+      if (req_load_output) begin
+        req_valid[slave_sel] <= 1'b0;
+      end
+    end
+
+    // Buffer request information without reset
+    for (i = 0; i < NUM_MASTERS; i = i + 1) begin
+      if (s_ctrlport_req_wr[i] | s_ctrlport_req_rd[i]) begin
         req_wr[i]                <= s_ctrlport_req_wr[i];
         req_rd[i]                <= s_ctrlport_req_rd[i];
         req_addr[20*i+:20]       <= s_ctrlport_req_addr[20*i+:20];
@@ -130,12 +142,6 @@ module ctrlport_combiner #(
         req_time[64*i+:64]       <= s_ctrlport_req_time[64*i+:64];
       end
     end
-
-      // Clear the active request when it gets output
-      if (req_load_output) begin
-        req_valid[slave_sel] <= 1'b0;
-      end
-    end
   end
 
 
@@ -217,13 +223,10 @@ module ctrlport_combiner #(
   //
   //---------------------------------------------------------------------------
 
-  always @(posedge ctrlport_clk) begin
-    if (ctrlport_rst) begin
-      m_ctrlport_req_wr <= 1'b0;
-      m_ctrlport_req_rd <= 1'b0;
-    end else begin : output_reg_gen
+  always @(posedge ctrlport_clk) begin : output_reg_gen
     integer i;
 
+    // ---------- Request --------------
     // Load the active request
     if (req_load_output) begin
       m_ctrlport_req_wr         <= req_wr        [slave_sel];
@@ -241,6 +244,12 @@ module ctrlport_combiner #(
       m_ctrlport_req_rd <= 1'b0;
     end
 
+    if (ctrlport_rst) begin
+      m_ctrlport_req_wr <= 1'b0;
+      m_ctrlport_req_rd <= 1'b0;
+    end
+
+    // ---------- Response --------------
     // Output any response to the master that made the request
     for (i = 0; i < NUM_MASTERS; i = i + 1) begin
       // Give the response data to all the slaves (no demux, to save logic)
@@ -248,13 +257,14 @@ module ctrlport_combiner #(
       s_ctrlport_resp_data[32*i +: 32] <= m_ctrlport_resp_data;
 
       // Give the ack only to the master that made the request (use a demux)
-        if (i == slave_sel && m_ctrlport_resp_ack) begin
+      if (ctrlport_rst) begin
+        s_ctrlport_resp_ack[i] <= 1'b0;
+      end else if (i == slave_sel && m_ctrlport_resp_ack) begin
         s_ctrlport_resp_ack[i] <= 1'b1;
       end else begin
         s_ctrlport_resp_ack[i] <= 1'b0;
       end
     end
   end
-  end
 
 endmodule

lib/rfnoc/utils/ctrlport_decoder.v

@@ -101,6 +101,7 @@ module ctrlport_decoder #(
           // Mask WR and RD based on address decoding
           m_ctrlport_req_wr[i] <= s_ctrlport_req_wr & decoder[i];
           m_ctrlport_req_rd[i] <= s_ctrlport_req_rd & decoder[i];
+        end
 
         // Other values pass through to all slaves, but should be ignored
         // unless the corresponding WR or RD is not asserted.
@@ -114,7 +115,6 @@ module ctrlport_decoder #(
         m_ctrlport_req_addr[20*i+:SLAVE_ADDR_W] <= s_ctrlport_req_addr[SLAVE_ADDR_W-1:0];
       end
     end
-    end
   endgenerate
 
 
@@ -144,10 +144,11 @@ module ctrlport_decoder #(
     if (ctrlport_rst) begin
       s_ctrlport_resp_ack  <= 0;
     end else begin
-      s_ctrlport_resp_data   <= data;
-      s_ctrlport_resp_status <= status;
       s_ctrlport_resp_ack  <= ack;
     end
+
+    s_ctrlport_resp_data   <= data;
+    s_ctrlport_resp_status <= status;
   end
 
 endmodule

lib/rfnoc/utils/ctrlport_decoder_param.v

@@ -119,6 +119,7 @@ module ctrlport_decoder_param #(
           // Mask WR and RD based on address decoding
           m_ctrlport_req_wr[i] <= s_ctrlport_req_wr & dec_mask[i];
           m_ctrlport_req_rd[i] <= s_ctrlport_req_rd & dec_mask[i];
+        end
 
         // Other values pass through to all slaves, but should be ignored
         // unless WR or RD is asserted.
@@ -132,7 +133,6 @@ module ctrlport_decoder_param #(
         m_ctrlport_req_addr[20*i +: ADDR_W] <= s_ctrlport_req_addr[ADDR_W-1 : 0];
       end
     end
-    end
   endgenerate
 
   //---------------------------------------------------------------------------
@@ -161,10 +161,11 @@ module ctrlport_decoder_param #(
     if (ctrlport_rst) begin
       s_ctrlport_resp_ack  <= 0;
     end else begin
-      s_ctrlport_resp_data   <= data;
-      s_ctrlport_resp_status <= status;
       s_ctrlport_resp_ack  <= ack;
     end
+
+    s_ctrlport_resp_data   <= data;
+    s_ctrlport_resp_status <= status;
   end
 
 endmodule

lib/rfnoc/utils/ctrlport_gate.v

@@ -52,11 +52,6 @@ module ctrlport_gate (
   `include "../core/ctrlport.vh"
 
   always @(posedge ctrlport_clk) begin
-    if (ctrlport_rst) begin
-      m_ctrlport_req_wr   <= 1'b0;
-      m_ctrlport_req_rd   <= 1'b0;
-      s_ctrlport_resp_ack <= 1'b0;
-    end else begin
     // Forward all signals by default
     m_ctrlport_req_wr         <= s_ctrlport_req_wr;
     m_ctrlport_req_rd         <= s_ctrlport_req_rd;
@@ -73,6 +68,12 @@ module ctrlport_gate (
     s_ctrlport_resp_status <= m_ctrlport_resp_status;
     s_ctrlport_resp_data   <= m_ctrlport_resp_data;
 
+    // Handle reset and disabled case
+    if (ctrlport_rst) begin
+      m_ctrlport_req_wr   <= 1'b0;
+      m_ctrlport_req_rd   <= 1'b0;
+      s_ctrlport_resp_ack <= 1'b0;
+    end else begin
       // Overwrite default assignments in case of disabled interface
       if (m_ctrlport_req_rd || m_ctrlport_req_wr) begin
         if (~enable) begin

lib/rfnoc/utils/ctrlport_resp_combine.v

@@ -40,11 +40,7 @@ module ctrlport_resp_combine #(
   output reg [31:0] s_ctrlport_resp_data
 );
 
-  always @(posedge ctrlport_clk) begin
-    if (ctrlport_rst) begin
-      s_ctrlport_resp_data <= 0;
-      s_ctrlport_resp_ack  <= 0;
-    end else begin : or_reg_resp
+  always @(posedge ctrlport_clk) begin : or_reg_resp
     reg [31:0] data;
     reg [ 1:0] status;
     reg        ack;
@@ -64,6 +60,9 @@ module ctrlport_resp_combine #(
     s_ctrlport_resp_data   <= data;
     s_ctrlport_resp_status <= status;
     s_ctrlport_resp_ack    <= ack;
+
+    if (ctrlport_rst) begin
+      s_ctrlport_resp_ack <= 0;
     end
   end
 

lib/rfnoc/utils/ctrlport_splitter.v

@@ -117,12 +117,12 @@ module ctrlport_splitter #(
 
       // Register the output to break combinatorial path
       always @(posedge ctrlport_clk) begin : response_reg
-        if (ctrlport_rst) begin
-          s_ctrlport_resp_ack  <= 0;
-        end else begin
         s_ctrlport_resp_data   <= data;
         s_ctrlport_resp_status <= status;
         s_ctrlport_resp_ack    <= ack;
+
+        if (ctrlport_rst) begin
+          s_ctrlport_resp_ack  <= 0;
         end
       end
     end