From 4d4b06dfac12b465f57852b9e8cd14e4cb8920b6 Mon Sep 17 00:00:00 2001
From: Martin Braun <martin.braun@ettus.com>
Date: Wed, 16 Nov 2022 11:34:05 +0100
Subject: [PATCH] fpga: Cosmetic changes to rx_frontend_gen3_tb

- Add different signal types
- Default to real/constant
- Minor cleanup


Original-commit: 0624d6c6452fa47c47bb33abc1eb8ef935cfcf1f
---
 .../rx_frontend_gen3_tb.sv                    | 35 ++++++++++++++-----
 1 file changed, 26 insertions(+), 9 deletions(-)

diff --git a/lib/rfnoc/blocks/rfnoc_block_radio/rx_frontend_gen3_tb/rx_frontend_gen3_tb.sv b/lib/rfnoc/blocks/rfnoc_block_radio/rx_frontend_gen3_tb/rx_frontend_gen3_tb.sv
index 7e18875..711ffe7 100644
--- a/lib/rfnoc/blocks/rfnoc_block_radio/rx_frontend_gen3_tb/rx_frontend_gen3_tb.sv
+++ b/lib/rfnoc/blocks/rfnoc_block_radio/rx_frontend_gen3_tb/rx_frontend_gen3_tb.sv
@@ -101,6 +101,11 @@ module rx_frontend_gen3_tb;
   // Input Generator
   //---------------------------------------------------------------------------
 
+  enum {
+    SIGTYPE_REAL,   // Real-valued sinusoid
+    SIGTYPE_CPLX,   // Complex-valued sinusoid
+    SIGTYPE_CNST    // Constant signal (real-valued)
+  } sigtype_state;
 
   real amplitude = 0.4375;               // Pick your favorite amplitude < 1.0
   real test_freq = CLK_FREQUENCY / 80.0; // Pick a frequency < CLK_FREQUENCY
@@ -113,14 +118,27 @@ module rx_frontend_gen3_tb;
 
   initial begin : gen_input
     count = 0;
+    sigtype_state = SIGTYPE_CPLX;
     forever begin
       clk_gen.clk_wait_r();
       if (rst) begin
         count = 0;
         continue;
       end
-      adc_i <= fp_amp * $cos(2.0*PI*f_norm*count);
-      adc_q <= fp_amp * $sin(2.0*PI*f_norm*count);
+      case (sigtype_state)
+        SIGTYPE_REAL: begin
+          adc_i <= fp_amp * $cos(2.0*PI*f_norm*count);
+          adc_q <= 0;
+        end
+        SIGTYPE_CPLX: begin
+          adc_i <= fp_amp * $cos(2.0*PI*f_norm*count);
+          adc_q <= fp_amp * $sin(2.0*PI*f_norm*count);
+        end
+        SIGTYPE_CNST: begin
+          adc_i <= fp_amp;
+          adc_q <= 0;
+        end
+      endcase
       count++;
     end
   end : gen_input
@@ -145,8 +163,6 @@ module rx_frontend_gen3_tb;
   //---------------------------------------------------------------------------
 
   initial begin : tb_main
-    string tb_name;
-
     // Initialize the test exec object for this testbench
     test.start_tb("rx_frontend_gen3_tb");
 
@@ -162,11 +178,13 @@ module rx_frontend_gen3_tb;
     @rst;
     test.end_test();
 
-    //--------------------------------
-    // Initialize Registers
-    //--------------------------------
+    //-------------------------------------------------------------------------
+    // Initialize Registers: TwinRX mode
+    // - No IQ/DC offset corrections
+    // - Enable 1/4-rate downconverter
+    //-------------------------------------------------------------------------
 
-    test.start_test("Initialize registers", 10us);
+    test.start_test("Initialize registers (TwinRX mode)", 10us);
 
     // Set IQ mapping (Enable down-conversion)
     sr_write(SR_IQ_MAPPING, DOWNCONVERT);
@@ -205,5 +223,4 @@ module rx_frontend_gen3_tb;
 
 endmodule : rx_frontend_gen3_tb
 
-
 `default_nettype wire