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fpga: n3xx: Add missing BIST image core headers

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Original-commit: 958eab7ea804337bd904c119427d363a05aa5cf6
This commit is contained in:
Wade Fife
2022-03-29 14:45:04 -05:00
parent 61ee0ddec3
commit 4784032014
6 changed files with 108 additions and 45 deletions
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top/n3xx/n300_bist_image_core.v
+15 -15
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@@ -1,5 +1,5 @@
// //
// Copyright 2021 Ettus Research, A National Instruments Brand // Copyright 2022 Ettus Research, A National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2021-05-03T08:51:04.740210 // File generated on: 2022-03-28T12:13:45.033343
// Source: n300_bist_image_core.yml // Source: n300_bist_image_core.yml
// Source SHA256: 209edc7c95f0a9fd8b96b6d10a40849f3ee84e5fc85a37696cc7510cd74c4af6 // Source SHA256: 2e3de3488c19ed292d6d48c0591d1a39b04772f29b4f47a445fc4f8ab6475613
// //
`default_nettype none `default_nettype none
@@ -61,7 +61,7 @@ module rfnoc_image_core #(
// dram // dram
input wire [ 0:0] axi_rst, input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid, output wire [ 3:0] m_axi_awid,
output wire [ 127:0] m_axi_awaddr, output wire [ 191:0] m_axi_awaddr,
output wire [ 31:0] m_axi_awlen, output wire [ 31:0] m_axi_awlen,
output wire [ 11:0] m_axi_awsize, output wire [ 11:0] m_axi_awsize,
output wire [ 7:0] m_axi_awburst, output wire [ 7:0] m_axi_awburst,
@@ -73,8 +73,8 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_awuser, output wire [ 3:0] m_axi_awuser,
output wire [ 3:0] m_axi_awvalid, output wire [ 3:0] m_axi_awvalid,
input wire [ 3:0] m_axi_awready, input wire [ 3:0] m_axi_awready,
output wire [ 255:0] m_axi_wdata, output wire [2047:0] m_axi_wdata,
output wire [ 31:0] m_axi_wstrb, output wire [ 255:0] m_axi_wstrb,
output wire [ 3:0] m_axi_wlast, output wire [ 3:0] m_axi_wlast,
output wire [ 3:0] m_axi_wuser, output wire [ 3:0] m_axi_wuser,
output wire [ 3:0] m_axi_wvalid, output wire [ 3:0] m_axi_wvalid,
@@ -85,7 +85,7 @@ module rfnoc_image_core #(
input wire [ 3:0] m_axi_bvalid, input wire [ 3:0] m_axi_bvalid,
output wire [ 3:0] m_axi_bready, output wire [ 3:0] m_axi_bready,
output wire [ 3:0] m_axi_arid, output wire [ 3:0] m_axi_arid,
output wire [ 127:0] m_axi_araddr, output wire [ 191:0] m_axi_araddr,
output wire [ 31:0] m_axi_arlen, output wire [ 31:0] m_axi_arlen,
output wire [ 11:0] m_axi_arsize, output wire [ 11:0] m_axi_arsize,
output wire [ 7:0] m_axi_arburst, output wire [ 7:0] m_axi_arburst,
@@ -98,7 +98,7 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_arvalid, output wire [ 3:0] m_axi_arvalid,
input wire [ 3:0] m_axi_arready, input wire [ 3:0] m_axi_arready,
input wire [ 3:0] m_axi_rid, input wire [ 3:0] m_axi_rid,
input wire [ 255:0] m_axi_rdata, input wire [2047:0] m_axi_rdata,
input wire [ 7:0] m_axi_rresp, input wire [ 7:0] m_axi_rresp,
input wire [ 3:0] m_axi_rlast, input wire [ 3:0] m_axi_rlast,
input wire [ 3:0] m_axi_ruser, input wire [ 3:0] m_axi_ruser,
@@ -674,7 +674,7 @@ module rfnoc_image_core #(
// axi_ram // axi_ram
wire [ 0:0] fifo0_axi_rst; wire [ 0:0] fifo0_axi_rst;
wire [ 3:0] fifo0_m_axi_awid; wire [ 3:0] fifo0_m_axi_awid;
wire [ 127:0] fifo0_m_axi_awaddr; wire [ 191:0] fifo0_m_axi_awaddr;
wire [ 31:0] fifo0_m_axi_awlen; wire [ 31:0] fifo0_m_axi_awlen;
wire [ 11:0] fifo0_m_axi_awsize; wire [ 11:0] fifo0_m_axi_awsize;
wire [ 7:0] fifo0_m_axi_awburst; wire [ 7:0] fifo0_m_axi_awburst;
@@ -686,8 +686,8 @@ module rfnoc_image_core #(
wire [ 3:0] fifo0_m_axi_awuser; wire [ 3:0] fifo0_m_axi_awuser;
wire [ 3:0] fifo0_m_axi_awvalid; wire [ 3:0] fifo0_m_axi_awvalid;
wire [ 3:0] fifo0_m_axi_awready; wire [ 3:0] fifo0_m_axi_awready;
wire [ 255:0] fifo0_m_axi_wdata; wire [2047:0] fifo0_m_axi_wdata;
wire [ 31:0] fifo0_m_axi_wstrb; wire [ 255:0] fifo0_m_axi_wstrb;
wire [ 3:0] fifo0_m_axi_wlast; wire [ 3:0] fifo0_m_axi_wlast;
wire [ 3:0] fifo0_m_axi_wuser; wire [ 3:0] fifo0_m_axi_wuser;
wire [ 3:0] fifo0_m_axi_wvalid; wire [ 3:0] fifo0_m_axi_wvalid;
@@ -698,7 +698,7 @@ module rfnoc_image_core #(
wire [ 3:0] fifo0_m_axi_bvalid; wire [ 3:0] fifo0_m_axi_bvalid;
wire [ 3:0] fifo0_m_axi_bready; wire [ 3:0] fifo0_m_axi_bready;
wire [ 3:0] fifo0_m_axi_arid; wire [ 3:0] fifo0_m_axi_arid;
wire [ 127:0] fifo0_m_axi_araddr; wire [ 191:0] fifo0_m_axi_araddr;
wire [ 31:0] fifo0_m_axi_arlen; wire [ 31:0] fifo0_m_axi_arlen;
wire [ 11:0] fifo0_m_axi_arsize; wire [ 11:0] fifo0_m_axi_arsize;
wire [ 7:0] fifo0_m_axi_arburst; wire [ 7:0] fifo0_m_axi_arburst;
@@ -711,7 +711,7 @@ module rfnoc_image_core #(
wire [ 3:0] fifo0_m_axi_arvalid; wire [ 3:0] fifo0_m_axi_arvalid;
wire [ 3:0] fifo0_m_axi_arready; wire [ 3:0] fifo0_m_axi_arready;
wire [ 3:0] fifo0_m_axi_rid; wire [ 3:0] fifo0_m_axi_rid;
wire [ 255:0] fifo0_m_axi_rdata; wire [2047:0] fifo0_m_axi_rdata;
wire [ 7:0] fifo0_m_axi_rresp; wire [ 7:0] fifo0_m_axi_rresp;
wire [ 3:0] fifo0_m_axi_rlast; wire [ 3:0] fifo0_m_axi_rlast;
wire [ 3:0] fifo0_m_axi_ruser; wire [ 3:0] fifo0_m_axi_ruser;
@@ -724,8 +724,8 @@ module rfnoc_image_core #(
.NUM_PORTS (4), .NUM_PORTS (4),
.MEM_DATA_W (64), .MEM_DATA_W (64),
.MEM_ADDR_W (31), .MEM_ADDR_W (31),
.FIFO_ADDR_BASE ({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}), .FIFO_ADDR_BASE ({31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}),
.FIFO_ADDR_MASK ({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}), .FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}),
.MEM_CLK_RATE (303819444), .MEM_CLK_RATE (303819444),
.MTU (MTU) .MTU (MTU)
) b_fifo0_1 ( ) b_fifo0_1 (
top/n3xx/n300_bist_image_core.vh
+21
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@@ -0,0 +1,21 @@
//
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for n300)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2022-03-28T12:13:45.065455
// Source: n300_bist_image_core.yml
// Source SHA256: 2e3de3488c19ed292d6d48c0591d1a39b04772f29b4f47a445fc4f8ab6475613
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/n3xx/n310_bist_image_core.v
+15 -15
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@@ -1,5 +1,5 @@
// //
// Copyright 2021 Ettus Research, A National Instruments Brand // Copyright 2022 Ettus Research, A National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2021-05-03T08:51:05.500549 // File generated on: 2022-03-28T12:13:45.473664
// Source: n310_bist_image_core.yml // Source: n310_bist_image_core.yml
// Source SHA256: fe5a985fa2e6edde671a8fb818d11a583d818a74f707df9bb107901060780eea // Source SHA256: 5aef8b31192d245541e1f27905e7ca42e645035f4582bca26ee760fd2f26c335
// //
`default_nettype none `default_nettype none
@@ -79,7 +79,7 @@ module rfnoc_image_core #(
// dram // dram
input wire [ 0:0] axi_rst, input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid, output wire [ 3:0] m_axi_awid,
output wire [ 127:0] m_axi_awaddr, output wire [ 191:0] m_axi_awaddr,
output wire [ 31:0] m_axi_awlen, output wire [ 31:0] m_axi_awlen,
output wire [ 11:0] m_axi_awsize, output wire [ 11:0] m_axi_awsize,
output wire [ 7:0] m_axi_awburst, output wire [ 7:0] m_axi_awburst,
@@ -91,8 +91,8 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_awuser, output wire [ 3:0] m_axi_awuser,
output wire [ 3:0] m_axi_awvalid, output wire [ 3:0] m_axi_awvalid,
input wire [ 3:0] m_axi_awready, input wire [ 3:0] m_axi_awready,
output wire [ 255:0] m_axi_wdata, output wire [2047:0] m_axi_wdata,
output wire [ 31:0] m_axi_wstrb, output wire [ 255:0] m_axi_wstrb,
output wire [ 3:0] m_axi_wlast, output wire [ 3:0] m_axi_wlast,
output wire [ 3:0] m_axi_wuser, output wire [ 3:0] m_axi_wuser,
output wire [ 3:0] m_axi_wvalid, output wire [ 3:0] m_axi_wvalid,
@@ -103,7 +103,7 @@ module rfnoc_image_core #(
input wire [ 3:0] m_axi_bvalid, input wire [ 3:0] m_axi_bvalid,
output wire [ 3:0] m_axi_bready, output wire [ 3:0] m_axi_bready,
output wire [ 3:0] m_axi_arid, output wire [ 3:0] m_axi_arid,
output wire [ 127:0] m_axi_araddr, output wire [ 191:0] m_axi_araddr,
output wire [ 31:0] m_axi_arlen, output wire [ 31:0] m_axi_arlen,
output wire [ 11:0] m_axi_arsize, output wire [ 11:0] m_axi_arsize,
output wire [ 7:0] m_axi_arburst, output wire [ 7:0] m_axi_arburst,
@@ -116,7 +116,7 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_arvalid, output wire [ 3:0] m_axi_arvalid,
input wire [ 3:0] m_axi_arready, input wire [ 3:0] m_axi_arready,
input wire [ 3:0] m_axi_rid, input wire [ 3:0] m_axi_rid,
input wire [ 255:0] m_axi_rdata, input wire [2047:0] m_axi_rdata,
input wire [ 7:0] m_axi_rresp, input wire [ 7:0] m_axi_rresp,
input wire [ 3:0] m_axi_rlast, input wire [ 3:0] m_axi_rlast,
input wire [ 3:0] m_axi_ruser, input wire [ 3:0] m_axi_ruser,
@@ -931,7 +931,7 @@ module rfnoc_image_core #(
// axi_ram // axi_ram
wire [ 0:0] fifo0_axi_rst; wire [ 0:0] fifo0_axi_rst;
wire [ 3:0] fifo0_m_axi_awid; wire [ 3:0] fifo0_m_axi_awid;
wire [ 127:0] fifo0_m_axi_awaddr; wire [ 191:0] fifo0_m_axi_awaddr;
wire [ 31:0] fifo0_m_axi_awlen; wire [ 31:0] fifo0_m_axi_awlen;
wire [ 11:0] fifo0_m_axi_awsize; wire [ 11:0] fifo0_m_axi_awsize;
wire [ 7:0] fifo0_m_axi_awburst; wire [ 7:0] fifo0_m_axi_awburst;
@@ -943,8 +943,8 @@ module rfnoc_image_core #(
wire [ 3:0] fifo0_m_axi_awuser; wire [ 3:0] fifo0_m_axi_awuser;
wire [ 3:0] fifo0_m_axi_awvalid; wire [ 3:0] fifo0_m_axi_awvalid;
wire [ 3:0] fifo0_m_axi_awready; wire [ 3:0] fifo0_m_axi_awready;
wire [ 255:0] fifo0_m_axi_wdata; wire [2047:0] fifo0_m_axi_wdata;
wire [ 31:0] fifo0_m_axi_wstrb; wire [ 255:0] fifo0_m_axi_wstrb;
wire [ 3:0] fifo0_m_axi_wlast; wire [ 3:0] fifo0_m_axi_wlast;
wire [ 3:0] fifo0_m_axi_wuser; wire [ 3:0] fifo0_m_axi_wuser;
wire [ 3:0] fifo0_m_axi_wvalid; wire [ 3:0] fifo0_m_axi_wvalid;
@@ -955,7 +955,7 @@ module rfnoc_image_core #(
wire [ 3:0] fifo0_m_axi_bvalid; wire [ 3:0] fifo0_m_axi_bvalid;
wire [ 3:0] fifo0_m_axi_bready; wire [ 3:0] fifo0_m_axi_bready;
wire [ 3:0] fifo0_m_axi_arid; wire [ 3:0] fifo0_m_axi_arid;
wire [ 127:0] fifo0_m_axi_araddr; wire [ 191:0] fifo0_m_axi_araddr;
wire [ 31:0] fifo0_m_axi_arlen; wire [ 31:0] fifo0_m_axi_arlen;
wire [ 11:0] fifo0_m_axi_arsize; wire [ 11:0] fifo0_m_axi_arsize;
wire [ 7:0] fifo0_m_axi_arburst; wire [ 7:0] fifo0_m_axi_arburst;
@@ -968,7 +968,7 @@ module rfnoc_image_core #(
wire [ 3:0] fifo0_m_axi_arvalid; wire [ 3:0] fifo0_m_axi_arvalid;
wire [ 3:0] fifo0_m_axi_arready; wire [ 3:0] fifo0_m_axi_arready;
wire [ 3:0] fifo0_m_axi_rid; wire [ 3:0] fifo0_m_axi_rid;
wire [ 255:0] fifo0_m_axi_rdata; wire [2047:0] fifo0_m_axi_rdata;
wire [ 7:0] fifo0_m_axi_rresp; wire [ 7:0] fifo0_m_axi_rresp;
wire [ 3:0] fifo0_m_axi_rlast; wire [ 3:0] fifo0_m_axi_rlast;
wire [ 3:0] fifo0_m_axi_ruser; wire [ 3:0] fifo0_m_axi_ruser;
@@ -981,8 +981,8 @@ module rfnoc_image_core #(
.NUM_PORTS (4), .NUM_PORTS (4),
.MEM_DATA_W (64), .MEM_DATA_W (64),
.MEM_ADDR_W (31), .MEM_ADDR_W (31),
.FIFO_ADDR_BASE ({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}), .FIFO_ADDR_BASE ({31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}),
.FIFO_ADDR_MASK ({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}), .FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}),
.MEM_CLK_RATE (303819444), .MEM_CLK_RATE (303819444),
.MTU (MTU) .MTU (MTU)
) b_fifo0_2 ( ) b_fifo0_2 (
top/n3xx/n310_bist_image_core.vh
+21
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@@ -0,0 +1,21 @@
//
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for n310)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2022-03-28T12:13:45.506549
// Source: n310_bist_image_core.yml
// Source SHA256: 5aef8b31192d245541e1f27905e7ca42e645035f4582bca26ee760fd2f26c335
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/n3xx/n320_bist_image_core.v
+15 -15
View File
@@ -1,5 +1,5 @@
// //
// Copyright 2021 Ettus Research, A National Instruments Brand // Copyright 2022 Ettus Research, A National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool. // This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// //
// File generated on: 2021-05-03T08:51:06.226381 // File generated on: 2022-03-28T12:13:45.909428
// Source: n320_bist_image_core.yml // Source: n320_bist_image_core.yml
// Source SHA256: d384cf18372dd4b674466793e7cf30abeb4f3ef658d466be7007a9b7b8af7241 // Source SHA256: aca3751d49ba6f7564282ae55c6368b2cfa11abd1a8abd77af3f4d5cf498e67b
// //
`default_nettype none `default_nettype none
@@ -79,7 +79,7 @@ module rfnoc_image_core #(
// dram // dram
input wire [ 0:0] axi_rst, input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid, output wire [ 3:0] m_axi_awid,
output wire [ 127:0] m_axi_awaddr, output wire [ 191:0] m_axi_awaddr,
output wire [ 31:0] m_axi_awlen, output wire [ 31:0] m_axi_awlen,
output wire [ 11:0] m_axi_awsize, output wire [ 11:0] m_axi_awsize,
output wire [ 7:0] m_axi_awburst, output wire [ 7:0] m_axi_awburst,
@@ -91,8 +91,8 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_awuser, output wire [ 3:0] m_axi_awuser,
output wire [ 3:0] m_axi_awvalid, output wire [ 3:0] m_axi_awvalid,
input wire [ 3:0] m_axi_awready, input wire [ 3:0] m_axi_awready,
output wire [ 255:0] m_axi_wdata, output wire [2047:0] m_axi_wdata,
output wire [ 31:0] m_axi_wstrb, output wire [ 255:0] m_axi_wstrb,
output wire [ 3:0] m_axi_wlast, output wire [ 3:0] m_axi_wlast,
output wire [ 3:0] m_axi_wuser, output wire [ 3:0] m_axi_wuser,
output wire [ 3:0] m_axi_wvalid, output wire [ 3:0] m_axi_wvalid,
@@ -103,7 +103,7 @@ module rfnoc_image_core #(
input wire [ 3:0] m_axi_bvalid, input wire [ 3:0] m_axi_bvalid,
output wire [ 3:0] m_axi_bready, output wire [ 3:0] m_axi_bready,
output wire [ 3:0] m_axi_arid, output wire [ 3:0] m_axi_arid,
output wire [ 127:0] m_axi_araddr, output wire [ 191:0] m_axi_araddr,
output wire [ 31:0] m_axi_arlen, output wire [ 31:0] m_axi_arlen,
output wire [ 11:0] m_axi_arsize, output wire [ 11:0] m_axi_arsize,
output wire [ 7:0] m_axi_arburst, output wire [ 7:0] m_axi_arburst,
@@ -116,7 +116,7 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_arvalid, output wire [ 3:0] m_axi_arvalid,
input wire [ 3:0] m_axi_arready, input wire [ 3:0] m_axi_arready,
input wire [ 3:0] m_axi_rid, input wire [ 3:0] m_axi_rid,
input wire [ 255:0] m_axi_rdata, input wire [2047:0] m_axi_rdata,
input wire [ 7:0] m_axi_rresp, input wire [ 7:0] m_axi_rresp,
input wire [ 3:0] m_axi_rlast, input wire [ 3:0] m_axi_rlast,
input wire [ 3:0] m_axi_ruser, input wire [ 3:0] m_axi_ruser,
@@ -777,7 +777,7 @@ module rfnoc_image_core #(
// axi_ram // axi_ram
wire [ 0:0] fifo0_axi_rst; wire [ 0:0] fifo0_axi_rst;
wire [ 3:0] fifo0_m_axi_awid; wire [ 3:0] fifo0_m_axi_awid;
wire [ 127:0] fifo0_m_axi_awaddr; wire [ 191:0] fifo0_m_axi_awaddr;
wire [ 31:0] fifo0_m_axi_awlen; wire [ 31:0] fifo0_m_axi_awlen;
wire [ 11:0] fifo0_m_axi_awsize; wire [ 11:0] fifo0_m_axi_awsize;
wire [ 7:0] fifo0_m_axi_awburst; wire [ 7:0] fifo0_m_axi_awburst;
@@ -789,8 +789,8 @@ module rfnoc_image_core #(
wire [ 3:0] fifo0_m_axi_awuser; wire [ 3:0] fifo0_m_axi_awuser;
wire [ 3:0] fifo0_m_axi_awvalid; wire [ 3:0] fifo0_m_axi_awvalid;
wire [ 3:0] fifo0_m_axi_awready; wire [ 3:0] fifo0_m_axi_awready;
wire [ 255:0] fifo0_m_axi_wdata; wire [2047:0] fifo0_m_axi_wdata;
wire [ 31:0] fifo0_m_axi_wstrb; wire [ 255:0] fifo0_m_axi_wstrb;
wire [ 3:0] fifo0_m_axi_wlast; wire [ 3:0] fifo0_m_axi_wlast;
wire [ 3:0] fifo0_m_axi_wuser; wire [ 3:0] fifo0_m_axi_wuser;
wire [ 3:0] fifo0_m_axi_wvalid; wire [ 3:0] fifo0_m_axi_wvalid;
@@ -801,7 +801,7 @@ module rfnoc_image_core #(
wire [ 3:0] fifo0_m_axi_bvalid; wire [ 3:0] fifo0_m_axi_bvalid;
wire [ 3:0] fifo0_m_axi_bready; wire [ 3:0] fifo0_m_axi_bready;
wire [ 3:0] fifo0_m_axi_arid; wire [ 3:0] fifo0_m_axi_arid;
wire [ 127:0] fifo0_m_axi_araddr; wire [ 191:0] fifo0_m_axi_araddr;
wire [ 31:0] fifo0_m_axi_arlen; wire [ 31:0] fifo0_m_axi_arlen;
wire [ 11:0] fifo0_m_axi_arsize; wire [ 11:0] fifo0_m_axi_arsize;
wire [ 7:0] fifo0_m_axi_arburst; wire [ 7:0] fifo0_m_axi_arburst;
@@ -814,7 +814,7 @@ module rfnoc_image_core #(
wire [ 3:0] fifo0_m_axi_arvalid; wire [ 3:0] fifo0_m_axi_arvalid;
wire [ 3:0] fifo0_m_axi_arready; wire [ 3:0] fifo0_m_axi_arready;
wire [ 3:0] fifo0_m_axi_rid; wire [ 3:0] fifo0_m_axi_rid;
wire [ 255:0] fifo0_m_axi_rdata; wire [2047:0] fifo0_m_axi_rdata;
wire [ 7:0] fifo0_m_axi_rresp; wire [ 7:0] fifo0_m_axi_rresp;
wire [ 3:0] fifo0_m_axi_rlast; wire [ 3:0] fifo0_m_axi_rlast;
wire [ 3:0] fifo0_m_axi_ruser; wire [ 3:0] fifo0_m_axi_ruser;
@@ -827,8 +827,8 @@ module rfnoc_image_core #(
.NUM_PORTS (4), .NUM_PORTS (4),
.MEM_DATA_W (64), .MEM_DATA_W (64),
.MEM_ADDR_W (31), .MEM_ADDR_W (31),
.FIFO_ADDR_BASE ({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}), .FIFO_ADDR_BASE ({31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}),
.FIFO_ADDR_MASK ({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}), .FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}),
.MEM_CLK_RATE (303819444), .MEM_CLK_RATE (303819444),
.MTU (MTU) .MTU (MTU)
) b_fifo0_2 ( ) b_fifo0_2 (
top/n3xx/n320_bist_image_core.vh
+21
View File
@@ -0,0 +1,21 @@
//
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for n320)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2022-03-28T12:13:45.942402
// Source: n320_bist_image_core.yml
// Source SHA256: aca3751d49ba6f7564282ae55c6368b2cfa11abd1a8abd77af3f4d5cf498e67b
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }