fpga: n3xx: Add missing BIST image core headers
Original-commit: 958eab7ea804337bd904c119427d363a05aa5cf6
This commit is contained in:
Wade Fife
@@ -1,5 +1,5 @@
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//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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// Copyright 2022 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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@@ -13,9 +13,9 @@
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// File generated on: 2021-05-03T08:51:04.740210
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// File generated on: 2022-03-28T12:13:45.033343
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// Source: n300_bist_image_core.yml
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// Source SHA256: 209edc7c95f0a9fd8b96b6d10a40849f3ee84e5fc85a37696cc7510cd74c4af6
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// Source SHA256: 2e3de3488c19ed292d6d48c0591d1a39b04772f29b4f47a445fc4f8ab6475613
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//
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`default_nettype none
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@@ -61,7 +61,7 @@ module rfnoc_image_core #(
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// dram
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input wire [ 0:0] axi_rst,
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output wire [ 3:0] m_axi_awid,
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output wire [ 127:0] m_axi_awaddr,
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output wire [ 191:0] m_axi_awaddr,
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output wire [ 31:0] m_axi_awlen,
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output wire [ 11:0] m_axi_awsize,
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output wire [ 7:0] m_axi_awburst,
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@@ -73,8 +73,8 @@ module rfnoc_image_core #(
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output wire [ 3:0] m_axi_awuser,
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output wire [ 3:0] m_axi_awvalid,
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input wire [ 3:0] m_axi_awready,
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output wire [ 255:0] m_axi_wdata,
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output wire [ 31:0] m_axi_wstrb,
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output wire [2047:0] m_axi_wdata,
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output wire [ 255:0] m_axi_wstrb,
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output wire [ 3:0] m_axi_wlast,
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output wire [ 3:0] m_axi_wuser,
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output wire [ 3:0] m_axi_wvalid,
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@@ -85,7 +85,7 @@ module rfnoc_image_core #(
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input wire [ 3:0] m_axi_bvalid,
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output wire [ 3:0] m_axi_bready,
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output wire [ 3:0] m_axi_arid,
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output wire [ 127:0] m_axi_araddr,
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output wire [ 191:0] m_axi_araddr,
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output wire [ 31:0] m_axi_arlen,
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output wire [ 11:0] m_axi_arsize,
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output wire [ 7:0] m_axi_arburst,
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@@ -98,7 +98,7 @@ module rfnoc_image_core #(
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output wire [ 3:0] m_axi_arvalid,
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input wire [ 3:0] m_axi_arready,
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input wire [ 3:0] m_axi_rid,
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input wire [ 255:0] m_axi_rdata,
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input wire [2047:0] m_axi_rdata,
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input wire [ 7:0] m_axi_rresp,
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input wire [ 3:0] m_axi_rlast,
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input wire [ 3:0] m_axi_ruser,
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@@ -674,7 +674,7 @@ module rfnoc_image_core #(
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// axi_ram
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wire [ 0:0] fifo0_axi_rst;
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wire [ 3:0] fifo0_m_axi_awid;
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wire [ 127:0] fifo0_m_axi_awaddr;
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wire [ 191:0] fifo0_m_axi_awaddr;
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wire [ 31:0] fifo0_m_axi_awlen;
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wire [ 11:0] fifo0_m_axi_awsize;
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wire [ 7:0] fifo0_m_axi_awburst;
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@@ -686,8 +686,8 @@ module rfnoc_image_core #(
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wire [ 3:0] fifo0_m_axi_awuser;
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wire [ 3:0] fifo0_m_axi_awvalid;
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wire [ 3:0] fifo0_m_axi_awready;
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wire [ 255:0] fifo0_m_axi_wdata;
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wire [ 31:0] fifo0_m_axi_wstrb;
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wire [2047:0] fifo0_m_axi_wdata;
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wire [ 255:0] fifo0_m_axi_wstrb;
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wire [ 3:0] fifo0_m_axi_wlast;
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wire [ 3:0] fifo0_m_axi_wuser;
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wire [ 3:0] fifo0_m_axi_wvalid;
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@@ -698,7 +698,7 @@ module rfnoc_image_core #(
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wire [ 3:0] fifo0_m_axi_bvalid;
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wire [ 3:0] fifo0_m_axi_bready;
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wire [ 3:0] fifo0_m_axi_arid;
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wire [ 127:0] fifo0_m_axi_araddr;
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wire [ 191:0] fifo0_m_axi_araddr;
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wire [ 31:0] fifo0_m_axi_arlen;
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wire [ 11:0] fifo0_m_axi_arsize;
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wire [ 7:0] fifo0_m_axi_arburst;
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@@ -711,7 +711,7 @@ module rfnoc_image_core #(
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wire [ 3:0] fifo0_m_axi_arvalid;
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wire [ 3:0] fifo0_m_axi_arready;
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wire [ 3:0] fifo0_m_axi_rid;
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wire [ 255:0] fifo0_m_axi_rdata;
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wire [2047:0] fifo0_m_axi_rdata;
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wire [ 7:0] fifo0_m_axi_rresp;
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wire [ 3:0] fifo0_m_axi_rlast;
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wire [ 3:0] fifo0_m_axi_ruser;
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@@ -724,8 +724,8 @@ module rfnoc_image_core #(
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.NUM_PORTS (4),
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.MEM_DATA_W (64),
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.MEM_ADDR_W (31),
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.FIFO_ADDR_BASE ({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}),
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.FIFO_ADDR_MASK ({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}),
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.FIFO_ADDR_BASE ({31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}),
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.FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}),
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.MEM_CLK_RATE (303819444),
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.MTU (MTU)
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) b_fifo0_1 (
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@@ -0,0 +1,21 @@
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//
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// Copyright 2022 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Header: rfnoc_image_core.vh (for n300)
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//
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// Description:
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//
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// This is the header file for the RFNoC Image Core.
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//
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// File generated on: 2022-03-28T12:13:45.065455
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// Source: n300_bist_image_core.yml
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// Source SHA256: 2e3de3488c19ed292d6d48c0591d1a39b04772f29b4f47a445fc4f8ab6475613
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//
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`define CHDR_WIDTH 64
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`define RFNOC_PROTOVER { 8'd1, 8'd0 }
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@@ -1,5 +1,5 @@
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//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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// Copyright 2022 Ettus Research, A National Instruments Brand
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||||
//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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@@ -13,9 +13,9 @@
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||||
// This file was automatically generated by the RFNoC image builder tool.
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||||
// Re-running that tool will overwrite this file!
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||||
//
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||||
// File generated on: 2021-05-03T08:51:05.500549
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// File generated on: 2022-03-28T12:13:45.473664
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// Source: n310_bist_image_core.yml
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// Source SHA256: fe5a985fa2e6edde671a8fb818d11a583d818a74f707df9bb107901060780eea
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// Source SHA256: 5aef8b31192d245541e1f27905e7ca42e645035f4582bca26ee760fd2f26c335
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//
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`default_nettype none
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@@ -79,7 +79,7 @@ module rfnoc_image_core #(
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// dram
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input wire [ 0:0] axi_rst,
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output wire [ 3:0] m_axi_awid,
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output wire [ 127:0] m_axi_awaddr,
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output wire [ 191:0] m_axi_awaddr,
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output wire [ 31:0] m_axi_awlen,
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output wire [ 11:0] m_axi_awsize,
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output wire [ 7:0] m_axi_awburst,
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@@ -91,8 +91,8 @@ module rfnoc_image_core #(
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output wire [ 3:0] m_axi_awuser,
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output wire [ 3:0] m_axi_awvalid,
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input wire [ 3:0] m_axi_awready,
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output wire [ 255:0] m_axi_wdata,
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output wire [ 31:0] m_axi_wstrb,
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output wire [2047:0] m_axi_wdata,
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output wire [ 255:0] m_axi_wstrb,
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output wire [ 3:0] m_axi_wlast,
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output wire [ 3:0] m_axi_wuser,
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output wire [ 3:0] m_axi_wvalid,
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@@ -103,7 +103,7 @@ module rfnoc_image_core #(
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input wire [ 3:0] m_axi_bvalid,
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output wire [ 3:0] m_axi_bready,
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output wire [ 3:0] m_axi_arid,
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output wire [ 127:0] m_axi_araddr,
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output wire [ 191:0] m_axi_araddr,
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output wire [ 31:0] m_axi_arlen,
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output wire [ 11:0] m_axi_arsize,
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output wire [ 7:0] m_axi_arburst,
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@@ -116,7 +116,7 @@ module rfnoc_image_core #(
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output wire [ 3:0] m_axi_arvalid,
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input wire [ 3:0] m_axi_arready,
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input wire [ 3:0] m_axi_rid,
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input wire [ 255:0] m_axi_rdata,
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input wire [2047:0] m_axi_rdata,
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input wire [ 7:0] m_axi_rresp,
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input wire [ 3:0] m_axi_rlast,
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input wire [ 3:0] m_axi_ruser,
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@@ -931,7 +931,7 @@ module rfnoc_image_core #(
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// axi_ram
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wire [ 0:0] fifo0_axi_rst;
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wire [ 3:0] fifo0_m_axi_awid;
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wire [ 127:0] fifo0_m_axi_awaddr;
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wire [ 191:0] fifo0_m_axi_awaddr;
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wire [ 31:0] fifo0_m_axi_awlen;
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wire [ 11:0] fifo0_m_axi_awsize;
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wire [ 7:0] fifo0_m_axi_awburst;
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@@ -943,8 +943,8 @@ module rfnoc_image_core #(
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wire [ 3:0] fifo0_m_axi_awuser;
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wire [ 3:0] fifo0_m_axi_awvalid;
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wire [ 3:0] fifo0_m_axi_awready;
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wire [ 255:0] fifo0_m_axi_wdata;
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wire [ 31:0] fifo0_m_axi_wstrb;
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wire [2047:0] fifo0_m_axi_wdata;
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wire [ 255:0] fifo0_m_axi_wstrb;
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wire [ 3:0] fifo0_m_axi_wlast;
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wire [ 3:0] fifo0_m_axi_wuser;
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wire [ 3:0] fifo0_m_axi_wvalid;
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@@ -955,7 +955,7 @@ module rfnoc_image_core #(
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wire [ 3:0] fifo0_m_axi_bvalid;
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wire [ 3:0] fifo0_m_axi_bready;
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wire [ 3:0] fifo0_m_axi_arid;
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wire [ 127:0] fifo0_m_axi_araddr;
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wire [ 191:0] fifo0_m_axi_araddr;
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wire [ 31:0] fifo0_m_axi_arlen;
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wire [ 11:0] fifo0_m_axi_arsize;
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wire [ 7:0] fifo0_m_axi_arburst;
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@@ -968,7 +968,7 @@ module rfnoc_image_core #(
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wire [ 3:0] fifo0_m_axi_arvalid;
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wire [ 3:0] fifo0_m_axi_arready;
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wire [ 3:0] fifo0_m_axi_rid;
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wire [ 255:0] fifo0_m_axi_rdata;
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wire [2047:0] fifo0_m_axi_rdata;
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wire [ 7:0] fifo0_m_axi_rresp;
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wire [ 3:0] fifo0_m_axi_rlast;
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wire [ 3:0] fifo0_m_axi_ruser;
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@@ -981,8 +981,8 @@ module rfnoc_image_core #(
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.NUM_PORTS (4),
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.MEM_DATA_W (64),
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.MEM_ADDR_W (31),
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.FIFO_ADDR_BASE ({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}),
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.FIFO_ADDR_MASK ({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}),
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.FIFO_ADDR_BASE ({31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}),
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.FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}),
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.MEM_CLK_RATE (303819444),
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.MTU (MTU)
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) b_fifo0_2 (
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@@ -0,0 +1,21 @@
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//
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// Copyright 2022 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Header: rfnoc_image_core.vh (for n310)
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//
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// Description:
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//
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// This is the header file for the RFNoC Image Core.
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||||
//
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||||
// This file was automatically generated by the RFNoC image builder tool.
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||||
// Re-running that tool will overwrite this file!
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||||
//
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||||
// File generated on: 2022-03-28T12:13:45.506549
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// Source: n310_bist_image_core.yml
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// Source SHA256: 5aef8b31192d245541e1f27905e7ca42e645035f4582bca26ee760fd2f26c335
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//
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`define CHDR_WIDTH 64
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`define RFNOC_PROTOVER { 8'd1, 8'd0 }
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@@ -1,5 +1,5 @@
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//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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// Copyright 2022 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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||||
@@ -13,9 +13,9 @@
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||||
// This file was automatically generated by the RFNoC image builder tool.
|
||||
// Re-running that tool will overwrite this file!
|
||||
//
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||||
// File generated on: 2021-05-03T08:51:06.226381
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// File generated on: 2022-03-28T12:13:45.909428
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// Source: n320_bist_image_core.yml
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// Source SHA256: d384cf18372dd4b674466793e7cf30abeb4f3ef658d466be7007a9b7b8af7241
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// Source SHA256: aca3751d49ba6f7564282ae55c6368b2cfa11abd1a8abd77af3f4d5cf498e67b
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//
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`default_nettype none
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@@ -79,7 +79,7 @@ module rfnoc_image_core #(
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// dram
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input wire [ 0:0] axi_rst,
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output wire [ 3:0] m_axi_awid,
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||||
output wire [ 127:0] m_axi_awaddr,
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output wire [ 191:0] m_axi_awaddr,
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||||
output wire [ 31:0] m_axi_awlen,
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output wire [ 11:0] m_axi_awsize,
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output wire [ 7:0] m_axi_awburst,
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@@ -91,8 +91,8 @@ module rfnoc_image_core #(
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output wire [ 3:0] m_axi_awuser,
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output wire [ 3:0] m_axi_awvalid,
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input wire [ 3:0] m_axi_awready,
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output wire [ 255:0] m_axi_wdata,
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output wire [ 31:0] m_axi_wstrb,
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output wire [2047:0] m_axi_wdata,
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output wire [ 255:0] m_axi_wstrb,
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output wire [ 3:0] m_axi_wlast,
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output wire [ 3:0] m_axi_wuser,
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output wire [ 3:0] m_axi_wvalid,
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@@ -103,7 +103,7 @@ module rfnoc_image_core #(
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input wire [ 3:0] m_axi_bvalid,
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output wire [ 3:0] m_axi_bready,
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output wire [ 3:0] m_axi_arid,
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output wire [ 127:0] m_axi_araddr,
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output wire [ 191:0] m_axi_araddr,
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output wire [ 31:0] m_axi_arlen,
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output wire [ 11:0] m_axi_arsize,
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output wire [ 7:0] m_axi_arburst,
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@@ -116,7 +116,7 @@ module rfnoc_image_core #(
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output wire [ 3:0] m_axi_arvalid,
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input wire [ 3:0] m_axi_arready,
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input wire [ 3:0] m_axi_rid,
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input wire [ 255:0] m_axi_rdata,
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input wire [2047:0] m_axi_rdata,
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input wire [ 7:0] m_axi_rresp,
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input wire [ 3:0] m_axi_rlast,
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input wire [ 3:0] m_axi_ruser,
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@@ -777,7 +777,7 @@ module rfnoc_image_core #(
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// axi_ram
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wire [ 0:0] fifo0_axi_rst;
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wire [ 3:0] fifo0_m_axi_awid;
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wire [ 127:0] fifo0_m_axi_awaddr;
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wire [ 191:0] fifo0_m_axi_awaddr;
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wire [ 31:0] fifo0_m_axi_awlen;
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wire [ 11:0] fifo0_m_axi_awsize;
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wire [ 7:0] fifo0_m_axi_awburst;
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@@ -789,8 +789,8 @@ module rfnoc_image_core #(
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wire [ 3:0] fifo0_m_axi_awuser;
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wire [ 3:0] fifo0_m_axi_awvalid;
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wire [ 3:0] fifo0_m_axi_awready;
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wire [ 255:0] fifo0_m_axi_wdata;
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wire [ 31:0] fifo0_m_axi_wstrb;
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wire [2047:0] fifo0_m_axi_wdata;
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wire [ 255:0] fifo0_m_axi_wstrb;
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wire [ 3:0] fifo0_m_axi_wlast;
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wire [ 3:0] fifo0_m_axi_wuser;
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wire [ 3:0] fifo0_m_axi_wvalid;
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@@ -801,7 +801,7 @@ module rfnoc_image_core #(
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wire [ 3:0] fifo0_m_axi_bvalid;
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wire [ 3:0] fifo0_m_axi_bready;
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wire [ 3:0] fifo0_m_axi_arid;
|
||||
wire [ 127:0] fifo0_m_axi_araddr;
|
||||
wire [ 191:0] fifo0_m_axi_araddr;
|
||||
wire [ 31:0] fifo0_m_axi_arlen;
|
||||
wire [ 11:0] fifo0_m_axi_arsize;
|
||||
wire [ 7:0] fifo0_m_axi_arburst;
|
||||
@@ -814,7 +814,7 @@ module rfnoc_image_core #(
|
||||
wire [ 3:0] fifo0_m_axi_arvalid;
|
||||
wire [ 3:0] fifo0_m_axi_arready;
|
||||
wire [ 3:0] fifo0_m_axi_rid;
|
||||
wire [ 255:0] fifo0_m_axi_rdata;
|
||||
wire [2047:0] fifo0_m_axi_rdata;
|
||||
wire [ 7:0] fifo0_m_axi_rresp;
|
||||
wire [ 3:0] fifo0_m_axi_rlast;
|
||||
wire [ 3:0] fifo0_m_axi_ruser;
|
||||
@@ -827,8 +827,8 @@ module rfnoc_image_core #(
|
||||
.NUM_PORTS (4),
|
||||
.MEM_DATA_W (64),
|
||||
.MEM_ADDR_W (31),
|
||||
.FIFO_ADDR_BASE ({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}),
|
||||
.FIFO_ADDR_MASK ({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}),
|
||||
.FIFO_ADDR_BASE ({31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}),
|
||||
.FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}),
|
||||
.MEM_CLK_RATE (303819444),
|
||||
.MTU (MTU)
|
||||
) b_fifo0_2 (
|
||||
|
||||
@@ -0,0 +1,21 @@
|
||||
//
|
||||
// Copyright 2022 Ettus Research, A National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Header: rfnoc_image_core.vh (for n320)
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This is the header file for the RFNoC Image Core.
|
||||
//
|
||||
// This file was automatically generated by the RFNoC image builder tool.
|
||||
// Re-running that tool will overwrite this file!
|
||||
//
|
||||
// File generated on: 2022-03-28T12:13:45.942402
|
||||
// Source: n320_bist_image_core.yml
|
||||
// Source SHA256: aca3751d49ba6f7564282ae55c6368b2cfa11abd1a8abd77af3f4d5cf498e67b
|
||||
//
|
||||
|
||||
`define CHDR_WIDTH 64
|
||||
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
|
||||
Reference in New Issue
Block a user