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fpga: e320: Connect CTRL_IN pins to FPGA

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These pins control hardware-controlled fast-lock for tuning or
cycle-accurate gain control. This commit does nothing to these pins
other than expose them into the design and assign them to zero. This
does not change the current behaviour (the motherboard has pull-downs on
these pins, so they're low by default).


Original-commit: c891f2d8738bc1b73bb92d88623f4760f9e2bd1e
This commit is contained in:
Martin Braun
2022-01-10 08:46:56 -06:00
committed by Wade Fife
parent 5b75fcbd9a
commit 471173f245
2 changed files with 12 additions and 1 deletions
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top/e320/e320.v
+4
View File
@@ -157,6 +157,7 @@ module e320 (
output wire XCVR_ENA_AGC,
output wire XCVR_RESET_N,
input wire [7:0] XCVR_CTRL_OUT,
output wire [3:0] XCVR_CTRL_IN,
// Amplifiers
output wire TX_HFAMP1_ENA,
@@ -1844,5 +1845,8 @@ module e320 (
.device_id(device_id)
);
// Control pins to AD9361 will lay low for now
assign XCVR_CTRL_IN = 4'h0;
endmodule // e320
`default_nettype wire
top/e320/mb_pins.xdc
+7
View File
@@ -154,6 +154,13 @@ set_property IOSTANDARD LVCMOS18 [get_ports {XCVR_CTRL_OUT[*]}]
set_property PULLUP TRUE [get_ports {XCVR_CTRL_OUT[6]}]
set_property PULLUP TRUE [get_ports {XCVR_CTRL_OUT[7]}]
# CTRL_IN, Bank 13, 1.8 V
set_property PACKAGE_PIN U24 [get_ports {XCVR_CTRL_IN[0]}]
set_property PACKAGE_PIN V24 [get_ports {XCVR_CTRL_IN[1]}]
set_property PACKAGE_PIN V23 [get_ports {XCVR_CTRL_IN[2]}]
set_property PACKAGE_PIN W24 [get_ports {XCVR_CTRL_IN[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {XCVR_CTRL_IN[*]}]
## RX/TX LEDs, Bank 10, 3.3 V
set_property PACKAGE_PIN AG14 [get_ports {RX1_GRN_ENA}]
set_property PACKAGE_PIN AG17 [get_ports {RX2_GRN_ENA}]