fpga: e320: Connect CTRL_IN pins to FPGA

These pins control hardware-controlled fast-lock for tuning or
cycle-accurate gain control. This commit does nothing to these pins
other than expose them into the design and assign them to zero. This
does not change the current behaviour (the motherboard has pull-downs on
these pins, so they're low by default).


Original-commit: c891f2d8738bc1b73bb92d88623f4760f9e2bd1e

top/e320/e320.v

@@ -156,7 +156,8 @@ module e320 (
   output wire XCVR_TXNRX,
   output wire XCVR_ENA_AGC,
   output wire XCVR_RESET_N,
-  input wire [7:0] XCVR_CTRL_OUT,
+  input  wire [7:0] XCVR_CTRL_OUT,
+  output wire [3:0] XCVR_CTRL_IN,
 
   // Amplifiers
   output wire TX_HFAMP1_ENA,
@@ -1844,5 +1845,8 @@ module e320 (
     .device_id(device_id)
   );
 
+  // Control pins to AD9361 will lay low for now
+  assign XCVR_CTRL_IN = 4'h0;
+
 endmodule // e320
 `default_nettype wire