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fpga: lib: add generic to disable bitq engine tri-stating

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Original-commit: b067b2af7924aa8577a8619f97d54122e0b71daf
This commit is contained in:
Max Köhler
2020-09-16 14:24:16 -05:00
committed by Wade Fife
parent f1d3374e50
commit 42d17bd090
2 changed files with 16 additions and 11 deletions
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lib/vivado_ipi/axi_bitq/axi_bitq.vhd
+3
View File
@@ -202,6 +202,9 @@ begin
bitq_rstn <= '0' when (S_AXI_ARESETN = '0') or (bitq_soft_rst = '1') else '1';
bitq_ctrl : entity bitq_fsm
generic map (
IDLE_VALUE => 'Z'
)
port map (
clk => S_AXI_ACLK,
rstn => S_AXI_ARESETN,
lib/vivado_ipi/axi_bitq/bitq_fsm.vhd
+9 -7
View File
@@ -12,6 +12,9 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bitq_fsm is
generic (
IDLE_VALUE : std_logic := 'Z'
);
port (
clk : in std_logic;
rstn : in std_logic;
@@ -27,7 +30,6 @@ port (
wr_data : in std_logic_vector(31 downto 0);
stb_data : in std_logic_vector(31 downto 0);
rd_data : out std_logic_vector(31 downto 0)
);
end bitq_fsm;
@@ -51,9 +53,9 @@ begin
begin
case (bitq_state) is
when IDLE =>
bit_clk <= 'Z';
bit_out <= 'Z';
bit_stb <= 'Z';
bit_clk <= IDLE_VALUE;
bit_out <= IDLE_VALUE;
bit_stb <= IDLE_VALUE;
ready <= '1';
when LOW =>
bit_clk <= '0';
@@ -66,9 +68,9 @@ begin
bit_stb <= bit_stb_r;
ready <= '0';
when others =>
bit_clk <= 'Z';
bit_out <= 'Z';
bit_stb <= 'Z';
bit_clk <= IDLE_VALUE;
bit_out <= IDLE_VALUE;
bit_stb <= IDLE_VALUE;
ready <= '1';
end case;
end process;