fpga: n320: Add BIST (AA) image files

This adds new image files which come with a DRAM FIFO. The addition of
an N320 image with a DRAM FIFO allows DDR3 BIST to be run on an
assembled (motherboard + daughterboard) N320.

This image is intentionally very similar to the N300_AA and N310_AA
targets which serve the same purpose of providing an image with a DRAM
FIFO for their respective devices.


Original-commit: ae2b9bf7aeea6f8f98f6dacffdfc018d87107927

top/n3xx/Makefile

@@ -39,6 +39,7 @@ N310_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n310_rfnoc_image_core.v DEFAULT_EDG
 N320_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n320_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath n320_static_router.hex)
 N300AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n300_bist_image_core.v DEFAULT_EDGE_FILE=$(abspath n300_bist_static_router.hex)
 N310AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n310_bist_image_core.v DEFAULT_EDGE_FILE=$(abspath n310_bist_static_router.hex)
+N320AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n320_bist_image_core.v DEFAULT_EDGE_FILE=$(abspath n320_bist_static_router.hex)
 
 # Set build option (check RTL, run synthesis, or do a full build)
 ifndef TARGET
@@ -162,6 +163,11 @@ N320_AQ: build/usrp_n320_fpga_AQ.dts
 	$(call vivado_build,N320,$(AQ_DEFS) N320=1,$(N320_DEFAULTS))
 	$(call post_build,N320,AQ)
 
+##N320_AA:  Aurora on SFP+ Port0, Aurora on SFP+ Port1.
+N320_AA: build/usrp_n320_fpga_AA.dts
+	$(call vivado_build,N320,$(AA_DEFS) N320=1,$(N320AA_DEFAULTS))
+	$(call post_build,N320,AA)
+
 build/%.dts: dts/%.dts dts/*.dtsi
 	-mkdir -p build
 	${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<

top/n3xx/dts/usrp_n320_fpga_AA.dts

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (c) 2017 National Instruments Corp
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "n320-fpga.dtsi"
+
+&fpga_full {
+	uio@40004000 {
+		compatible = "usrp-uio";
+		reg = <0x40004000 0x1000>;
+		reg-names = "misc-auro-regs0";
+		status = "okay";
+	};
+
+
+	uio@4000c000 {
+		compatible = "usrp-uio";
+		reg = <0x4000c000 0x1000>;
+		reg-names = "misc-auro-regs1";
+		status = "okay";
+	};
+};
+
+#include "n320-common.dtsi"
+#include "dma-common.dtsi"

top/n3xx/n320_bist_image_core.yml

@@ -0,0 +1,93 @@
+# General parameters
+# -----------------------------------------
+schema: rfnoc_imagebuilder_args         # Identifier for the schema used to validate this file
+copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers
+license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers
+version: 1.0                            # File version
+rfnoc_version: 1.0                      # RFNoC protocol version
+chdr_width: 64                          # Bitwidth of the CHDR bus for this block
+device: 'n320'
+default_target: 'N320_AA'
+
+# A list of all stream endpoints in design
+# ----------------------------------------
+stream_endpoints:
+  ep0:                       # Stream endpoint name
+    ctrl: True                      # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 32768                # Ingress buffer size for data
+  ep1:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 32768                # Ingress buffer size for data
+  # We call the next endpoints 4 and 5 to keep them consistent with the
+  # N310 version of this file
+  ep4:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 32768                # Ingress buffer size for data
+  ep5:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 32768                # Ingress buffer size for data
+
+# A list of all NoC blocks in design
+# ----------------------------------
+noc_blocks:
+  radio0:
+    block_desc: 'radio_1x64.yml'
+  radio1:
+    block_desc: 'radio_1x64.yml'
+  fifo0:
+    block_desc: 'axi_ram_fifo_4x64.yml'
+    parameters:
+      # These parameters match the memory interface on the N3XX
+      NUM_PORTS: 4
+      MEM_DATA_W: 64
+      MEM_ADDR_W: 31
+      FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}"
+      FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}"
+      MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz
+
+# A list of all static connections in design
+# ------------------------------------------
+# Format: A list of connection maps (list of key-value pairs) with the following keys
+#         - srcblk = Source block to connect
+#         - srcport = Port on the source block to connect
+#         - dstblk = Destination block to connect
+#         - dstport = Port on the destination block to connect
+connections:
+  # ep0 to radio0(0) - RF0 TX
+  - { srcblk: ep0,  srcport: out0, dstblk: radio0, dstport: in_0  }
+  # radio0(0) to ep0 - RF0 RX
+  - { srcblk: radio0, srcport: out_0, dstblk: ep0,  dstport: in0  }
+  # ep1 to radio1(0) - RF1 TX
+  - { srcblk: ep1,  srcport: out0, dstblk: radio1, dstport: in_0  }
+  # radio1(0) to ep1 - RF1 RX
+  - { srcblk: radio1, srcport: out_0, dstblk: ep1,  dstport: in0  }
+  # ep4 to fifo0(0)
+  - { srcblk: ep4,   srcport: out0,  dstblk: fifo0, dstport: in_0 }
+  - { srcblk: fifo0, srcport: out_0, dstblk: ep4,   dstport: in0  }
+  # ep5 to fifo0(1)
+  - { srcblk: ep5,   srcport: out0,  dstblk: fifo0, dstport: in_1 }
+  - { srcblk: fifo0, srcport: out_1, dstblk: ep5,   dstport: in0  }
+  # BSP Connections
+  - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 }
+  - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 }
+  - { srcblk: _device_, srcport: radio_ch0, dstblk: radio0, dstport: radio_iface }
+  - { srcblk: _device_, srcport: radio_ch1, dstblk: radio1, dstport: radio_iface }
+  - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper }
+  - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport: time_keeper }
+  - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram }
+
+# A list of all clock domain connections in design
+# ------------------------------------------
+# Format: A list of connection maps (list of key-value pairs) with the following keys
+#         - srcblk  = Source block to connect (Always "_device"_)
+#         - srcport = Clock domain on the source block to connect
+#         - dstblk  = Destination block to connect
+#         - dstport = Clock domain on the destination block to connect
+clk_domains:
+  - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
+  - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
+  - { srcblk: _device_, srcport: dram,  dstblk: fifo0,  dstport: mem   }

top/n3xx/n320_bist_static_router.hex

@@ -0,0 +1,9 @@
+00000008
+00400140
+01400040
+00800180
+01800080
+00c001c0
+01c000c0
+010001c1
+01c10100