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fpga: n320: Add BIST (AA) image files

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This adds new image files which come with a DRAM FIFO. The addition of
an N320 image with a DRAM FIFO allows DDR3 BIST to be run on an
assembled (motherboard + daughterboard) N320.

This image is intentionally very similar to the N300_AA and N310_AA
targets which serve the same purpose of providing an image with a DRAM
FIFO for their respective devices.


Original-commit: ae2b9bf7aeea6f8f98f6dacffdfc018d87107927
This commit is contained in:
steviez
2020-07-31 14:32:54 -05:00
committed by Aaron Rossetto
parent 439c2af5e2
commit 3bbc81bb44
5 changed files with 1148 additions and 0 deletions
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top/n3xx/Makefile
+6
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@@ -39,6 +39,7 @@ N310_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n310_rfnoc_image_core.v DEFAULT_EDG
N320_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n320_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath n320_static_router.hex)
N300AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n300_bist_image_core.v DEFAULT_EDGE_FILE=$(abspath n300_bist_static_router.hex)
N310AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n310_bist_image_core.v DEFAULT_EDGE_FILE=$(abspath n310_bist_static_router.hex)
N320AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n320_bist_image_core.v DEFAULT_EDGE_FILE=$(abspath n320_bist_static_router.hex)
# Set build option (check RTL, run synthesis, or do a full build)
ifndef TARGET
@@ -162,6 +163,11 @@ N320_AQ: build/usrp_n320_fpga_AQ.dts
$(call vivado_build,N320,$(AQ_DEFS) N320=1,$(N320_DEFAULTS))
$(call post_build,N320,AQ)
##N320_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1.
N320_AA: build/usrp_n320_fpga_AA.dts
$(call vivado_build,N320,$(AA_DEFS) N320=1,$(N320AA_DEFAULTS))
$(call post_build,N320,AA)
build/%.dts: dts/%.dts dts/*.dtsi
-mkdir -p build
${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<