fpga: x400: Add x410_400_128_rfnoc_image_core
Original-commit: 13c03d4c2f366b41f5dd526326775a499a21514c
This commit is contained in:
Wade Fife
@@ -53,6 +53,9 @@ X410_X1_200: DEFS += $(QSFP0_10GBE) RFBW_200M=1 DRAM_CH=4*$(D
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X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4_200: DEFS += $(QSFP0_4X10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4_200: DEFS += $(QSFP0_4X10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=0
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X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=0
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X410_X1_400: DEFS += $(QSFP0_10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_XG_400: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_X4_400: DEFS += $(QSFP0_4X10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_C1_400: DEFS += $(QSFP0_100GBE) RFBW_400M=1 DRAM_CH=0
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X410_C1_400: DEFS += $(QSFP0_100GBE) RFBW_400M=1 DRAM_CH=0
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X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_400M=1 DRAM_CH=0
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X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_400M=1 DRAM_CH=0
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@@ -66,6 +69,7 @@ DEFS += $(OPTIONS)
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X410_100_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_100_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_100_static_router.hex)
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X410_100_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_100_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_100_static_router.hex)
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X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
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X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
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X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
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X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
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X410_400_128_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_128_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_128_static_router.hex)
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# Option to stop after RTL elaboration. Use this flag as a synthesis check.
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# Option to stop after RTL elaboration. Use this flag as a synthesis check.
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@@ -110,6 +114,9 @@ vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID
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##X410_X1_200 | 200 MHz | 10 GbE (Lane 0) | None | 64b x 4 Ch
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##X410_X1_200 | 200 MHz | 10 GbE (Lane 0) | None | 64b x 4 Ch
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##X410_XG_200 | 200 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
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##X410_XG_200 | 200 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
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##X410_X4_200 | 200 MHz | 4 x 10 GbE | None | 64b x 4 Ch
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##X410_X4_200 | 200 MHz | 4 x 10 GbE | None | 64b x 4 Ch
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##X410_X1_400 | 400 MHz | 10 GbE (Lane 0) | None | 128b x 4 Ch
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##X410_XG_400 | 400 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 128b x 4 ch
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##X410_X4_400 | 400 MHz | 4 x 10 GbE | None | 128b x 4 Ch
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##X410_C1_400 | 400 MHz | 100 GbE | None | None
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##X410_C1_400 | 400 MHz | 100 GbE | None | None
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##X410_CG_400 | 400 MHz | 100 GbE | 100 GbE | None
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##X410_CG_400 | 400 MHz | 100 GbE | 100 GbE | None
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##* Note: Not all targets are shipped with UHD
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##* Note: Not all targets are shipped with UHD
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@@ -138,6 +145,18 @@ X410_X4_200: build/usrp_x410_fpga_X4_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,X4_200)
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$(call post_build,X410,X4_200)
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X410_X1_400: build/usrp_x410_fpga_X1_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
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$(call post_build,X410,X1_400)
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X410_XG_400: build/usrp_x410_fpga_XG_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
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$(call post_build,X410,XG_400)
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X410_X4_400: build/usrp_x410_fpga_X4_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
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$(call post_build,X410,X4_400)
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X410_C1_400: build/usrp_x410_fpga_C1_400.dts
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X410_C1_400: build/usrp_x410_fpga_C1_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call post_build,X410,C1_400)
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$(call post_build,X410,C1_400)
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,21 @@
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//
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// Copyright 2022 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Header: rfnoc_image_core.vh (for x410)
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//
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// Description:
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//
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// This is the header file for the RFNoC Image Core.
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//
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// File generated on: 2022-03-14T16:50:52.329591
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// Source: ./x410_400_128_rfnoc_image_core.yml
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// Source SHA256: 78673c977afc0a046ef08c3070fd3600aac7ba8918ce79c698731d693678cd85
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//
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`define CHDR_WIDTH 128
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`define RFNOC_PROTOVER { 8'd1, 8'd0 }
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@@ -0,0 +1,118 @@
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# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers
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license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers
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version: '1.0' # File version
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rfnoc_version: '1.0' # RFNoC protocol version
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chdr_width: 128 # Bit width of the CHDR bus for this image
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device: 'x410' # USRP type
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image_core_name: 'x410_400_128' # Name to use for the RFNoC Image Core files
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default_target: 'X410_X4_400' # Default make target
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# A list of all stream endpoints in design
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# ----------------------------------------
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stream_endpoints:
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ep0: # Stream endpoint name
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ctrl: True # Endpoint passes control traffic
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data: True # Endpoint passes data traffic
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buff_size_bytes: 32768 # Stream endpoint buffer size
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ep1:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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ep2:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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ep3:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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ep4:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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ep5:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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ep6:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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ep7:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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# A list of all NoC blocks in design
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# ----------------------------------
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noc_blocks:
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radio0:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 2
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NIPC: RADIO_NIPC
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radio1:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 2
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NIPC: RADIO_NIPC
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replay0:
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block_desc: 'replay.yml'
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parameters:
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NUM_PORTS: 4
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MEM_DATA_W: 128
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MEM_ADDR_W: 32
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# A list of all static connections in design
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# ------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect
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# - srcport = Port on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Port on the destination block to connect
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connections:
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# Daughter Board 0 Radio
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- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
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- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
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- { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
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- { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
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#
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# Daughter Board 1 Radio
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- { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 }
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- { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 }
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- { srcblk: ep3, srcport: out0, dstblk: radio1, dstport: in_1 }
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- { srcblk: radio1, srcport: out_1, dstblk: ep3, dstport: in0 }
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#
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# Replay
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- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
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- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
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- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
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- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
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- { srcblk: ep6, srcport: out0, dstblk: replay0, dstport: in_2 }
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- { srcblk: replay0, srcport: out_2, dstblk: ep6, dstport: in0 }
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- { srcblk: ep7, srcport: out0, dstblk: replay0, dstport: in_3 }
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- { srcblk: replay0, srcport: out_3, dstblk: ep7, dstport: in0 }
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#
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# BSP Connections
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- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
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- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
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- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
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- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
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- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
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- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
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- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
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# A list of all clock domain connections in design
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# ------------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect (Always "_device_")
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# - srcport = Clock domain on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Clock domain on the destination block to connect
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clk_domains:
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- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
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- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
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- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
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@@ -0,0 +1,17 @@
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00000010
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